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GET /api/patches/119622/?format=api
{ "id": 119622, "url": "http://patches.dpdk.org/api/patches/119622/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221109165038.1049-1-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221109165038.1049-1-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221109165038.1049-1-getelson@nvidia.com", "date": "2022-11-09T16:50:38", "name": "net/mlx5: fix port initialization with small LRO", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "06a3da68dd80d9534832c83b3c1e3fe41a3e3292", "submitter": { "id": 1882, "url": "http://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221109165038.1049-1-getelson@nvidia.com/mbox/", "series": [ { "id": 25665, "url": "http://patches.dpdk.org/api/series/25665/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25665", "date": "2022-11-09T16:50:38", "name": "net/mlx5: fix port initialization with small LRO", "version": 1, "mbox": "http://patches.dpdk.org/series/25665/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/119622/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/119622/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8B6BBA034C;\n\tWed, 9 Nov 2022 17:51:11 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 2022840151;\n\tWed, 9 Nov 2022 17:51:11 +0100 (CET)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2086.outbound.protection.outlook.com [40.107.243.86])\n by mails.dpdk.org (Postfix) with ESMTP id 3C1E0400D4;\n Wed, 9 Nov 2022 17:51:09 +0100 (CET)", "from MW4PR03CA0133.namprd03.prod.outlook.com (2603:10b6:303:8c::18)\n by PH7PR12MB7353.namprd12.prod.outlook.com (2603:10b6:510:20c::10)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5791.27; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <matan@nvidia.com>, <rasland@nvidia.com>,\n <stable@dpdk.org>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Subject": "[PATCH] net/mlx5: fix port initialization with small LRO", "Date": "Wed, 9 Nov 2022 18:50:38 +0200", "Message-ID": "<20221109165038.1049-1-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT021:EE_|PH7PR12MB7353:EE_", "X-MS-Office365-Filtering-Correlation-Id": "1563eff5-c205-4bcb-35aa-08dac27298f5", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 18I7ssAy4jyJrAGPDN6lun5DT1T6W76VgiSo8Bg37ZE8yxMB2xauAupJIbz7I+Q77ACBkQoliNsfq9PKSt2hZ6Nk+87JnAh5NmPlkTSLXKBJcdIKeF05Qrom1onE9G21G0mm64eCGBw8WGYJjWUPv3s6WVhxLSzr1BRELrOcDYKlCUlkkhd6Rnb4nnHjPVWXx1Fr27XSBt+v4gzs1Rwb7+lApmN5RMHomPQoZEcQ/nzFDRMfvmy8JlMQkU7PX7WHIWl/Y4e0s9EJHOooP8vYQjStwhtQ4VqlQWnkoQTHEQBF9M3Flc8iUYlUwB+jkuXN2104idRc6iKvIB7j3Hcri0Wb/+G2q9QZCjfDOp2nKlIZCSuNefQg8wBx5NLl3WAudzoe9cITuptZLqX8rPj9N0x6rYMNtEBWkmyJDFaNsvkSRVon1NblAqdC7nyCY9NQOew9RxxlEpetkLzST+cStUzLiStbwotFI179WM9aiI6xIKNyU+i6YEPyo9L7zWn7EO8kLJVqhJHs6jbeEYOFUgDUYtXMM/8y+uMMeLwe+PBzTdzLoS23aj312Be2zE5d55FtnLVxilHarwQYjKUBZvsdOfto1jISKy9j6BuMHGzXn1And1Q5kJ32W3x0OIOTFLc/PSrW5LCVHUZJzDYMKO6wEkqBF45XGjdEu3TNsa71m+wubIKghQvFNI1Yb9PnHVztcsgRcCqMpdkCwluyCG6ajA81nciISeFDCLJWOGHCQIrJP81QJcvuNf6YL7/RHCE+DCMKYWf5evdTwh5cZw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(376002)(396003)(136003)(346002)(39860400002)(451199015)(40470700004)(36840700001)(46966006)(2906002)(5660300002)(8936002)(8676002)(6916009)(54906003)(316002)(41300700001)(70586007)(70206006)(450100002)(36756003)(40480700001)(40460700003)(82310400005)(55016003)(82740400003)(426003)(1076003)(356005)(7636003)(47076005)(86362001)(16526019)(336012)(83380400001)(186003)(36860700001)(2616005)(478600001)(4326008)(107886003)(6666004)(26005)(6286002)(7696005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "09 Nov 2022 16:51:07.3519 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 1563eff5-c205-4bcb-35aa-08dac27298f5", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT021.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB7353", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "If application provided maximal LRO size was less than expected PMD\nminimum, the PMD either crashed with assert, if asserts were enabled,\nor proceeded with port initialization to set port private maximal\nLRO size below supported minimum.\n\nThe patch terminates port start if LRO size\ndoes not match PMD requirements and TCP LRO offload was requested\nat least for one Rx queue.\n\nFixes: 50c00baff763 (\"net/mlx5: limit LRO size to maximum Rx packet\")\n\nCc: stable@dpdk.org\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_rxq.c | 1 -\n drivers/net/mlx5/mlx5_trigger.c | 16 ++++++++++++++++\n 2 files changed, 16 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 0d9d11680b..724cd6c7e6 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -1533,7 +1533,6 @@ mlx5_max_lro_msg_size_adjust(struct rte_eth_dev *dev, uint16_t idx,\n \t MLX5_MAX_TCP_HDR_OFFSET)\n \t\tmax_lro_size -= MLX5_MAX_TCP_HDR_OFFSET;\n \tmax_lro_size = RTE_MIN(max_lro_size, MLX5_MAX_LRO_SIZE);\n-\tMLX5_ASSERT(max_lro_size >= MLX5_LRO_SEG_CHUNK_SIZE);\n \tmax_lro_size /= MLX5_LRO_SEG_CHUNK_SIZE;\n \tif (priv->max_lro_msg_size)\n \t\tpriv->max_lro_msg_size =\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 4b821a1076..71089299b8 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -1167,6 +1167,22 @@ mlx5_dev_start(struct rte_eth_dev *dev)\n \telse\n \t\trte_net_mlx5_dynf_inline_mask = 0;\n \tif (dev->data->nb_rx_queues > 0) {\n+\t\tuint32_t max_lro_msg_size = priv->max_lro_msg_size;\n+\n+\t\tif (max_lro_msg_size < MLX5_LRO_SEG_CHUNK_SIZE) {\n+\t\t\tuint32_t i;\n+\t\t\tstruct mlx5_rxq_priv *rxq;\n+\n+\t\t\tfor (i = 0; i != priv->rxqs_n; ++i) {\n+\t\t\t\trxq = mlx5_rxq_get(dev, i);\n+\t\t\t\tif (rxq && rxq->ctrl && rxq->ctrl->rxq.lro) {\n+\t\t\t\t\tDRV_LOG(ERR, \"port %u invalid max LRO size\",\n+\t\t\t\t\t\tdev->data->port_id);\n+\t\t\t\t\trte_errno = EINVAL;\n+\t\t\t\t\treturn -rte_errno;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n \t\tret = mlx5_dev_configure_rss_reta(dev);\n \t\tif (ret) {\n \t\t\tDRV_LOG(ERR, \"port %u reta config failed: %s\",\n", "prefixes": [] }