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GET /api/patches/118824/?format=api
{ "id": 118824, "url": "http://patches.dpdk.org/api/patches/118824/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221020155749.16643-18-valex@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221020155749.16643-18-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221020155749.16643-18-valex@nvidia.com", "date": "2022-10-20T15:57:47", "name": "[v6,17/18] net/mlx5/hws: Add HWS debug layer", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "80f2a9e9299e861900f7b5cf6656715cf708625a", "submitter": { "id": 2858, "url": "http://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221020155749.16643-18-valex@nvidia.com/mbox/", "series": [ { "id": 25345, "url": "http://patches.dpdk.org/api/series/25345/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25345", "date": "2022-10-20T15:57:30", "name": "net/mlx5: Add HW steering low level support", "version": 6, "mbox": "http://patches.dpdk.org/series/25345/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/118824/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/118824/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 12C3EA0553;\n\tThu, 20 Oct 2022 18:01:22 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 94F7242BD5;\n\tThu, 20 Oct 2022 17:59:52 +0200 (CEST)", "from NAM02-BN1-obe.outbound.protection.outlook.com\n (mail-bn1nam07on2057.outbound.protection.outlook.com [40.107.212.57])\n by mails.dpdk.org (Postfix) with ESMTP id 13CBA427FF\n for <dev@dpdk.org>; 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mx.microsoft.com 1; spf=none (sender ip is\n 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=fail (p=reject sp=reject pct=100) action=oreject\n header.from=nvidia.com; dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=YBalSvz+k8Rxb97TogcGHAO12dF/GXvtygb+BZqeUCI=;\n b=caOQsvfAcsTA7H8oDIFenbTqx8hXC0PVbNSFgulSyBgvg+XekIu8qfHQcw1SRLknygae3VuQS49lWwoBhKt2TsXKgt48arfcHItVMG72XYMrgl6RtKBobH1T7WcH9KjTtFH/PuaLvtqLGeVjHlVg+F0xkYSXj5OAb0XYZW1SuWH8zXClCB3mWjtND4cE5J4FeL4B12QF0cQL5Y74YUkHaLmfwr0tLTmtngxytuAhX50hsUGi7X1HQicIO2gqTRBve6JAokBYGhk/KqkMxyWH0G2ZFQK3mc6H0SHWx6K5Wqa7FBZhxofqmW6O2q8WHc/TafrjYssPdDgxG6K1lsujrg==", "X-MS-Exchange-Authentication-Results": "spf=none (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=fail action=oreject header.from=nvidia.com;", "Received-SPF": "None (protection.outlook.com: nvidia.com does not designate\n permitted sender hosts)", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, Hamdan Igbaria <hamdani@nvidia.com>", "Subject": "[v6 17/18] net/mlx5/hws: Add HWS debug layer", "Date": "Thu, 20 Oct 2022 18:57:47 +0300", "Message-ID": "<20221020155749.16643-18-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221020155749.16643-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221020155749.16643-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT075:EE_|IA1PR12MB6332:EE_", "X-MS-Office365-Filtering-Correlation-Id": "64c8fda8-22f1-4da7-0c31-08dab2b41de2", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 7/yv/xaNv8Ldld3WW2a186tm7yMuc49khu4jbPZJXKt6dm+63/BwaWv0BFyBEeB7l8fS87KN/GWoGxYbBw//nTCt2hd0G3KC0ECYy5zN0sa6U/VWbV0PRCH+Uw8F/khqMehGc4vZfa4JECbcJyl+JLEUyIVtGJQYrgGT4VmwD/ij4nh8qW4NfaGNea/y/cAbG+xXV0jsjjM7aMNlTTCrHl8hfoOExZpinVZFQgru6Oec1uw4m6+WTNpzul8H3jrYs9//v6mW+ad5Vtg6oedSCrO8ffgPo2NxzArHCBA77XTihHlzxqq+HfLlHbIg8gQ/QZWkfZnMTUXEp0W4Pz+WsTI65rI5Qi7cl0uiOn74nLfPAnIWCps6aOFiOYhKfGjnORfTvDHblNRclJb7PmRfi+XEn9AKdjz8ujUBSJiqCCX5itXfzoMPEh8kf8L2+I2bZ+iTRRHSyNA0Y2GxOb0smIb291LMvwF51wcQBRT6PdFZ/moFaKjw+FLE3nAjyozw4xM99Ape3/8kIduye5ku0mkMT4gMsqFF7Y1l/aypkZDzCWm0KGaZ2QkOP7xZ0ubI84at8sjnMB3zyLEzz4/4q0xiDpt9W/MkmGK8BVYejYuxqR5o+nrjP+2PB4coe0PB7XYu8Jp0XYE7VutLZNO8IdZwQkerhQAPlP3cIcxAg0vvmHMvVRunWK6aV2Omz+r9Ira2opgsywgztLBBNe4OrJn4Yrp6osmQBwK8lPorT9hu21qOdH/LBSYn6NkmrKhXbIsKOPVeETCgyHokrKkspQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT075.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB6332", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Hamdan Igbaria <hamdani@nvidia.com>\n\nThe debug layer is used to generate a debug CSV file\ncontaining details of the context, table, matcher, rules\nand other useful debug information.\n\nSigned-off-by: Hamdan Igbaria <hamdani@nvidia.com>\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_debug.c | 462 ++++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_debug.h | 28 ++\n 2 files changed, 490 insertions(+)\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_debug.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_debug.h", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.c b/drivers/net/mlx5/hws/mlx5dr_debug.c\nnew file mode 100644\nindex 0000000000..890a761c48\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_debug.c\n@@ -0,0 +1,462 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#include \"mlx5dr_internal.h\"\n+\n+const char *mlx5dr_debug_action_type_str[] = {\n+\t[MLX5DR_ACTION_TYP_LAST] = \"LAST\",\n+\t[MLX5DR_ACTION_TYP_TNL_L2_TO_L2] = \"TNL_L2_TO_L2\",\n+\t[MLX5DR_ACTION_TYP_L2_TO_TNL_L2] = \"L2_TO_TNL_L2\",\n+\t[MLX5DR_ACTION_TYP_TNL_L3_TO_L2] = \"TNL_L3_TO_L2\",\n+\t[MLX5DR_ACTION_TYP_L2_TO_TNL_L3] = \"L2_TO_TNL_L3\",\n+\t[MLX5DR_ACTION_TYP_DROP] = \"DROP\",\n+\t[MLX5DR_ACTION_TYP_TIR] = \"TIR\",\n+\t[MLX5DR_ACTION_TYP_FT] = \"FT\",\n+\t[MLX5DR_ACTION_TYP_CTR] = \"CTR\",\n+\t[MLX5DR_ACTION_TYP_TAG] = \"TAG\",\n+\t[MLX5DR_ACTION_TYP_MODIFY_HDR] = \"MODIFY_HDR\",\n+\t[MLX5DR_ACTION_TYP_VPORT] = \"VPORT\",\n+\t[MLX5DR_ACTION_TYP_MISS] = \"DEFAULT_MISS\",\n+\t[MLX5DR_ACTION_TYP_POP_VLAN] = \"POP_VLAN\",\n+\t[MLX5DR_ACTION_TYP_PUSH_VLAN] = \"PUSH_VLAN\",\n+\t[MLX5DR_ACTION_TYP_ASO_METER] = \"ASO_METER\",\n+\t[MLX5DR_ACTION_TYP_ASO_CT] = \"ASO_CT\",\n+};\n+\n+static_assert(ARRAY_SIZE(mlx5dr_debug_action_type_str) == MLX5DR_ACTION_TYP_MAX,\n+\t \"Missing mlx5dr_debug_action_type_str\");\n+\n+const char *mlx5dr_debug_action_type_to_str(enum mlx5dr_action_type action_type)\n+{\n+\treturn mlx5dr_debug_action_type_str[action_type];\n+}\n+\n+static int\n+mlx5dr_debug_dump_matcher_template_definer(FILE *f,\n+\t\t\t\t\t struct mlx5dr_match_template *mt)\n+{\n+\tstruct mlx5dr_definer *definer = mt->definer;\n+\tint i, ret;\n+\n+\tret = fprintf(f, \"%d,0x%\" PRIx64 \",0x%\" PRIx64 \",%d,%d,\",\n+\t\t MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_DEFINER,\n+\t\t (uint64_t)(uintptr_t)definer,\n+\t\t (uint64_t)(uintptr_t)mt,\n+\t\t definer->obj->id,\n+\t\t definer->type);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tfor (i = 0; i < DW_SELECTORS; i++) {\n+\t\tret = fprintf(f, \"0x%x%s\", definer->dw_selector[i],\n+\t\t\t (i == DW_SELECTORS - 1) ? \",\" : \"-\");\n+\t\tif (ret < 0) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < BYTE_SELECTORS; i++) {\n+\t\tret = fprintf(f, \"0x%x%s\", definer->byte_selector[i],\n+\t\t\t (i == BYTE_SELECTORS - 1) ? \",\" : \"-\");\n+\t\tif (ret < 0) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < MLX5DR_JUMBO_TAG_SZ; i++) {\n+\t\tret = fprintf(f, \"%02x\", definer->mask.jumbo[i]);\n+\t\tif (ret < 0) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\t}\n+\n+\tret = fprintf(f, \"\\n\");\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mlx5dr_debug_dump_matcher_match_template(FILE *f, struct mlx5dr_matcher *matcher)\n+{\n+\tbool is_root = matcher->tbl->level == MLX5DR_ROOT_LEVEL;\n+\tint i, ret;\n+\n+\tfor (i = 0; i < matcher->num_of_mt; i++) {\n+\t\tstruct mlx5dr_match_template *mt = matcher->mt[i];\n+\n+\t\tret = fprintf(f, \"%d,0x%\" PRIx64 \",0x%\" PRIx64 \",%d,%d\\n\",\n+\t\t\t MLX5DR_DEBUG_RES_TYPE_MATCHER_MATCH_TEMPLATE,\n+\t\t\t (uint64_t)(uintptr_t)mt,\n+\t\t\t (uint64_t)(uintptr_t)matcher,\n+\t\t\t is_root ? 0 : mt->fc_sz,\n+\t\t\t mt->flags);\n+\t\tif (ret < 0) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\n+\t\tif (!is_root) {\n+\t\t\tret = mlx5dr_debug_dump_matcher_template_definer(f, mt);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mlx5dr_debug_dump_matcher_action_template(FILE *f, struct mlx5dr_matcher *matcher)\n+{\n+\tbool is_root = matcher->tbl->level == MLX5DR_ROOT_LEVEL;\n+\tenum mlx5dr_action_type action_type;\n+\tint i, j, ret;\n+\n+\tfor (i = 0; i < matcher->num_of_at; i++) {\n+\t\tstruct mlx5dr_action_template *at = matcher->at[i];\n+\n+\t\tret = fprintf(f, \"%d,0x%\" PRIx64 \",0x%\" PRIx64 \",%d,%d,%d\",\n+\t\t\t MLX5DR_DEBUG_RES_TYPE_MATCHER_ACTION_TEMPLATE,\n+\t\t\t (uint64_t)(uintptr_t)at,\n+\t\t\t (uint64_t)(uintptr_t)matcher,\n+\t\t\t at->only_term ? 0 : 1,\n+\t\t\t is_root ? 0 : at->num_of_action_stes,\n+\t\t\t at->num_actions);\n+\t\tif (ret < 0) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\n+\t\tfor (j = 0; j < at->num_actions; j++) {\n+\t\t\taction_type = at->action_type_arr[j];\n+\t\t\tret = fprintf(f, \",%s\", mlx5dr_debug_action_type_to_str(action_type));\n+\t\t\tif (ret < 0) {\n+\t\t\t\trte_errno = EINVAL;\n+\t\t\t\treturn rte_errno;\n+\t\t\t}\n+\t\t}\n+\n+\t\tfprintf(f, \"\\n\");\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mlx5dr_debug_dump_matcher_attr(FILE *f, struct mlx5dr_matcher *matcher)\n+{\n+\tstruct mlx5dr_matcher_attr *attr = &matcher->attr;\n+\tint ret;\n+\n+\tret = fprintf(f, \"%d,0x%\" PRIx64 \",%d,%d,%d,%d,%d,%d\\n\",\n+\t\t MLX5DR_DEBUG_RES_TYPE_MATCHER_ATTR,\n+\t\t (uint64_t)(uintptr_t)matcher,\n+\t\t attr->priority,\n+\t\t attr->mode,\n+\t\t attr->table.sz_row_log,\n+\t\t attr->table.sz_col_log,\n+\t\t attr->optimize_using_rule_idx,\n+\t\t attr->optimize_flow_src);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mlx5dr_debug_dump_matcher(FILE *f, struct mlx5dr_matcher *matcher)\n+{\n+\tbool is_root = matcher->tbl->level == MLX5DR_ROOT_LEVEL;\n+\tenum mlx5dr_table_type tbl_type = matcher->tbl->type;\n+\tstruct mlx5dr_devx_obj *ste_0, *ste_1 = NULL;\n+\tstruct mlx5dr_pool_chunk *ste;\n+\tstruct mlx5dr_pool *ste_pool;\n+\tint ret;\n+\n+\tret = fprintf(f, \"%d,0x%\" PRIx64 \",0x%\" PRIx64 \",%d,%d,0x%\" PRIx64,\n+\t\t MLX5DR_DEBUG_RES_TYPE_MATCHER,\n+\t\t (uint64_t)(uintptr_t)matcher,\n+\t\t (uint64_t)(uintptr_t)matcher->tbl,\n+\t\t matcher->num_of_mt,\n+\t\t is_root ? 0 : matcher->end_ft->id,\n+\t\t matcher->col_matcher ? (uint64_t)(uintptr_t)matcher->col_matcher : 0);\n+\tif (ret < 0)\n+\t\tgoto out_err;\n+\n+\tste = &matcher->match_ste.ste;\n+\tste_pool = matcher->match_ste.pool;\n+\tif (ste_pool) {\n+\t\tste_0 = mlx5dr_pool_chunk_get_base_devx_obj(ste_pool, ste);\n+\t\tif (tbl_type == MLX5DR_TABLE_TYPE_FDB)\n+\t\t\tste_1 = mlx5dr_pool_chunk_get_base_devx_obj_mirror(ste_pool, ste);\n+\t} else {\n+\t\tste_0 = NULL;\n+\t\tste_1 = NULL;\n+\t}\n+\n+\tret = fprintf(f, \",%d,%d,%d,%d\",\n+\t\t matcher->match_ste.rtc_0 ? matcher->match_ste.rtc_0->id : 0,\n+\t\t ste_0 ? (int)ste_0->id : -1,\n+\t\t matcher->match_ste.rtc_1 ? matcher->match_ste.rtc_1->id : 0,\n+\t\t ste_1 ? (int)ste_1->id : -1);\n+\tif (ret < 0)\n+\t\tgoto out_err;\n+\n+\tste = &matcher->action_ste.ste;\n+\tste_pool = matcher->action_ste.pool;\n+\tif (ste_pool) {\n+\t\tste_0 = mlx5dr_pool_chunk_get_base_devx_obj(ste_pool, ste);\n+\t\tif (tbl_type == MLX5DR_TABLE_TYPE_FDB)\n+\t\t\tste_1 = mlx5dr_pool_chunk_get_base_devx_obj_mirror(ste_pool, ste);\n+\t} else {\n+\t\tste_0 = NULL;\n+\t\tste_1 = NULL;\n+\t}\n+\n+\tret = fprintf(f, \",%d,%d,%d,%d\\n\",\n+\t\t matcher->action_ste.rtc_0 ? matcher->action_ste.rtc_0->id : 0,\n+\t\t ste_0 ? (int)ste_0->id : -1,\n+\t\t matcher->action_ste.rtc_1 ? matcher->action_ste.rtc_1->id : 0,\n+\t\t ste_1 ? (int)ste_1->id : -1);\n+\tif (ret < 0)\n+\t\tgoto out_err;\n+\n+\tret = mlx5dr_debug_dump_matcher_attr(f, matcher);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mlx5dr_debug_dump_matcher_match_template(f, matcher);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mlx5dr_debug_dump_matcher_action_template(f, matcher);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+\n+out_err:\n+\trte_errno = EINVAL;\n+\treturn rte_errno;\n+}\n+\n+static int mlx5dr_debug_dump_table(FILE *f, struct mlx5dr_table *tbl)\n+{\n+\tbool is_root = tbl->level == MLX5DR_ROOT_LEVEL;\n+\tstruct mlx5dr_matcher *matcher;\n+\tint ret;\n+\n+\tret = fprintf(f, \"%d,0x%\" PRIx64 \",0x%\" PRIx64 \",%d,%d,%d,%d\\n\",\n+\t\t MLX5DR_DEBUG_RES_TYPE_TABLE,\n+\t\t (uint64_t)(uintptr_t)tbl,\n+\t\t (uint64_t)(uintptr_t)tbl->ctx,\n+\t\t is_root ? 0 : tbl->ft->id,\n+\t\t tbl->type,\n+\t\t is_root ? 0 : tbl->fw_ft_type,\n+\t\t tbl->level);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tLIST_FOREACH(matcher, &tbl->head, next) {\n+\t\tret = mlx5dr_debug_dump_matcher(f, matcher);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mlx5dr_debug_dump_context_send_engine(FILE *f, struct mlx5dr_context *ctx)\n+{\n+\tstruct mlx5dr_send_engine *send_queue;\n+\tint ret, i, j;\n+\n+\tfor (i = 0; i < (int)ctx->queues; i++) {\n+\t\tsend_queue = &ctx->send_queue[i];\n+\t\tret = fprintf(f, \"%d,0x%\" PRIx64 \",%d,%d,%d,%d,%d,%d,%d,%d,%d\\n\",\n+\t\t\t MLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_ENGINE,\n+\t\t\t (uint64_t)(uintptr_t)ctx,\n+\t\t\t i,\n+\t\t\t send_queue->used_entries,\n+\t\t\t send_queue->th_entries,\n+\t\t\t send_queue->rings,\n+\t\t\t send_queue->num_entries,\n+\t\t\t send_queue->err,\n+\t\t\t send_queue->completed.ci,\n+\t\t\t send_queue->completed.pi,\n+\t\t\t send_queue->completed.mask);\n+\t\tif (ret < 0) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\n+\t\tfor (j = 0; j < MLX5DR_NUM_SEND_RINGS; j++) {\n+\t\t\tstruct mlx5dr_send_ring *send_ring = &send_queue->send_ring[j];\n+\t\t\tstruct mlx5dr_send_ring_cq *cq = &send_ring->send_cq;\n+\t\t\tstruct mlx5dr_send_ring_sq *sq = &send_ring->send_sq;\n+\n+\t\t\tret = fprintf(f, \"%d,0x%\" PRIx64 \",%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\\n\",\n+\t\t\t\t MLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_RING,\n+\t\t\t\t (uint64_t)(uintptr_t)ctx,\n+\t\t\t\t j,\n+\t\t\t\t i,\n+\t\t\t\t cq->cqn,\n+\t\t\t\t cq->cons_index,\n+\t\t\t\t cq->ncqe_mask,\n+\t\t\t\t cq->buf_sz,\n+\t\t\t\t cq->ncqe,\n+\t\t\t\t cq->cqe_log_sz,\n+\t\t\t\t cq->poll_wqe,\n+\t\t\t\t cq->cqe_sz,\n+\t\t\t\t sq->sqn,\n+\t\t\t\t sq->obj->id,\n+\t\t\t\t sq->cur_post,\n+\t\t\t\t sq->buf_mask);\n+\t\t\tif (ret < 0) {\n+\t\t\t\trte_errno = EINVAL;\n+\t\t\t\treturn rte_errno;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mlx5dr_debug_dump_context_caps(FILE *f, struct mlx5dr_context *ctx)\n+{\n+\tstruct mlx5dr_cmd_query_caps *caps = ctx->caps;\n+\tint ret;\n+\n+\tret = fprintf(f, \"%d,0x%\" PRIx64 \",%s,%d,%d,%d,%d,\",\n+\t\t MLX5DR_DEBUG_RES_TYPE_CONTEXT_CAPS,\n+\t\t (uint64_t)(uintptr_t)ctx,\n+\t\t caps->fw_ver,\n+\t\t caps->wqe_based_update,\n+\t\t caps->ste_format,\n+\t\t caps->ste_alloc_log_max,\n+\t\t caps->log_header_modify_argument_max_alloc);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tret = fprintf(f, \"%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\\n\",\n+\t\t caps->flex_protocols,\n+\t\t caps->rtc_reparse_mode,\n+\t\t caps->rtc_index_mode,\n+\t\t caps->ste_alloc_log_gran,\n+\t\t caps->stc_alloc_log_max,\n+\t\t caps->stc_alloc_log_gran,\n+\t\t caps->rtc_log_depth_max,\n+\t\t caps->format_select_gtpu_dw_0,\n+\t\t caps->format_select_gtpu_dw_1,\n+\t\t caps->format_select_gtpu_dw_2,\n+\t\t caps->format_select_gtpu_ext_dw_0,\n+\t\t caps->nic_ft.max_level,\n+\t\t caps->nic_ft.reparse,\n+\t\t caps->fdb_ft.max_level,\n+\t\t caps->fdb_ft.reparse,\n+\t\t caps->log_header_modify_argument_granularity);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mlx5dr_debug_dump_context_attr(FILE *f, struct mlx5dr_context *ctx)\n+{\n+\tint ret;\n+\n+\tret = fprintf(f, \"%u,0x%\" PRIx64 \",%d,%zu,%d\\n\",\n+\t\t MLX5DR_DEBUG_RES_TYPE_CONTEXT_ATTR,\n+\t\t (uint64_t)(uintptr_t)ctx,\n+\t\t ctx->pd_num,\n+\t\t ctx->queues,\n+\t\t ctx->send_queue->num_entries);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mlx5dr_debug_dump_context_info(FILE *f, struct mlx5dr_context *ctx)\n+{\n+\tint ret;\n+\n+\tret = fprintf(f, \"%d,0x%\" PRIx64 \",%d,%s,%s\\n\",\n+\t\t MLX5DR_DEBUG_RES_TYPE_CONTEXT,\n+\t\t (uint64_t)(uintptr_t)ctx,\n+\t\t ctx->flags & MLX5DR_CONTEXT_FLAG_HWS_SUPPORT,\n+\t\t mlx5_glue->get_device_name(ctx->ibv_ctx->device),\n+\t\t DEBUG_VERSION);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tret = mlx5dr_debug_dump_context_attr(f, ctx);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mlx5dr_debug_dump_context_caps(f, ctx);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static int mlx5dr_debug_dump_context(FILE *f, struct mlx5dr_context *ctx)\n+{\n+\tstruct mlx5dr_table *tbl;\n+\tint ret;\n+\n+\tret = mlx5dr_debug_dump_context_info(f, ctx);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mlx5dr_debug_dump_context_send_engine(f, ctx);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tLIST_FOREACH(tbl, &ctx->head, next) {\n+\t\tret = mlx5dr_debug_dump_table(f, tbl);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int mlx5dr_debug_dump(struct mlx5dr_context *ctx, FILE *f)\n+{\n+\tint ret;\n+\n+\tif (!f || !ctx) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tpthread_spin_lock(&ctx->ctrl_lock);\n+\tret = mlx5dr_debug_dump_context(f, ctx);\n+\tpthread_spin_unlock(&ctx->ctrl_lock);\n+\n+\treturn -ret;\n+}\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_debug.h b/drivers/net/mlx5/hws/mlx5dr_debug.h\nnew file mode 100644\nindex 0000000000..cf00170f7d\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_debug.h\n@@ -0,0 +1,28 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#ifndef MLX5DR_DEBUG_H_\n+#define MLX5DR_DEBUG_H_\n+\n+#define DEBUG_VERSION \"1.0.DPDK\"\n+\n+enum mlx5dr_debug_res_type {\n+\tMLX5DR_DEBUG_RES_TYPE_CONTEXT = 4000,\n+\tMLX5DR_DEBUG_RES_TYPE_CONTEXT_ATTR = 4001,\n+\tMLX5DR_DEBUG_RES_TYPE_CONTEXT_CAPS = 4002,\n+\tMLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_ENGINE = 4003,\n+\tMLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_RING = 4004,\n+\n+\tMLX5DR_DEBUG_RES_TYPE_TABLE = 4100,\n+\n+\tMLX5DR_DEBUG_RES_TYPE_MATCHER = 4200,\n+\tMLX5DR_DEBUG_RES_TYPE_MATCHER_ATTR = 4201,\n+\tMLX5DR_DEBUG_RES_TYPE_MATCHER_MATCH_TEMPLATE = 4202,\n+\tMLX5DR_DEBUG_RES_TYPE_MATCHER_ACTION_TEMPLATE = 4204,\n+\tMLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_DEFINER = 4203,\n+};\n+\n+const char *mlx5dr_debug_action_type_to_str(enum mlx5dr_action_type action_type);\n+\n+#endif /* MLX5DR_DEBUG_H_ */\n", "prefixes": [ "v6", "17/18" ] }