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GET /api/patches/118482/?format=api
{ "id": 118482, "url": "http://patches.dpdk.org/api/patches/118482/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221018194131.23006-17-andrew.boyer@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221018194131.23006-17-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221018194131.23006-17-andrew.boyer@amd.com", "date": "2022-10-18T19:41:11", "name": "[v2,16/36] net/ionic: free all buffers during Rx queue stop", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d951941e128f42f26344ca451d61da7d7a743d6a", "submitter": { "id": 2861, "url": "http://patches.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221018194131.23006-17-andrew.boyer@amd.com/mbox/", "series": [ { "id": 25088, "url": "http://patches.dpdk.org/api/series/25088/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25088", "date": "2022-10-11T00:49:57", "name": "net/ionic: updates for 22.11 release", "version": 1, "mbox": "http://patches.dpdk.org/series/25088/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/118482/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/118482/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id CB685A0560;\n\tTue, 18 Oct 2022 21:45:32 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BEEE1410EE;\n\tTue, 18 Oct 2022 21:45:32 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40])\n by mails.dpdk.org (Postfix) with ESMTP id 80B19410EE\n for <dev@dpdk.org>; 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helo=SATLEXMB04.amd.com; pr=C", "From": "Andrew Boyer <andrew.boyer@amd.com>", "To": "<dev@dpdk.org>", "CC": "Andrew Boyer <andrew.boyer@amd.com>", "Subject": "[PATCH v2 16/36] net/ionic: free all buffers during Rx queue stop", "Date": "Tue, 18 Oct 2022 12:41:11 -0700", "Message-ID": "<20221018194131.23006-17-andrew.boyer@amd.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20221011005032.47584-1-andrew.boyer@amd.com>", "References": "<20221011005032.47584-1-andrew.boyer@amd.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.180.168.240]", "X-ClientProxiedBy": "SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com\n (10.181.40.145)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT034:EE_|SA3PR12MB7950:EE_", "X-MS-Office365-Filtering-Correlation-Id": "af8154d1-0f5f-4457-0d75-08dab1415003", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n jeZ9bjNud8kcZhpYzaQbaFzE93MvK1OaV/NaCVI/wM0sNlLymjvdQEuge0pxTicK2CprDBt3n/Drl9tNh0aX8AIN2PxBCGZUgd28N3Un9CP2W8QoO05e7q5ngVJzR1+XiFe8KZZQc4bFLnFjylTl1NkwEQ2RSEKSiIGf2pBOyI6YDKRuNBOJvfcxVRK5yuKqBk2N16O2Gz1/i92ijtfHagTX8WXRMlZAgW5mgtqd+MuCFMov4hAvYNUS3O4VeAvqssjHeTwTFAT0LmyiOjppWbawlFuMZRb8unaKToRECrfxNZoZsAmsVimrNzi/j79MNxr+7BWZKu3JvmB46cF3fnzfAoHLywCJbjl1xQ3WGHWtPgriAtU7r3PHH18gjIEU4Qva88QC6UerYnXrjsO0FybksdYoXc+F3c/DsbZZdEL4E6eTAX/vYfGDoiOp+BSydpLW+CsJitrWHsUGRAjeHPy5NyMzCzWoIvXIXigND5QoeNzrgjn/1v9/8k6LxCYFBf39HSrvymIgnsqJfw2/5Dizn2CX7OcykMk7Q/bZBD5Co1bkuLvhWycG4xdwDQHCubgtuM39+C4j2VDsb8COxOKcGp5vSfkWUaqU0F9olAjsTnYZoxKfVV+fZm0rkJrM6dV+rWWLPnfa1nY45HhylIj2lxlFAeWWdos5Ct7N38GMcGfihix6N25PVW7thVo2viz3qwdZI61YZgqgGQO9yZknmKEe3YPygAStqlyQmFetNzT8eiQWQMEAJVlWEz/wEE7U92iK9jWlwuF1Ky06vLTD08u2Ug377Wnd0sz5zfBJ0ImX4xDOK2y/+EqxBO9d", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230022)(4636009)(136003)(376002)(396003)(39860400002)(346002)(451199015)(46966006)(40470700004)(36840700001)(186003)(426003)(47076005)(336012)(36860700001)(16526019)(1076003)(2906002)(82310400005)(5660300002)(316002)(6916009)(2616005)(86362001)(82740400003)(41300700001)(26005)(6666004)(8676002)(70206006)(70586007)(30864003)(83380400001)(40480700001)(81166007)(4326008)(356005)(8936002)(40460700003)(44832011)(478600001)(36756003)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Oct 2022 19:45:29.8933 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n af8154d1-0f5f-4457-0d75-08dab1415003", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT034.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA3PR12MB7950", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Free all of the mbufs in the receive queue when the queue is\nstopped. This will allow them to be resized when the MTU is\nchanged.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\n---\n drivers/net/ionic/ionic_dev.c | 16 +++++\n drivers/net/ionic/ionic_dev.h | 2 +\n drivers/net/ionic/ionic_lif.c | 32 ++++-----\n drivers/net/ionic/ionic_lif.h | 4 --\n drivers/net/ionic/ionic_rxtx.c | 116 +++++++++++++++------------------\n 5 files changed, 81 insertions(+), 89 deletions(-)", "diff": "diff --git a/drivers/net/ionic/ionic_dev.c b/drivers/net/ionic/ionic_dev.c\nindex 1082a007d3..70c14882ed 100644\n--- a/drivers/net/ionic/ionic_dev.c\n+++ b/drivers/net/ionic/ionic_dev.c\n@@ -317,6 +317,15 @@ ionic_cq_init(struct ionic_cq *cq, uint16_t num_descs)\n \treturn 0;\n }\n \n+void\n+ionic_cq_reset(struct ionic_cq *cq)\n+{\n+\tcq->tail_idx = 0;\n+\tcq->done_color = 1;\n+\n+\tmemset(cq->base, 0, sizeof(struct ionic_nop_comp) * cq->num_descs);\n+}\n+\n void\n ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa)\n {\n@@ -379,3 +388,10 @@ ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa)\n \tq->sg_base = base;\n \tq->sg_base_pa = base_pa;\n }\n+\n+void\n+ionic_q_reset(struct ionic_queue *q)\n+{\n+\tq->head_idx = 0;\n+\tq->tail_idx = 0;\n+}\ndiff --git a/drivers/net/ionic/ionic_dev.h b/drivers/net/ionic/ionic_dev.h\nindex 6dab7e5bbd..b77de30de1 100644\n--- a/drivers/net/ionic/ionic_dev.h\n+++ b/drivers/net/ionic/ionic_dev.h\n@@ -225,6 +225,7 @@ struct ionic_doorbell __iomem *ionic_db_map(struct ionic_lif *lif,\n \tstruct ionic_queue *q);\n \n int ionic_cq_init(struct ionic_cq *cq, uint16_t num_descs);\n+void ionic_cq_reset(struct ionic_cq *cq);\n void ionic_cq_map(struct ionic_cq *cq, void *base, rte_iova_t base_pa);\n typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, uint16_t cq_desc_index,\n \t\tvoid *cb_arg);\n@@ -232,6 +233,7 @@ uint32_t ionic_cq_service(struct ionic_cq *cq, uint32_t work_to_do,\n \tionic_cq_cb cb, void *cb_arg);\n \n int ionic_q_init(struct ionic_queue *q, uint32_t index, uint16_t num_descs);\n+void ionic_q_reset(struct ionic_queue *q);\n void ionic_q_map(struct ionic_queue *q, void *base, rte_iova_t base_pa);\n void ionic_q_sg_map(struct ionic_queue *q, void *base, rte_iova_t base_pa);\n \ndiff --git a/drivers/net/ionic/ionic_lif.c b/drivers/net/ionic/ionic_lif.c\nindex ccd7ea68bb..e7cb9e2ea3 100644\n--- a/drivers/net/ionic/ionic_lif.c\n+++ b/drivers/net/ionic/ionic_lif.c\n@@ -30,25 +30,7 @@ static const uint8_t ionic_qtype_vers[IONIC_QTYPE_MAX] = {\n static int ionic_lif_addr_add(struct ionic_lif *lif, const uint8_t *addr);\n static int ionic_lif_addr_del(struct ionic_lif *lif, const uint8_t *addr);\n \n-int\n-ionic_qcq_enable(struct ionic_qcq *qcq)\n-{\n-\tstruct ionic_queue *q = &qcq->q;\n-\tstruct ionic_lif *lif = qcq->lif;\n-\tstruct ionic_admin_ctx ctx = {\n-\t\t.pending_work = true,\n-\t\t.cmd.q_control = {\n-\t\t\t.opcode = IONIC_CMD_Q_CONTROL,\n-\t\t\t.type = q->type,\n-\t\t\t.index = rte_cpu_to_le_32(q->index),\n-\t\t\t.oper = IONIC_Q_ENABLE,\n-\t\t},\n-\t};\n-\n-\treturn ionic_adminq_post_wait(lif, &ctx);\n-}\n-\n-int\n+static int\n ionic_qcq_disable(struct ionic_qcq *qcq)\n {\n \tstruct ionic_queue *q = &qcq->q;\n@@ -133,7 +115,6 @@ ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats\n \tfor (i = 0; i < lif->nrxqcqs; i++) {\n \t\tstruct ionic_rx_stats *rx_stats = &lif->rxqcqs[i]->stats;\n \t\tstats->ierrors +=\n-\t\t\trx_stats->no_cb_arg +\n \t\t\trx_stats->bad_cq_status +\n \t\t\trx_stats->no_room +\n \t\t\trx_stats->bad_len;\n@@ -154,7 +135,6 @@ ionic_lif_get_abs_stats(const struct ionic_lif *lif, struct rte_eth_stats *stats\n \t\tstats->q_ipackets[i] = rx_stats->packets;\n \t\tstats->q_ibytes[i] = rx_stats->bytes;\n \t\tstats->q_errors[i] =\n-\t\t\trx_stats->no_cb_arg +\n \t\t\trx_stats->bad_cq_status +\n \t\t\trx_stats->no_room +\n \t\t\trx_stats->bad_len;\n@@ -1146,12 +1126,16 @@ ionic_lif_rss_teardown(struct ionic_lif *lif)\n void\n ionic_lif_txq_deinit(struct ionic_tx_qcq *txq)\n {\n+\tionic_qcq_disable(&txq->qcq);\n+\n \ttxq->flags &= ~IONIC_QCQ_F_INITED;\n }\n \n void\n ionic_lif_rxq_deinit(struct ionic_rx_qcq *rxq)\n {\n+\tionic_qcq_disable(&rxq->qcq);\n+\n \trxq->flags &= ~IONIC_QCQ_F_INITED;\n }\n \n@@ -1488,6 +1472,9 @@ ionic_lif_txq_init(struct ionic_tx_qcq *txq)\n \t\tctx.cmd.q_init.ring_size);\n \tIONIC_PRINT(DEBUG, \"txq_init.ver %u\", ctx.cmd.q_init.ver);\n \n+\tionic_q_reset(q);\n+\tionic_cq_reset(cq);\n+\n \terr = ionic_adminq_post_wait(lif, &ctx);\n \tif (err)\n \t\treturn err;\n@@ -1536,6 +1523,9 @@ ionic_lif_rxq_init(struct ionic_rx_qcq *rxq)\n \t\tctx.cmd.q_init.ring_size);\n \tIONIC_PRINT(DEBUG, \"rxq_init.ver %u\", ctx.cmd.q_init.ver);\n \n+\tionic_q_reset(q);\n+\tionic_cq_reset(cq);\n+\n \terr = ionic_adminq_post_wait(lif, &ctx);\n \tif (err)\n \t\treturn err;\ndiff --git a/drivers/net/ionic/ionic_lif.h b/drivers/net/ionic/ionic_lif.h\nindex c87f981803..a8f7458327 100644\n--- a/drivers/net/ionic/ionic_lif.h\n+++ b/drivers/net/ionic/ionic_lif.h\n@@ -39,7 +39,6 @@ struct ionic_tx_stats {\n struct ionic_rx_stats {\n \tuint64_t packets;\n \tuint64_t bytes;\n-\tuint64_t no_cb_arg;\n \tuint64_t bad_cq_status;\n \tuint64_t no_room;\n \tuint64_t bad_len;\n@@ -207,9 +206,6 @@ int ionic_tx_qcq_alloc(struct ionic_lif *lif, uint32_t socket_id,\n \tstruct ionic_tx_qcq **qcq_out);\n void ionic_qcq_free(struct ionic_qcq *qcq);\n \n-int ionic_qcq_enable(struct ionic_qcq *qcq);\n-int ionic_qcq_disable(struct ionic_qcq *qcq);\n-\n int ionic_lif_rxq_init(struct ionic_rx_qcq *rxq);\n void ionic_lif_rxq_deinit(struct ionic_rx_qcq *rxq);\n \ndiff --git a/drivers/net/ionic/ionic_rxtx.c b/drivers/net/ionic/ionic_rxtx.c\nindex c90d3d62f3..b2c3639e51 100644\n--- a/drivers/net/ionic/ionic_rxtx.c\n+++ b/drivers/net/ionic/ionic_rxtx.c\n@@ -47,6 +47,34 @@\n #include \"ionic_lif.h\"\n #include \"ionic_rxtx.h\"\n \n+static void\n+ionic_empty_array(void **array, uint32_t cnt, uint16_t idx)\n+{\n+\tuint32_t i;\n+\n+\tfor (i = idx; i < cnt; i++)\n+\t\tif (array[i])\n+\t\t\trte_pktmbuf_free_seg(array[i]);\n+\n+\tmemset(array, 0, sizeof(void *) * cnt);\n+}\n+\n+static void __rte_cold\n+ionic_tx_empty(struct ionic_tx_qcq *txq)\n+{\n+\tstruct ionic_queue *q = &txq->qcq.q;\n+\n+\tionic_empty_array(q->info, q->num_descs, 0);\n+}\n+\n+static void __rte_cold\n+ionic_rx_empty(struct ionic_rx_qcq *rxq)\n+{\n+\tstruct ionic_queue *q = &rxq->qcq.q;\n+\n+\tionic_empty_array(q->info, q->num_descs, 0);\n+}\n+\n /*********************************************************************\n *\n * TX functions\n@@ -121,21 +149,16 @@ void __rte_cold\n ionic_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)\n {\n \tstruct ionic_tx_qcq *txq = dev->data->tx_queues[qid];\n-\tstruct ionic_tx_stats *stats = &txq->stats;\n \n \tIONIC_PRINT_CALL();\n \n-\tIONIC_PRINT(DEBUG, \"TX queue %u pkts %ju tso %ju\",\n-\t\ttxq->qcq.q.index, stats->packets, stats->tso);\n-\n-\tionic_lif_txq_deinit(txq);\n-\n \tionic_qcq_free(&txq->qcq);\n }\n \n int __rte_cold\n ionic_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)\n {\n+\tstruct ionic_tx_stats *stats;\n \tstruct ionic_tx_qcq *txq;\n \n \tIONIC_PRINT(DEBUG, \"Stopping TX queue %u\", tx_queue_id);\n@@ -150,9 +173,14 @@ ionic_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)\n \t * before disabling Tx queue\n \t */\n \n-\tionic_qcq_disable(&txq->qcq);\n+\tionic_lif_txq_deinit(txq);\n \n-\tionic_tx_flush(txq);\n+\t/* Free all buffers from descriptor ring */\n+\tionic_tx_empty(txq);\n+\n+\tstats = &txq->stats;\n+\tIONIC_PRINT(DEBUG, \"TX queue %u pkts %ju tso %ju\",\n+\t\ttxq->qcq.q.index, stats->packets, stats->tso);\n \n \treturn 0;\n }\n@@ -236,13 +264,9 @@ ionic_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)\n \tIONIC_PRINT(DEBUG, \"Starting TX queue %u, %u descs\",\n \t\ttx_queue_id, txq->qcq.q.num_descs);\n \n-\tif (!(txq->flags & IONIC_QCQ_F_INITED)) {\n-\t\terr = ionic_lif_txq_init(txq);\n-\t\tif (err)\n-\t\t\treturn err;\n-\t} else {\n-\t\tionic_qcq_enable(&txq->qcq);\n-\t}\n+\terr = ionic_lif_txq_init(txq);\n+\tif (err)\n+\t\treturn err;\n \n \ttx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n \n@@ -648,42 +672,16 @@ ionic_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,\n \tqinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;\n }\n \n-static void __rte_cold\n-ionic_rx_empty(struct ionic_rx_qcq *rxq)\n-{\n-\tstruct ionic_queue *q = &rxq->qcq.q;\n-\tstruct rte_mbuf *mbuf;\n-\tvoid **info;\n-\n-\twhile (q->tail_idx != q->head_idx) {\n-\t\tinfo = IONIC_INFO_PTR(q, q->tail_idx);\n-\t\tmbuf = info[0];\n-\t\trte_mempool_put(rxq->mb_pool, mbuf);\n-\n-\t\tq->tail_idx = Q_NEXT_TO_SRVC(q, 1);\n-\t}\n-}\n-\n void __rte_cold\n ionic_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)\n {\n \tstruct ionic_rx_qcq *rxq = dev->data->rx_queues[qid];\n-\tstruct ionic_rx_stats *stats;\n \n \tif (!rxq)\n \t\treturn;\n \n \tIONIC_PRINT_CALL();\n \n-\tstats = &rxq->stats;\n-\n-\tIONIC_PRINT(DEBUG, \"RX queue %u pkts %ju mtod %ju\",\n-\t\trxq->qcq.q.index, stats->packets, stats->mtods);\n-\n-\tionic_rx_empty(rxq);\n-\n-\tionic_lif_rxq_deinit(rxq);\n-\n \tionic_qcq_free(&rxq->qcq);\n }\n \n@@ -787,17 +785,6 @@ ionic_rx_clean(struct ionic_rx_qcq *rxq,\n \n \trxm = info[0];\n \n-\tif (!rx_svc) {\n-\t\tstats->no_cb_arg++;\n-\t\t/* Flush */\n-\t\trte_pktmbuf_free(rxm);\n-\t\t/*\n-\t\t * Note: rte_mempool_put is faster with no segs\n-\t\t * rte_mempool_put(rxq->mb_pool, rxm);\n-\t\t */\n-\t\treturn;\n-\t}\n-\n \tif (cq_desc->status) {\n \t\tstats->bad_cq_status++;\n \t\tionic_rx_recycle(q, q_desc_index, rxm);\n@@ -1028,13 +1015,9 @@ ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)\n \tIONIC_PRINT(DEBUG, \"Starting RX queue %u, %u descs, size %u\",\n \t\trx_queue_id, rxq->qcq.q.num_descs, rxq->frame_size);\n \n-\tif (!(rxq->flags & IONIC_QCQ_F_INITED)) {\n-\t\terr = ionic_lif_rxq_init(rxq);\n-\t\tif (err)\n-\t\t\treturn err;\n-\t} else {\n-\t\tionic_qcq_enable(&rxq->qcq);\n-\t}\n+\terr = ionic_lif_rxq_init(rxq);\n+\tif (err)\n+\t\treturn err;\n \n \t/* Allocate buffers for descriptor rings */\n \tif (ionic_rx_fill(rxq) != 0) {\n@@ -1103,19 +1086,24 @@ ionic_rxq_service(struct ionic_rx_qcq *rxq, uint32_t work_to_do,\n int __rte_cold\n ionic_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)\n {\n+\tuint8_t *rx_queue_state = eth_dev->data->rx_queue_state;\n+\tstruct ionic_rx_stats *stats;\n \tstruct ionic_rx_qcq *rxq;\n \n \tIONIC_PRINT(DEBUG, \"Stopping RX queue %u\", rx_queue_id);\n \n \trxq = eth_dev->data->rx_queues[rx_queue_id];\n \n-\teth_dev->data->rx_queue_state[rx_queue_id] =\n-\t\tRTE_ETH_QUEUE_STATE_STOPPED;\n+\trx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n+\tionic_lif_rxq_deinit(rxq);\n \n-\tionic_qcq_disable(&rxq->qcq);\n+\t/* Free all buffers from descriptor ring */\n+\tionic_rx_empty(rxq);\n \n-\t/* Flush */\n-\tionic_rxq_service(rxq, -1, NULL);\n+\tstats = &rxq->stats;\n+\tIONIC_PRINT(DEBUG, \"RX queue %u pkts %ju mtod %ju\",\n+\t\trxq->qcq.q.index, stats->packets, stats->mtods);\n \n \treturn 0;\n }\n", "prefixes": [ "v2", "16/36" ] }