Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/118220/?format=api
{ "id": 118220, "url": "http://patches.dpdk.org/api/patches/118220/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221014114833.13389-19-valex@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221014114833.13389-19-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221014114833.13389-19-valex@nvidia.com", "date": "2022-10-14T11:48:33", "name": "[v3,18/18] net/mlx5/hws: Enable HWS", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "cb0f3d87abdaa91df7923f2b7ccb4847fa17a96d", "submitter": { "id": 2858, "url": "http://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221014114833.13389-19-valex@nvidia.com/mbox/", "series": [ { "id": 25236, "url": "http://patches.dpdk.org/api/series/25236/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25236", "date": "2022-10-14T11:48:15", "name": "net/mlx5: Add HW steering low level support", "version": 3, "mbox": "http://patches.dpdk.org/series/25236/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/118220/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/118220/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3977EA00C2;\n\tFri, 14 Oct 2022 13:51:47 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B88F442DE1;\n\tFri, 14 Oct 2022 13:50:08 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2069.outbound.protection.outlook.com [40.107.244.69])\n by mails.dpdk.org (Postfix) with ESMTP id 0B6CB42DE1\n for <dev@dpdk.org>; Fri, 14 Oct 2022 13:50:07 +0200 (CEST)", "from BN9PR03CA0697.namprd03.prod.outlook.com (2603:10b6:408:ef::12)\n by CY8PR12MB7561.namprd12.prod.outlook.com (2603:10b6:930:94::22)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.26; Fri, 14 Oct\n 2022 11:50:03 +0000", "from BN8NAM11FT019.eop-nam11.prod.protection.outlook.com\n (2603:10b6:408:ef:cafe::f2) by BN9PR03CA0697.outlook.office365.com\n (2603:10b6:408:ef::12) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.30 via Frontend\n Transport; Fri, 14 Oct 2022 11:50:02 +0000", "from mail.nvidia.com (216.228.117.160) by\n BN8NAM11FT019.mail.protection.outlook.com (10.13.176.158) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.5723.20 via Frontend Transport; Fri, 14 Oct 2022 11:50:02 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 14 Oct\n 2022 04:49:48 -0700", "from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 14 Oct\n 2022 04:49:46 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=e6V6/JXD5vvhqvlGjHLLvjY/2EZlJNXNgL43OKX65NEmp5uLC/P4pGOsGeb4qfoAa8GxHk7TPcyruGmATt6tCrR1ZGLcEno51sKvwQexILjrp8vwAWDLRX+NmYWV35FpyrE/LFYxQJNZDeRXza3PFyJvYJsSUNEY4J6E6o2ArPGJg82/D5J4ZUvnUrfezokIDBFn99b/N7/IYU/ebkSh4k9Zfa7geYgQi8JJ6Xi6UyOwaSE9SJS66ngCjSanQO/lT3cjifbqMcK3V/6MWptM+x0TQ/2ZM84ujhhigXddSgPKWHd/HylS8eqh330LlV2FOogPEdTUgQSABHROGbiEiw==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=Zlea//h5/m1YRuV0nR9Z48Ptk4aZskUCzDovSAM+yeQ=;\n b=CNvrPrGLhzCFghoHExtvtAncaRtvEITWjzCVwGMt2R6tRxDdUISQUPalx4S0JvlBsUs3xeqezpViYZo0q37EsAb8BLmNdjCLQtF8aVIAi6GVRgfa3n9ww4L6qJdIZErR+j1/Gd5wwUoYD/dMQAybI8uTRgPqy4GffTRXttxGcBOkKy8GzA9K82KvZButuAjkn/YD8WIV28fsWTtqbVRQDDQ5VAaYwzzd5DZ1WWxl7HijmfbLwy152LmkWc/uoX0CAM9SmXLviwi4jMjYikvciGfvotWjUTGkDY2aSbGppSrZLAu9jpTpvRaEBCUdDI2c/uhMinKJTCEZgigUKZwrdQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=Zlea//h5/m1YRuV0nR9Z48Ptk4aZskUCzDovSAM+yeQ=;\n b=gd+nnOJ3Za1MMY56fkDqw3iO5Lq1+sU12VRQ4x/8Bs8lC3euHDym6o72goqH6aLORfsY5Rdy8GGWtfnVY0np5UEBnHNNL2KnWBa5qjam/px1L0eBIWg+s+EhRGxEZharbjdjQL+HhVSThqeX1ux7TG05xghYCJUhaSnPHweGZ5UqMOtqvrAN2EsAYNv6Cq95XqJr9Iy065b2C+dMKNxO/1cPGShJgI6LmM5nNb9jdOjEmwg3cRXsErNNCzP0Ah7PmktHk64Tk4ScFs8S0XeS23S0/zU6sVFohIHY8jT8En9etJC4gLjzDbjSHvFA3uNO6RgBAMXnTiL+mCiql/SFjg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v3 18/18] net/mlx5/hws: Enable HWS", "Date": "Fri, 14 Oct 2022 14:48:33 +0300", "Message-ID": "<20221014114833.13389-19-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221014114833.13389-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221014114833.13389-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT019:EE_|CY8PR12MB7561:EE_", "X-MS-Office365-Filtering-Correlation-Id": "4f25a9c6-18b0-4dd2-dd0f-08daadda3acc", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n bILplQ27Xl+YXg8KkKNBUJ372BTRafGV13+4++Xc8u7ZKr/1YZ4xquS1pcHA+xA4v+rBVRw18az6XbkcrZUootXIyYyNvc2VHULtgp1C6rB3kxEnHDXt7rkRDh4PLwo3gZR1Q7C6Tfn7MFQtuwAy2ckiwck0AjWnV3b9uV90P9bexPuyfOm15mzsr6Thn0BVjozfCPYhLU12Dm8CVvtDLnPhqClRrP9OXaGJh0o7DD/IONkIUbyM4hptdPlTN4bUHLR5JOff2g1MOAuetAbYuPJGfE82FhY0Z8uewKKjkS/UrBbCqjvC3J27E9EKD+lk1sbDUN8dlXSdW+FCOGjkwJGvY++pFwkqNc0ueJber05V+yDVCt1i/GdCmLCyxAhsJMGlqbuu37geZxPtKeUrO2xRx6I/UHZScQ8gDr8Neu2owNk4uhwRDHS0o9zJ6vioN9iyaaDdu1/aKKwDRRQjCiDiKs57fO67aob8NyzdxzvGfLaGr5+P4Odom1PvTM/DWN67pz3FYGhNwc0pl4aw/i311ROcdoEzIUR7PseKrL9MuHt6pghV+h8XHk2Tv47FgYL4zH0HjHt4ETP30EWi9ww2KCQYpbySWj4ekHp4IIYMwqJxFDc5+CJNKTwOixWWix7SHBoetXf5R1pkZccfEy9bxDafP2w1lp/YXLDj/x6NmNwnSvrWF6dK63MRwFLZhWcZKf/glQ7GsALWCSRdy0hsYuzaaSaE4PDfaKyDsEvrWRNV8gw0pprhPPEAysodvl06qxUiMQxAdeo1zr3qLA==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(136003)(39860400002)(376002)(396003)(346002)(451199015)(36840700001)(46966006)(40470700004)(40460700003)(8936002)(26005)(336012)(36860700001)(47076005)(110136005)(426003)(2616005)(86362001)(356005)(4326008)(2906002)(70586007)(30864003)(83380400001)(316002)(1076003)(8676002)(82740400003)(70206006)(16526019)(6286002)(6666004)(186003)(6636002)(7636003)(54906003)(55016003)(5660300002)(40480700001)(41300700001)(7696005)(36756003)(478600001)(82310400005)(107886003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "14 Oct 2022 11:50:02.5139 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4f25a9c6-18b0-4dd2-dd0f-08daadda3acc", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT019.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY8PR12MB7561", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Replace stub implenation of HWS with mlx5dr code.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/common/mlx5/linux/meson.build | 2 +\n drivers/net/mlx5/hws/meson.build | 18 +\n drivers/net/mlx5/{mlx5_dr.h => hws/mlx5dr.h} | 210 ++++++++--\n drivers/net/mlx5/hws/mlx5dr_internal.h | 93 +++++\n drivers/net/mlx5/meson.build | 5 +-\n drivers/net/mlx5/mlx5.h | 2 +-\n drivers/net/mlx5/mlx5_dr.c | 383 -------------------\n drivers/net/mlx5/mlx5_flow.h | 11 +-\n drivers/net/mlx5/mlx5_flow_hw.c | 10 +-\n 9 files changed, 307 insertions(+), 427 deletions(-)\n create mode 100644 drivers/net/mlx5/hws/meson.build\n rename drivers/net/mlx5/{mlx5_dr.h => hws/mlx5dr.h} (66%)\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_internal.h\n delete mode 100644 drivers/net/mlx5/mlx5_dr.c", "diff": "diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build\nindex f9d1937571..8c95e7ab56 100644\n--- a/drivers/common/mlx5/linux/meson.build\n+++ b/drivers/common/mlx5/linux/meson.build\n@@ -229,6 +229,8 @@ foreach arg:has_member_args\n endforeach\n configure_file(output : 'mlx5_autoconf.h', configuration : config)\n \n+MLX5_HAVE_IBV_FLOW_DV_SUPPORT=config.get('HAVE_IBV_FLOW_DV_SUPPORT')\n+\n # Build Glue Library\n if dlopen_ibverbs\n dlopen_name = 'mlx5_glue'\ndiff --git a/drivers/net/mlx5/hws/meson.build b/drivers/net/mlx5/hws/meson.build\nnew file mode 100644\nindex 0000000000..f94798dd2d\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/meson.build\n@@ -0,0 +1,18 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+\n+includes += include_directories('.')\n+sources += files(\n+\t'mlx5dr_context.c',\n+\t'mlx5dr_table.c',\n+\t'mlx5dr_matcher.c',\n+\t'mlx5dr_rule.c',\n+\t'mlx5dr_action.c',\n+\t'mlx5dr_buddy.c',\n+\t'mlx5dr_pool.c',\n+\t'mlx5dr_cmd.c',\n+\t'mlx5dr_send.c',\n+\t'mlx5dr_definer.c',\n+\t'mlx5dr_debug.c',\n+\t'mlx5dr_pat_arg.c',\n+)\ndiff --git a/drivers/net/mlx5/mlx5_dr.h b/drivers/net/mlx5/hws/mlx5dr.h\nsimilarity index 66%\nrename from drivers/net/mlx5/mlx5_dr.h\nrename to drivers/net/mlx5/hws/mlx5dr.h\nindex d0b2c15652..980bda0d63 100644\n--- a/drivers/net/mlx5/mlx5_dr.h\n+++ b/drivers/net/mlx5/hws/mlx5dr.h\n@@ -1,9 +1,9 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n */\n \n-#ifndef MLX5_DR_H_\n-#define MLX5_DR_H_\n+#ifndef MLX5DR_H_\n+#define MLX5DR_H_\n \n #include <rte_flow.h>\n \n@@ -26,6 +26,27 @@ enum mlx5dr_matcher_resource_mode {\n \tMLX5DR_MATCHER_RESOURCE_MODE_HTABLE,\n };\n \n+enum mlx5dr_action_type {\n+\tMLX5DR_ACTION_TYP_LAST,\n+\tMLX5DR_ACTION_TYP_TNL_L2_TO_L2,\n+\tMLX5DR_ACTION_TYP_L2_TO_TNL_L2,\n+\tMLX5DR_ACTION_TYP_TNL_L3_TO_L2,\n+\tMLX5DR_ACTION_TYP_L2_TO_TNL_L3,\n+\tMLX5DR_ACTION_TYP_DROP,\n+\tMLX5DR_ACTION_TYP_TIR,\n+\tMLX5DR_ACTION_TYP_FT,\n+\tMLX5DR_ACTION_TYP_CTR,\n+\tMLX5DR_ACTION_TYP_TAG,\n+\tMLX5DR_ACTION_TYP_MODIFY_HDR,\n+\tMLX5DR_ACTION_TYP_VPORT,\n+\tMLX5DR_ACTION_TYP_MISS,\n+\tMLX5DR_ACTION_TYP_POP_VLAN,\n+\tMLX5DR_ACTION_TYP_PUSH_VLAN,\n+\tMLX5DR_ACTION_TYP_ASO_METER,\n+\tMLX5DR_ACTION_TYP_ASO_CT,\n+\tMLX5DR_ACTION_TYP_MAX,\n+};\n+\n enum mlx5dr_action_flags {\n \tMLX5DR_ACTION_FLAG_ROOT_RX = 1 << 0,\n \tMLX5DR_ACTION_FLAG_ROOT_TX = 1 << 1,\n@@ -33,7 +54,10 @@ enum mlx5dr_action_flags {\n \tMLX5DR_ACTION_FLAG_HWS_RX = 1 << 3,\n \tMLX5DR_ACTION_FLAG_HWS_TX = 1 << 4,\n \tMLX5DR_ACTION_FLAG_HWS_FDB = 1 << 5,\n-\tMLX5DR_ACTION_FLAG_INLINE = 1 << 6,\n+\t/* Shared action can be used over a few threads, since data is written\n+\t * only once at the creation of the action.\n+\t */\n+\tMLX5DR_ACTION_FLAG_SHARED = 1 << 6,\n };\n \n enum mlx5dr_action_reformat_type {\n@@ -43,6 +67,18 @@ enum mlx5dr_action_reformat_type {\n \tMLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L3,\n };\n \n+enum mlx5dr_action_aso_meter_color {\n+\tMLX5DR_ACTION_ASO_METER_COLOR_RED = 0x0,\n+\tMLX5DR_ACTION_ASO_METER_COLOR_YELLOW = 0x1,\n+\tMLX5DR_ACTION_ASO_METER_COLOR_GREEN = 0x2,\n+\tMLX5DR_ACTION_ASO_METER_COLOR_UNDEFINED = 0x3,\n+};\n+\n+enum mlx5dr_action_aso_ct_flags {\n+\tMLX5DR_ACTION_ASO_CT_DIRECTION_INITIATOR = 0 << 0,\n+\tMLX5DR_ACTION_ASO_CT_DIRECTION_RESPONDER = 1 << 0,\n+};\n+\n enum mlx5dr_match_template_flags {\n \t/* Allow relaxed matching by skipping derived dependent match fields. */\n \tMLX5DR_MATCH_TEMPLATE_FLAG_RELAXED_MATCH = 1,\n@@ -56,7 +92,7 @@ enum mlx5dr_send_queue_actions {\n struct mlx5dr_context_attr {\n \tuint16_t queues;\n \tuint16_t queue_size;\n-\tsize_t initial_log_ste_memory;\n+\tsize_t initial_log_ste_memory; /* Currently not in use */\n \t/* Optional PD used for allocating res ources */\n \tstruct ibv_pd *pd;\n };\n@@ -66,9 +102,21 @@ struct mlx5dr_table_attr {\n \tuint32_t level;\n };\n \n+enum mlx5dr_matcher_flow_src {\n+\tMLX5DR_MATCHER_FLOW_SRC_ANY = 0x0,\n+\tMLX5DR_MATCHER_FLOW_SRC_WIRE = 0x1,\n+\tMLX5DR_MATCHER_FLOW_SRC_VPORT = 0x2,\n+};\n+\n struct mlx5dr_matcher_attr {\n+\t/* Processing priority inside table */\n \tuint32_t priority;\n+\t/* Provide all rules with unique rule_idx in num_log range to reduce locking */\n+\tbool optimize_using_rule_idx;\n+\t/* Resource mode and corresponding size */\n \tenum mlx5dr_matcher_resource_mode mode;\n+\t/* Optimize insertion in case packet origin is the same for all rules */\n+\tenum mlx5dr_matcher_flow_src optimize_flow_src;\n \tunion {\n \t\tstruct {\n \t\t\tuint8_t sz_row_log;\n@@ -84,6 +132,8 @@ struct mlx5dr_matcher_attr {\n struct mlx5dr_rule_attr {\n \tuint16_t queue_id;\n \tvoid *user_data;\n+\t/* Valid if matcher optimize_using_rule_idx is set */\n+\tuint32_t rule_idx;\n \tuint32_t burst:1;\n };\n \n@@ -92,6 +142,9 @@ struct mlx5dr_devx_obj {\n \tuint32_t id;\n };\n \n+/* In actions that take offset, the offset is unique, and the user should not\n+ * reuse the same index because data changing is not atomic.\n+ */\n struct mlx5dr_rule_action {\n \tstruct mlx5dr_action *action;\n \tunion {\n@@ -114,33 +167,19 @@ struct mlx5dr_rule_action {\n \t\t} reformat;\n \n \t\tstruct {\n-\t\t\trte_be32_t vlan_hdr;\n+\t\t\t__be32 vlan_hdr;\n \t\t} push_vlan;\n-\t};\n-};\n-\n-enum {\n-\tMLX5DR_MATCH_TAG_SZ = 32,\n-\tMLX5DR_JAMBO_TAG_SZ = 44,\n-};\n \n-enum mlx5dr_rule_status {\n-\tMLX5DR_RULE_STATUS_UNKNOWN,\n-\tMLX5DR_RULE_STATUS_CREATING,\n-\tMLX5DR_RULE_STATUS_CREATED,\n-\tMLX5DR_RULE_STATUS_DELETING,\n-\tMLX5DR_RULE_STATUS_DELETED,\n-\tMLX5DR_RULE_STATUS_FAILED,\n-};\n+\t\tstruct {\n+\t\t\tuint32_t offset;\n+\t\t\tenum mlx5dr_action_aso_meter_color init_color;\n+\t\t} aso_meter;\n \n-struct mlx5dr_rule {\n-\tstruct mlx5dr_matcher *matcher;\n-\tunion {\n-\t\tuint8_t match_tag[MLX5DR_MATCH_TAG_SZ];\n-\t\tstruct ibv_flow *flow;\n+\t\tstruct {\n+\t\t\tuint32_t offset;\n+\t\t\tenum mlx5dr_action_aso_ct_flags direction;\n+\t\t} aso_ct;\n \t};\n-\tenum mlx5dr_rule_status status;\n-\tuint32_t rtc_used; /* The RTC into which the STE was inserted */\n };\n \n /* Open a context used for direct rule insertion using hardware steering.\n@@ -153,7 +192,7 @@ struct mlx5dr_rule {\n * @return pointer to mlx5dr_context on success NULL otherwise.\n */\n struct mlx5dr_context *\n-mlx5dr_context_open(void *ibv_ctx,\n+mlx5dr_context_open(struct ibv_context *ibv_ctx,\n \t\t struct mlx5dr_context_attr *attr);\n \n /* Close a context used for direct hardware steering.\n@@ -205,6 +244,26 @@ mlx5dr_match_template_create(const struct rte_flow_item items[],\n */\n int mlx5dr_match_template_destroy(struct mlx5dr_match_template *mt);\n \n+/* Create new action template based on action_type array, the action template\n+ * will be used for matcher creation.\n+ *\n+ * @param[in] action_type\n+ *\tAn array of actions based on the order of actions which will be provided\n+ *\twith rule_actions to mlx5dr_rule_create. The last action is marked\n+ *\tusing MLX5DR_ACTION_TYP_LAST.\n+ * @return pointer to mlx5dr_action_template on success NULL otherwise\n+ */\n+struct mlx5dr_action_template *\n+mlx5dr_action_template_create(const enum mlx5dr_action_type action_type[]);\n+\n+/* Destroy action template.\n+ *\n+ * @param[in] at\n+ *\tAction template to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_action_template_destroy(struct mlx5dr_action_template *at);\n+\n /* Create a new direct rule matcher. Each matcher can contain multiple rules.\n * Matchers on the table will be processed by priority. Matching fields and\n * mask are described by the match template. In some cases multiple match\n@@ -216,6 +275,10 @@ int mlx5dr_match_template_destroy(struct mlx5dr_match_template *mt);\n *\tArray of match templates to be used on matcher.\n * @param[in] num_of_mt\n *\tNumber of match templates in mt array.\n+ * @param[in] at\n+ *\tArray of action templates to be used on matcher.\n+ * @param[in] num_of_at\n+ *\tNumber of action templates in mt array.\n * @param[in] attr\n *\tAttributes used for matcher creation.\n * @return pointer to mlx5dr_matcher on success NULL otherwise.\n@@ -224,6 +287,8 @@ struct mlx5dr_matcher *\n mlx5dr_matcher_create(struct mlx5dr_table *table,\n \t\t struct mlx5dr_match_template *mt[],\n \t\t uint8_t num_of_mt,\n+\t\t struct mlx5dr_action_template *at[],\n+\t\t uint8_t num_of_at,\n \t\t struct mlx5dr_matcher_attr *attr);\n \n /* Destroy direct rule matcher.\n@@ -245,11 +310,13 @@ size_t mlx5dr_rule_get_handle_size(void);\n * @param[in] matcher\n *\tThe matcher in which the new rule will be created.\n * @param[in] mt_idx\n- *\tMatch template index to create the rule with.\n+ *\tMatch template index to create the match with.\n * @param[in] items\n *\tThe items used for the value matching.\n * @param[in] rule_actions\n *\tRule action to be executed on match.\n+ * @param[in] at_idx\n+ *\tAction template index to apply the actions with.\n * @param[in] num_of_actions\n *\tNumber of rule actions.\n * @param[in] attr\n@@ -261,8 +328,8 @@ size_t mlx5dr_rule_get_handle_size(void);\n int mlx5dr_rule_create(struct mlx5dr_matcher *matcher,\n \t\t uint8_t mt_idx,\n \t\t const struct rte_flow_item items[],\n+\t\t uint8_t at_idx,\n \t\t struct mlx5dr_rule_action rule_actions[],\n-\t\t uint8_t num_of_actions,\n \t\t struct mlx5dr_rule_attr *attr,\n \t\t struct mlx5dr_rule *rule_handle);\n \n@@ -317,6 +384,21 @@ mlx5dr_action_create_dest_table(struct mlx5dr_context *ctx,\n \t\t\t\tstruct mlx5dr_table *tbl,\n \t\t\t\tuint32_t flags);\n \n+/* Create direct rule goto vport action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] ib_port_num\n+ *\tDestination ib_port number.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_dest_vport(struct mlx5dr_context *ctx,\n+\t\t\t\tuint32_t ib_port_num,\n+\t\t\t\tuint32_t flags);\n+\n /* Create direct rule goto TIR action.\n *\n * @param[in] ctx\n@@ -400,10 +482,66 @@ mlx5dr_action_create_reformat(struct mlx5dr_context *ctx,\n struct mlx5dr_action *\n mlx5dr_action_create_modify_header(struct mlx5dr_context *ctx,\n \t\t\t\t size_t pattern_sz,\n-\t\t\t\t rte_be64_t pattern[],\n+\t\t\t\t __be64 pattern[],\n \t\t\t\t uint32_t log_bulk_size,\n \t\t\t\t uint32_t flags);\n \n+/* Create direct rule ASO flow meter action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] devx_obj\n+ *\tThe DEVX ASO object.\n+ * @param[in] return_reg_c\n+ *\tCopy the ASO object value into this reg_c, after a packet hits a rule with this ASO object.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_aso_meter(struct mlx5dr_context *ctx,\n+\t\t\t struct mlx5dr_devx_obj *devx_obj,\n+\t\t\t uint8_t return_reg_c,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule ASO CT action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] devx_obj\n+ *\tThe DEVX ASO object.\n+ * @param[in] return_reg_id\n+ * \tCopy the ASO object value into this reg_id, after a packet hits a rule with this ASO object.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_aso_ct(struct mlx5dr_context *ctx,\n+\t\t\t struct mlx5dr_devx_obj *devx_obj,\n+\t\t\t uint8_t return_reg_id,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule pop vlan action.\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_pop_vlan(struct mlx5dr_context *ctx, uint32_t flags);\n+\n+/* Create direct rule push vlan action.\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_push_vlan(struct mlx5dr_context *ctx, uint32_t flags);\n+\n /* Destroy direct rule action.\n *\n * @param[in] action\n@@ -432,11 +570,11 @@ int mlx5dr_send_queue_poll(struct mlx5dr_context *ctx,\n /* Perform an action on the queue\n *\n * @param[in] ctx\n- *\tThe context to which the queue belong to.\n+ * \tThe context to which the queue belong to.\n * @param[in] queue_id\n- *\tThe id of the queue to perform the action on.\n+ * \tThe id of the queue to perform the action on.\n * @param[in] actions\n- *\tActions to perform on the queue. (enum mlx5dr_send_queue_actions)\n+ * \tActions to perform on the queue. (enum mlx5dr_send_queue_actions)\n * @return zero on success non zero otherwise.\n */\n int mlx5dr_send_queue_action(struct mlx5dr_context *ctx,\n@@ -448,7 +586,7 @@ int mlx5dr_send_queue_action(struct mlx5dr_context *ctx,\n * @param[in] ctx\n *\tThe context which to dump the info from.\n * @param[in] f\n- *\tThe file to write the dump to.\n+ * \tThe file to write the dump to.\n * @return zero on success non zero otherwise.\n */\n int mlx5dr_debug_dump(struct mlx5dr_context *ctx, FILE *f);\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_internal.h b/drivers/net/mlx5/hws/mlx5dr_internal.h\nnew file mode 100644\nindex 0000000000..dbd77b9c66\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_internal.h\n@@ -0,0 +1,93 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#ifndef MLX5DR_INTERNAL_H_\n+#define MLX5DR_INTERNAL_H_\n+\n+#include <stdint.h>\n+#include <sys/queue.h>\n+/* Verbs headers do not support -pedantic. */\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-Wpedantic\"\n+#endif\n+#include <infiniband/verbs.h>\n+#include <infiniband/mlx5dv.h>\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic error \"-Wpedantic\"\n+#endif\n+#include <rte_flow.h>\n+#include <rte_gtp.h>\n+\n+#include \"mlx5_prm.h\"\n+#include \"mlx5_glue.h\"\n+#include \"mlx5_flow.h\"\n+#include \"mlx5_utils.h\"\n+#include \"mlx5_malloc.h\"\n+\n+#include \"mlx5dr.h\"\n+#include \"mlx5dr_pool.h\"\n+#include \"mlx5dr_context.h\"\n+#include \"mlx5dr_table.h\"\n+#include \"mlx5dr_matcher.h\"\n+#include \"mlx5dr_send.h\"\n+#include \"mlx5dr_rule.h\"\n+#include \"mlx5dr_cmd.h\"\n+#include \"mlx5dr_action.h\"\n+#include \"mlx5dr_definer.h\"\n+#include \"mlx5dr_debug.h\"\n+#include \"mlx5dr_pat_arg.h\"\n+\n+#define DW_SIZE\t\t4\n+#define BITS_IN_BYTE\t8\n+#define BITS_IN_DW\t(BITS_IN_BYTE * DW_SIZE)\n+\n+#define BIT(_bit) (1ULL << (_bit))\n+#define IS_BIT_SET(_value, _bit) (_value & (1ULL << (_bit)))\n+\n+#ifndef ARRAY_SIZE\n+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))\n+#endif\n+\n+#ifdef RTE_LIBRTE_MLX5_DEBUG\n+/* Prevent double function name print when debug is set */\n+#define DR_LOG DRV_LOG\n+#else\n+/* Print function name as part of the log */\n+#define DR_LOG(level, ...) \\\n+\tDRV_LOG(level, RTE_FMT(\"[%s]: \" RTE_FMT_HEAD(__VA_ARGS__,), __func__, RTE_FMT_TAIL(__VA_ARGS__,)))\n+#endif\n+\n+static inline void *simple_malloc(size_t size)\n+{\n+\treturn mlx5_malloc(MLX5_MEM_SYS,\n+\t\t\t size,\n+\t\t\t MLX5_MALLOC_ALIGNMENT,\n+\t\t\t SOCKET_ID_ANY);\n+}\n+\n+static inline void *simple_calloc(size_t nmemb, size_t size)\n+{\n+\treturn mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO,\n+\t\t\t nmemb * size,\n+\t\t\t MLX5_MALLOC_ALIGNMENT,\n+\t\t\t SOCKET_ID_ANY);\n+}\n+\n+static inline void simple_free(void *addr)\n+{\n+\tmlx5_free(addr);\n+}\n+\n+static inline bool is_mem_zero(const uint8_t *mem, size_t size)\n+{\n+\tassert(size);\n+\treturn (*mem == 0) && memcmp(mem, mem + 1, size - 1) == 0;\n+}\n+\n+static inline uint64_t roundup_pow_of_two(uint64_t n)\n+{\n+\treturn n == 1 ? 1 : 1ULL << log2above(n);\n+}\n+\n+#endif /* MLX5DR_INTERNAL_H_ */\ndiff --git a/drivers/net/mlx5/meson.build b/drivers/net/mlx5/meson.build\nindex 6a84d96380..7d9e4c5025 100644\n--- a/drivers/net/mlx5/meson.build\n+++ b/drivers/net/mlx5/meson.build\n@@ -14,7 +14,6 @@ sources = files(\n 'mlx5.c',\n 'mlx5_ethdev.c',\n 'mlx5_flow.c',\n- 'mlx5_dr.c',\n 'mlx5_flow_meter.c',\n 'mlx5_flow_dv.c',\n 'mlx5_flow_hw.c',\n@@ -72,3 +71,7 @@ endif\n testpmd_sources += files('mlx5_testpmd.c')\n \n subdir(exec_env)\n+\n+if MLX5_HAVE_IBV_FLOW_DV_SUPPORT\n+\tsubdir('hws')\n+endif\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 741be2df98..05782a8804 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -34,7 +34,7 @@\n #include \"mlx5_os.h\"\n #include \"mlx5_autoconf.h\"\n #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n-#include \"mlx5_dr.h\"\n+#include \"hws/mlx5dr.h\"\n #endif\n \n #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)\ndiff --git a/drivers/net/mlx5/mlx5_dr.c b/drivers/net/mlx5/mlx5_dr.c\ndeleted file mode 100644\nindex 7218708986..0000000000\n--- a/drivers/net/mlx5/mlx5_dr.c\n+++ /dev/null\n@@ -1,383 +0,0 @@\n-/* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.\n- */\n-#include <rte_flow.h>\n-\n-#include \"mlx5_defs.h\"\n-#if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n-#include \"mlx5_dr.h\"\n-\n-/*\n- * The following null stubs are prepared in order not to break the linkage\n- * before the HW steering low-level implementation is added.\n- */\n-\n-/* Open a context used for direct rule insertion using hardware steering.\n- * Each context can contain multiple tables of different types.\n- *\n- * @param[in] ibv_ctx\n- *\tThe ibv context to used for HWS.\n- * @param[in] attr\n- *\tAttributes used for context open.\n- * @return pointer to mlx5dr_context on success NULL otherwise.\n- */\n-__rte_weak struct mlx5dr_context *\n-mlx5dr_context_open(void *ibv_ctx,\n-\t\t struct mlx5dr_context_attr *attr)\n-{\n-\t(void)ibv_ctx;\n-\t(void)attr;\n-\treturn NULL;\n-}\n-\n-/* Close a context used for direct hardware steering.\n- *\n- * @param[in] ctx\n- *\tmlx5dr context to close.\n- * @return zero on success non zero otherwise.\n- */\n-__rte_weak int\n-mlx5dr_context_close(struct mlx5dr_context *ctx)\n-{\n-\t(void)ctx;\n-\treturn 0;\n-}\n-\n-/* Create a new direct rule table. Each table can contain multiple matchers.\n- *\n- * @param[in] ctx\n- *\tThe context in which the new table will be opened.\n- * @param[in] attr\n- *\tAttributes used for table creation.\n- * @return pointer to mlx5dr_table on success NULL otherwise.\n- */\n-__rte_weak struct mlx5dr_table *\n-mlx5dr_table_create(struct mlx5dr_context *ctx,\n-\t\t struct mlx5dr_table_attr *attr)\n-{\n-\t(void)ctx;\n-\t(void)attr;\n-\treturn NULL;\n-}\n-\n-/* Destroy direct rule table.\n- *\n- * @param[in] tbl\n- *\tmlx5dr table to destroy.\n- * @return zero on success non zero otherwise.\n- */\n-__rte_weak int mlx5dr_table_destroy(struct mlx5dr_table *tbl)\n-{\n-\t(void)tbl;\n-\treturn 0;\n-}\n-\n-/* Create new match template based on items mask, the match template\n- * will be used for matcher creation.\n- *\n- * @param[in] items\n- *\tDescribe the mask for template creation\n- * @param[in] flags\n- *\tTemplate creation flags\n- * @return pointer to mlx5dr_match_template on success NULL otherwise\n- */\n-__rte_weak struct mlx5dr_match_template *\n-mlx5dr_match_template_create(const struct rte_flow_item items[],\n-\t\t\t enum mlx5dr_match_template_flags flags)\n-{\n-\t(void)items;\n-\t(void)flags;\n-\treturn NULL;\n-}\n-\n-/* Destroy match template.\n- *\n- * @param[in] mt\n- *\tMatch template to destroy.\n- * @return zero on success non zero otherwise.\n- */\n-__rte_weak int\n-mlx5dr_match_template_destroy(struct mlx5dr_match_template *mt)\n-{\n-\t(void)mt;\n-\treturn 0;\n-}\n-\n-/* Create a new direct rule matcher. Each matcher can contain multiple rules.\n- * Matchers on the table will be processed by priority. Matching fields and\n- * mask are described by the match template. In some cases multiple match\n- * templates can be used on the same matcher.\n- *\n- * @param[in] table\n- *\tThe table in which the new matcher will be opened.\n- * @param[in] mt\n- *\tArray of match templates to be used on matcher.\n- * @param[in] num_of_mt\n- *\tNumber of match templates in mt array.\n- * @param[in] attr\n- *\tAttributes used for matcher creation.\n- * @return pointer to mlx5dr_matcher on success NULL otherwise.\n- */\n-__rte_weak struct mlx5dr_matcher *\n-mlx5dr_matcher_create(struct mlx5dr_table *table __rte_unused,\n-\t\t struct mlx5dr_match_template *mt[] __rte_unused,\n-\t\t uint8_t num_of_mt __rte_unused,\n-\t\t struct mlx5dr_matcher_attr *attr __rte_unused)\n-{\n-\treturn NULL;\n-}\n-\n-/* Destroy direct rule matcher.\n- *\n- * @param[in] matcher\n- *\tMatcher to destroy.\n- * @return zero on success non zero otherwise.\n- */\n-__rte_weak int\n-mlx5dr_matcher_destroy(struct mlx5dr_matcher *matcher __rte_unused)\n-{\n-\treturn 0;\n-}\n-\n-/* Enqueue create rule operation.\n- *\n- * @param[in] matcher\n- *\tThe matcher in which the new rule will be created.\n- * @param[in] mt_idx\n- *\tMatch template index to create the rule with.\n- * @param[in] items\n- *\tThe items used for the value matching.\n- * @param[in] rule_actions\n- *\tRule action to be executed on match.\n- * @param[in] num_of_actions\n- *\tNumber of rule actions.\n- * @param[in] attr\n- *\tRule creation attributes.\n- * @param[in, out] rule_handle\n- *\tA valid rule handle. The handle doesn't require any initialization.\n- * @return zero on successful enqueue non zero otherwise.\n- */\n-__rte_weak int\n-mlx5dr_rule_create(struct mlx5dr_matcher *matcher __rte_unused,\n-\t\t uint8_t mt_idx __rte_unused,\n-\t\t const struct rte_flow_item items[] __rte_unused,\n-\t\t struct mlx5dr_rule_action rule_actions[] __rte_unused,\n-\t\t uint8_t num_of_actions __rte_unused,\n-\t\t struct mlx5dr_rule_attr *attr __rte_unused,\n-\t\t struct mlx5dr_rule *rule_handle __rte_unused)\n-{\n-\treturn 0;\n-}\n-\n-/* Enqueue destroy rule operation.\n- *\n- * @param[in] rule\n- *\tThe rule destruction to enqueue.\n- * @param[in] attr\n- *\tRule destruction attributes.\n- * @return zero on successful enqueue non zero otherwise.\n- */\n-__rte_weak int\n-mlx5dr_rule_destroy(struct mlx5dr_rule *rule __rte_unused,\n-\t\t struct mlx5dr_rule_attr *attr __rte_unused)\n-{\n-\treturn 0;\n-}\n-\n-/* Create direct rule drop action.\n- *\n- * @param[in] ctx\n- *\tThe context in which the new action will be created.\n- * @param[in] flags\n- *\tAction creation flags. (enum mlx5dr_action_flags)\n- * @return pointer to mlx5dr_action on success NULL otherwise.\n- */\n-__rte_weak struct mlx5dr_action *\n-mlx5dr_action_create_dest_drop(struct mlx5dr_context *ctx __rte_unused,\n-\t\t\t uint32_t flags __rte_unused)\n-{\n-\treturn NULL;\n-}\n-\n-/* Create direct rule default miss action.\n- * Defaults are RX: Drop TX: Wire.\n- *\n- * @param[in] ctx\n- *\tThe context in which the new action will be created.\n- * @param[in] flags\n- *\tAction creation flags. (enum mlx5dr_action_flags)\n- * @return pointer to mlx5dr_action on success NULL otherwise.\n- */\n-__rte_weak struct mlx5dr_action *\n-mlx5dr_action_create_default_miss(struct mlx5dr_context *ctx __rte_unused,\n-\t\t\t\t uint32_t flags __rte_unused)\n-{\n-\treturn NULL;\n-}\n-\n-/* Create direct rule goto table action.\n- *\n- * @param[in] ctx\n- *\tThe context in which the new action will be created.\n- * @param[in] tbl\n- *\tDestination table.\n- * @param[in] flags\n- *\tAction creation flags. (enum mlx5dr_action_flags)\n- * @return pointer to mlx5dr_action on success NULL otherwise.\n- */\n-__rte_weak struct mlx5dr_action *\n-mlx5dr_action_create_dest_table(struct mlx5dr_context *ctx __rte_unused,\n-\t\t\t\tstruct mlx5dr_table *tbl __rte_unused,\n-\t\t\t\tuint32_t flags __rte_unused)\n-{\n-\treturn NULL;\n-}\n-\n-/* Create direct rule goto TIR action.\n- *\n- * @param[in] ctx\n- *\tThe context in which the new action will be created.\n- * @param[in] obj\n- *\tDirect rule TIR devx object.\n- * @param[in] flags\n- *\tAction creation flags. (enum mlx5dr_action_flags)\n- * @return pointer to mlx5dr_action on success NULL otherwise.\n- */\n-__rte_weak struct mlx5dr_action *\n-mlx5dr_action_create_dest_tir(struct mlx5dr_context *ctx __rte_unused,\n-\t\t\t struct mlx5dr_devx_obj *obj __rte_unused,\n-\t\t\t uint32_t flags __rte_unused)\n-{\n-\treturn NULL;\n-}\n-\n-/* Create direct rule TAG action.\n- *\n- * @param[in] ctx\n- *\tThe context in which the new action will be created.\n- * @param[in] flags\n- *\tAction creation flags. (enum mlx5dr_action_flags)\n- * @return pointer to mlx5dr_action on success NULL otherwise.\n- */\n-__rte_weak struct mlx5dr_action *\n-mlx5dr_action_create_tag(struct mlx5dr_context *ctx __rte_unused,\n-\t\t\t uint32_t flags __rte_unused)\n-{\n-\treturn NULL;\n-}\n-\n-/* Create direct rule counter action.\n- *\n- * @param[in] ctx\n- *\tThe context in which the new action will be created.\n- * @param[in] obj\n- *\tDirect rule counter devx object.\n- * @param[in] flags\n- *\tAction creation flags. (enum mlx5dr_action_flags)\n- * @return pointer to mlx5dr_action on success NULL otherwise.\n- */\n-__rte_weak struct mlx5dr_action *\n-mlx5dr_action_create_counter(struct mlx5dr_context *ctx,\n-\t\t\t struct mlx5dr_devx_obj *obj,\n-\t\t\t uint32_t flags);\n-\n-/* Create direct rule reformat action.\n- *\n- * @param[in] ctx\n- *\tThe context in which the new action will be created.\n- * @param[in] reformat_type\n- *\tType of reformat.\n- * @param[in] data_sz\n- *\tSize in bytes of data.\n- * @param[in] inline_data\n- *\tHeader data array in case of inline action.\n- * @param[in] log_bulk_size\n- *\tNumber of unique values used with this pattern.\n- * @param[in] flags\n- *\tAction creation flags. (enum mlx5dr_action_flags)\n- * @return pointer to mlx5dr_action on success NULL otherwise.\n- */\n-__rte_weak struct mlx5dr_action *\n-mlx5dr_action_create_reformat(struct mlx5dr_context *ctx __rte_unused,\n-\t enum mlx5dr_action_reformat_type reformat_type __rte_unused,\n-\t\t\t size_t data_sz __rte_unused,\n-\t\t\t void *inline_data __rte_unused,\n-\t\t\t uint32_t log_bulk_size __rte_unused,\n-\t\t\t uint32_t flags __rte_unused)\n-{\n-\treturn NULL;\n-}\n-\n-/* Create direct rule modify header action.\n- *\n- * @param[in] ctx\n- *\tThe context in which the new action will be created.\n- * @param[in] pattern_sz\n- *\tByte size of the pattern array.\n- * @param[in] pattern\n- *\tPRM format modify pattern action array.\n- * @param[in] log_bulk_size\n- *\tNumber of unique values used with this pattern.\n- * @param[in] flags\n- *\tAction creation flags. (enum mlx5dr_action_flags)\n- * @return pointer to mlx5dr_action on success NULL otherwise.\n- */\n-__rte_weak struct mlx5dr_action *\n-mlx5dr_action_create_modify_header(struct mlx5dr_context *ctx,\n-\t\t\t\t size_t pattern_sz,\n-\t\t\t\t rte_be64_t pattern[],\n-\t\t\t\t uint32_t log_bulk_size,\n-\t\t\t\t uint32_t flags);\n-\n-/* Destroy direct rule action.\n- *\n- * @param[in] action\n- *\tThe action to destroy.\n- * @return zero on success non zero otherwise.\n- */\n-__rte_weak int\n-mlx5dr_action_destroy(struct mlx5dr_action *action __rte_unused)\n-{\n-\treturn 0;\n-}\n-\n-/* Poll queue for rule creation and deletions completions.\n- *\n- * @param[in] ctx\n- *\tThe context to which the queue belong to.\n- * @param[in] queue_id\n- *\tThe id of the queue to poll.\n- * @param[in, out] res\n- *\tCompletion array.\n- * @param[in] res_nb\n- *\tMaximum number of results to return.\n- * @return negative number on failure, the number of completions otherwise.\n- */\n-__rte_weak int\n-mlx5dr_send_queue_poll(struct mlx5dr_context *ctx __rte_unused,\n-\t\t uint16_t queue_id __rte_unused,\n-\t\t struct rte_flow_op_result res[] __rte_unused,\n-\t\t uint32_t res_nb __rte_unused)\n-{\n-\treturn 0;\n-}\n-\n-/* Perform an action on the queue\n- *\n- * @param[in] ctx\n- *\tThe context to which the queue belong to.\n- * @param[in] queue_id\n- *\tThe id of the queue to perform the action on.\n- * @param[in] actions\n- *\tActions to perform on the queue. (enum mlx5dr_send_queue_actions)\n- * @return zero on success non zero otherwise.\n- */\n-__rte_weak int\n-mlx5dr_send_queue_action(struct mlx5dr_context *ctx __rte_unused,\n-\t\t\t uint16_t queue_id __rte_unused,\n-\t\t\t uint32_t actions __rte_unused)\n-{\n-\treturn 0;\n-}\n-\n-#endif\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 2002f6ef4b..cde602d3a1 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -17,6 +17,7 @@\n #include <mlx5_prm.h>\n \n #include \"mlx5.h\"\n+#include \"hws/mlx5dr.h\"\n \n /* E-Switch Manager port, used for rte_flow_item_port_id. */\n #define MLX5_PORT_ESW_MGR UINT32_MAX\n@@ -1043,6 +1044,10 @@ struct rte_flow {\n \n #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-Wpedantic\"\n+#endif\n+\n /* HWS flow struct. */\n struct rte_flow_hw {\n \tuint32_t idx; /* Flow index from indexed pool. */\n@@ -1053,9 +1058,13 @@ struct rte_flow_hw {\n \t\tstruct mlx5_hrxq *hrxq; /* TIR action. */\n \t};\n \tstruct rte_flow_template_table *table; /* The table flow allcated from. */\n-\tstruct mlx5dr_rule rule; /* HWS layer data struct. */\n+\tuint8_t rule[0]; /* HWS layer data struct. */\n } __rte_packed;\n \n+#ifdef PEDANTIC\n+#pragma GCC diagnostic error \"-Wpedantic\"\n+#endif\n+\n /* rte flow action translate to DR action struct. */\n struct mlx5_action_construct_data {\n \tLIST_ENTRY(mlx5_action_construct_data) next;\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 78c741bb91..fecf28c1ca 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -1107,8 +1107,8 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev,\n \t\t\t\t actions, rule_acts, &acts_num);\n \tret = mlx5dr_rule_create(table->matcher,\n \t\t\t\t pattern_template_index, items,\n-\t\t\t\t rule_acts, acts_num,\n-\t\t\t\t &rule_attr, &flow->rule);\n+\t\t\t\t action_template_index, rule_acts,\n+\t\t\t\t &rule_attr, (struct mlx5dr_rule *)flow->rule);\n \tif (likely(!ret))\n \t\treturn (struct rte_flow *)flow;\n \t/* Flow created fail, return the descriptor and flow memory. */\n@@ -1171,7 +1171,7 @@ flow_hw_async_flow_destroy(struct rte_eth_dev *dev,\n \tjob->user_data = user_data;\n \tjob->flow = fh;\n \trule_attr.user_data = job;\n-\tret = mlx5dr_rule_destroy(&fh->rule, &rule_attr);\n+\tret = mlx5dr_rule_destroy((struct mlx5dr_rule *)fh->rule, &rule_attr);\n \tif (likely(!ret))\n \t\treturn 0;\n \tpriv->hw_q[queue].job_idx++;\n@@ -1437,7 +1437,7 @@ flow_hw_table_create(struct rte_eth_dev *dev,\n \t\t.data = &flow_attr,\n \t};\n \tstruct mlx5_indexed_pool_config cfg = {\n-\t\t.size = sizeof(struct rte_flow_hw),\n+\t\t.size = sizeof(struct rte_flow_hw) + mlx5dr_rule_get_handle_size(),\n \t\t.trunk_size = 1 << 12,\n \t\t.per_core_cache = 1 << 13,\n \t\t.need_lock = 1,\n@@ -1498,7 +1498,7 @@ flow_hw_table_create(struct rte_eth_dev *dev,\n \t\ttbl->its[i] = item_templates[i];\n \t}\n \ttbl->matcher = mlx5dr_matcher_create\n-\t\t(tbl->grp->tbl, mt, nb_item_templates, &matcher_attr);\n+\t\t(tbl->grp->tbl, mt, nb_item_templates, NULL, 0, &matcher_attr);\n \tif (!tbl->matcher)\n \t\tgoto it_error;\n \ttbl->nb_item_templates = nb_item_templates;\n", "prefixes": [ "v3", "18/18" ] }