Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/118218/?format=api
{ "id": 118218, "url": "http://patches.dpdk.org/api/patches/118218/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221014114833.13389-18-valex@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221014114833.13389-18-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221014114833.13389-18-valex@nvidia.com", "date": "2022-10-14T11:48:32", "name": "[v3,17/18] net/mlx5/hws: Add HWS debug layer", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "80f2a9e9299e861900f7b5cf6656715cf708625a", "submitter": { "id": 2858, "url": "http://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221014114833.13389-18-valex@nvidia.com/mbox/", "series": [ { "id": 25236, "url": "http://patches.dpdk.org/api/series/25236/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25236", "date": "2022-10-14T11:48:15", "name": "net/mlx5: Add HW steering low level support", "version": 3, "mbox": "http://patches.dpdk.org/series/25236/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/118218/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/118218/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8F956A00C2;\n\tFri, 14 Oct 2022 13:51:30 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D224A42E0A;\n\tFri, 14 Oct 2022 13:50:03 +0200 (CEST)", "from NAM02-BN1-obe.outbound.protection.outlook.com\n (mail-bn1nam07on2062.outbound.protection.outlook.com [40.107.212.62])\n by mails.dpdk.org (Postfix) with ESMTP id AF6AF42E3B\n for <dev@dpdk.org>; Fri, 14 Oct 2022 13:50:02 +0200 (CEST)", "from MW4PR03CA0105.namprd03.prod.outlook.com (2603:10b6:303:b7::20)\n by SA1PR12MB6896.namprd12.prod.outlook.com (2603:10b6:806:24f::5)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.26; Fri, 14 Oct\n 2022 11:50:00 +0000", "from CO1NAM11FT048.eop-nam11.prod.protection.outlook.com\n (2603:10b6:303:b7:cafe::df) by MW4PR03CA0105.outlook.office365.com\n (2603:10b6:303:b7::20) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5723.28 via Frontend\n Transport; Fri, 14 Oct 2022 11:49:59 +0000", "from mail.nvidia.com (216.228.117.161) by\n CO1NAM11FT048.mail.protection.outlook.com (10.13.175.148) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.5723.20 via Frontend Transport; Fri, 14 Oct 2022 11:49:59 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 14 Oct\n 2022 04:49:46 -0700", "from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 14 Oct\n 2022 04:49:43 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=azEPLRbEOyJT43iAqY+wVBCMEkWLdKwFwDYqG7xKQTp5MjpD9DHgneXbrtyONKO+5wvoUJO6EZHQZG9aTkoB/k1mUxZs1gYL6jqYixy6QAeItF0kTGJMvGu0qiav+i8GxFUqcRkrCBPjbrX4lxSlYq/TcCgwli/TCNvsUnUhTv81Tnj+uy447C1eRu7vEz0H+Nq0boEBZtdtCs9003SfW+qVS2GjRagLHlejeDA46mrNvvPhQhE0Fo06H7ntkbbhaxVOeAUFW0b/O3RpNEzfAZUVkPtOM4PYBrT/VkWI8ERsXzCHwuFBpUkhUW96vOg/jAKmpIOSR/RkMytNMtE09Q==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=YBalSvz+k8Rxb97TogcGHAO12dF/GXvtygb+BZqeUCI=;\n b=B9X6bL4bJYnL0+eNGAYgVhL2S7XQJw3yn/aACHVWE8cfnVq+2KV9ITRyCoTKmkX6GUsb+arb6RVXhJEr7lPncTzkOPOcx0vwnUGaxkBIUz9WGrrCSIEDfZD4Mf6Hy7rXSB2rdMk1lgecCbHUhZ9KVUUVxJ65dxQS85ILNpcK/RyPRhv+TFY+QxjcuUqOmj5NduXTUm9Tmsr04XSIW+l49Foo1eWDb0Ej82G7Vbnyc6WZ4kXaYEj/Ssh2FE5/S6aCdM4l0glpa0PlW0ZQp2RgS2bGCPQ4aAI2G/fyu9Srhd9xXzoxXEi4/nyawhZewN8NsRr/W/aGUosvlBW8QEPMAA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.161) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=YBalSvz+k8Rxb97TogcGHAO12dF/GXvtygb+BZqeUCI=;\n b=dm9YP2rQJ3KnWWb/vBMRP50efE1TIkASOJZgzD+PO/LCpUiFXprY6E0ZgBbPqBKlrpSnCz/yPm3n0GQqWQkQLX7dRn1xXchsDy+Z+cAzXmNKfDf/0CQotUcuiB57RAaSZ2mSDo1BtWK1FwURB6+wxo2G301gd4DD+hZ06lxJwvYTXPY0ehkK4GTxIVA8cKuakdQY3mX8NHRk8B1tbq0wuwGfLzGDFyzVRtkAyjVihqKNcbhyJEAohjVJoXP6ZTy8/2giDyJ1l+VjAA6pNQUJ8EvvOoZswwAk5BGxWntRQDiBM4MVjJaJn5lReLNRk59JE7YR+Plo4ft4nuL59oEe8g==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, Hamdan Igbaria <hamdani@nvidia.com>", "Subject": "[v3 17/18] net/mlx5/hws: Add HWS debug layer", "Date": "Fri, 14 Oct 2022 14:48:32 +0300", "Message-ID": "<20221014114833.13389-18-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221014114833.13389-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221014114833.13389-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT048:EE_|SA1PR12MB6896:EE_", "X-MS-Office365-Filtering-Correlation-Id": "4d12df06-ca4f-4bce-d2f3-08daadda38e7", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n mrRIS6iajfZBpiWDPcBhbWbahAsOQW0WYLA2mQCwf13Tt31KerP44Je7wIT/7qW+t0wyXv4dek32SF1XPgJnyToXb969PkTss0ch2aqzMT6t5Grwvm/56ewdjqjd8sOz3doL2oh0fyL/fTrGQcSarTClj4VwZvflXE+TsLw29m1voXxt5jWveT+v+6+TwCTaX/JfRRGUHz/8VEfMdwFH655+Ar+nvv8/2Efytdm4fZLY0CN5RBwnsLoHeSzKesJMJawd+iGOaXo23iCkiTud7BGoeqCw/eybFjuwnzwIiftCgN1L53dAM60oq62inz+Bw64sdzl7kYXlOfRXYqgHQtkZnS58y78r3TtrmaTE1Ns9zMM9JUU7guFwRwxUF/k9qXbDmQCdzbA2GGRt944/hOu4lJGMvOwKk7A9hcSnixHJiAf14jbSKRUlaOE5GdiIgsv9BcPStc0HZQpQ1KqFlnXGPsQN1wI3ritV8ijQ9kSg57E9vQ+LMnRWeZx1SZVYwREfaliimBBuaxeimiE3Kpr42vY9yK+ER2msQGCvRLc3EDS/nrRwESfMPOhm7h4ra7KsfcYJ/mbRs9pEjDzqNRBfIwgb2Yj5qN+KR/XsGbDnjcxUXCmXjCpLfj+0pMN7XYParF5ZJL9Mdysm7+PRL+OnacKKRZHpZFAdjnPGhAwE7iaXfh3w8JNXU3z2RGfvXAL6bJ9IHyvIf1smGBMJ3RntnMWM3/hPI9KCN/YLP54ycqxVCZUQIsLG7PJKP8K9yaOLq7YaxzbdYOFhiN+qMQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(396003)(376002)(39860400002)(346002)(136003)(451199015)(36840700001)(46966006)(40470700004)(107886003)(478600001)(6286002)(6666004)(7696005)(82740400003)(356005)(40480700001)(82310400005)(7636003)(55016003)(26005)(40460700003)(336012)(16526019)(86362001)(47076005)(426003)(2616005)(186003)(1076003)(83380400001)(5660300002)(36860700001)(30864003)(36756003)(110136005)(2906002)(70206006)(70586007)(8676002)(8936002)(41300700001)(6636002)(54906003)(316002)(4326008);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "14 Oct 2022 11:49:59.4445 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 4d12df06-ca4f-4bce-d2f3-08daadda38e7", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT048.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR12MB6896", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Hamdan Igbaria <hamdani@nvidia.com>\n\nThe debug layer is used to generate a debug CSV file\ncontaining details of the context, table, matcher, rules\nand other useful debug information.\n\nSigned-off-by: Hamdan Igbaria <hamdani@nvidia.com>\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_debug.c | 462 ++++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_debug.h | 28 ++\n 2 files changed, 490 insertions(+)\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_debug.c\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_debug.h", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_debug.c b/drivers/net/mlx5/hws/mlx5dr_debug.c\nnew file mode 100644\nindex 0000000000..890a761c48\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_debug.c\n@@ -0,0 +1,462 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#include \"mlx5dr_internal.h\"\n+\n+const char *mlx5dr_debug_action_type_str[] = {\n+\t[MLX5DR_ACTION_TYP_LAST] = \"LAST\",\n+\t[MLX5DR_ACTION_TYP_TNL_L2_TO_L2] = \"TNL_L2_TO_L2\",\n+\t[MLX5DR_ACTION_TYP_L2_TO_TNL_L2] = \"L2_TO_TNL_L2\",\n+\t[MLX5DR_ACTION_TYP_TNL_L3_TO_L2] = \"TNL_L3_TO_L2\",\n+\t[MLX5DR_ACTION_TYP_L2_TO_TNL_L3] = \"L2_TO_TNL_L3\",\n+\t[MLX5DR_ACTION_TYP_DROP] = \"DROP\",\n+\t[MLX5DR_ACTION_TYP_TIR] = \"TIR\",\n+\t[MLX5DR_ACTION_TYP_FT] = \"FT\",\n+\t[MLX5DR_ACTION_TYP_CTR] = \"CTR\",\n+\t[MLX5DR_ACTION_TYP_TAG] = \"TAG\",\n+\t[MLX5DR_ACTION_TYP_MODIFY_HDR] = \"MODIFY_HDR\",\n+\t[MLX5DR_ACTION_TYP_VPORT] = \"VPORT\",\n+\t[MLX5DR_ACTION_TYP_MISS] = \"DEFAULT_MISS\",\n+\t[MLX5DR_ACTION_TYP_POP_VLAN] = \"POP_VLAN\",\n+\t[MLX5DR_ACTION_TYP_PUSH_VLAN] = \"PUSH_VLAN\",\n+\t[MLX5DR_ACTION_TYP_ASO_METER] = \"ASO_METER\",\n+\t[MLX5DR_ACTION_TYP_ASO_CT] = \"ASO_CT\",\n+};\n+\n+static_assert(ARRAY_SIZE(mlx5dr_debug_action_type_str) == MLX5DR_ACTION_TYP_MAX,\n+\t \"Missing mlx5dr_debug_action_type_str\");\n+\n+const char *mlx5dr_debug_action_type_to_str(enum mlx5dr_action_type action_type)\n+{\n+\treturn mlx5dr_debug_action_type_str[action_type];\n+}\n+\n+static int\n+mlx5dr_debug_dump_matcher_template_definer(FILE *f,\n+\t\t\t\t\t struct mlx5dr_match_template *mt)\n+{\n+\tstruct mlx5dr_definer *definer = mt->definer;\n+\tint i, ret;\n+\n+\tret = fprintf(f, \"%d,0x%\" PRIx64 \",0x%\" PRIx64 \",%d,%d,\",\n+\t\t MLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_DEFINER,\n+\t\t (uint64_t)(uintptr_t)definer,\n+\t\t (uint64_t)(uintptr_t)mt,\n+\t\t definer->obj->id,\n+\t\t definer->type);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tfor (i = 0; i < DW_SELECTORS; i++) {\n+\t\tret = fprintf(f, \"0x%x%s\", definer->dw_selector[i],\n+\t\t\t (i == DW_SELECTORS - 1) ? \",\" : \"-\");\n+\t\tif (ret < 0) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < BYTE_SELECTORS; i++) {\n+\t\tret = fprintf(f, \"0x%x%s\", definer->byte_selector[i],\n+\t\t\t (i == BYTE_SELECTORS - 1) ? \",\" : \"-\");\n+\t\tif (ret < 0) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\t}\n+\n+\tfor (i = 0; i < MLX5DR_JUMBO_TAG_SZ; i++) {\n+\t\tret = fprintf(f, \"%02x\", definer->mask.jumbo[i]);\n+\t\tif (ret < 0) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\t}\n+\n+\tret = fprintf(f, \"\\n\");\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mlx5dr_debug_dump_matcher_match_template(FILE *f, struct mlx5dr_matcher *matcher)\n+{\n+\tbool is_root = matcher->tbl->level == MLX5DR_ROOT_LEVEL;\n+\tint i, ret;\n+\n+\tfor (i = 0; i < matcher->num_of_mt; i++) {\n+\t\tstruct mlx5dr_match_template *mt = matcher->mt[i];\n+\n+\t\tret = fprintf(f, \"%d,0x%\" PRIx64 \",0x%\" PRIx64 \",%d,%d\\n\",\n+\t\t\t MLX5DR_DEBUG_RES_TYPE_MATCHER_MATCH_TEMPLATE,\n+\t\t\t (uint64_t)(uintptr_t)mt,\n+\t\t\t (uint64_t)(uintptr_t)matcher,\n+\t\t\t is_root ? 0 : mt->fc_sz,\n+\t\t\t mt->flags);\n+\t\tif (ret < 0) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\n+\t\tif (!is_root) {\n+\t\t\tret = mlx5dr_debug_dump_matcher_template_definer(f, mt);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mlx5dr_debug_dump_matcher_action_template(FILE *f, struct mlx5dr_matcher *matcher)\n+{\n+\tbool is_root = matcher->tbl->level == MLX5DR_ROOT_LEVEL;\n+\tenum mlx5dr_action_type action_type;\n+\tint i, j, ret;\n+\n+\tfor (i = 0; i < matcher->num_of_at; i++) {\n+\t\tstruct mlx5dr_action_template *at = matcher->at[i];\n+\n+\t\tret = fprintf(f, \"%d,0x%\" PRIx64 \",0x%\" PRIx64 \",%d,%d,%d\",\n+\t\t\t MLX5DR_DEBUG_RES_TYPE_MATCHER_ACTION_TEMPLATE,\n+\t\t\t (uint64_t)(uintptr_t)at,\n+\t\t\t (uint64_t)(uintptr_t)matcher,\n+\t\t\t at->only_term ? 0 : 1,\n+\t\t\t is_root ? 0 : at->num_of_action_stes,\n+\t\t\t at->num_actions);\n+\t\tif (ret < 0) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\n+\t\tfor (j = 0; j < at->num_actions; j++) {\n+\t\t\taction_type = at->action_type_arr[j];\n+\t\t\tret = fprintf(f, \",%s\", mlx5dr_debug_action_type_to_str(action_type));\n+\t\t\tif (ret < 0) {\n+\t\t\t\trte_errno = EINVAL;\n+\t\t\t\treturn rte_errno;\n+\t\t\t}\n+\t\t}\n+\n+\t\tfprintf(f, \"\\n\");\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mlx5dr_debug_dump_matcher_attr(FILE *f, struct mlx5dr_matcher *matcher)\n+{\n+\tstruct mlx5dr_matcher_attr *attr = &matcher->attr;\n+\tint ret;\n+\n+\tret = fprintf(f, \"%d,0x%\" PRIx64 \",%d,%d,%d,%d,%d,%d\\n\",\n+\t\t MLX5DR_DEBUG_RES_TYPE_MATCHER_ATTR,\n+\t\t (uint64_t)(uintptr_t)matcher,\n+\t\t attr->priority,\n+\t\t attr->mode,\n+\t\t attr->table.sz_row_log,\n+\t\t attr->table.sz_col_log,\n+\t\t attr->optimize_using_rule_idx,\n+\t\t attr->optimize_flow_src);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mlx5dr_debug_dump_matcher(FILE *f, struct mlx5dr_matcher *matcher)\n+{\n+\tbool is_root = matcher->tbl->level == MLX5DR_ROOT_LEVEL;\n+\tenum mlx5dr_table_type tbl_type = matcher->tbl->type;\n+\tstruct mlx5dr_devx_obj *ste_0, *ste_1 = NULL;\n+\tstruct mlx5dr_pool_chunk *ste;\n+\tstruct mlx5dr_pool *ste_pool;\n+\tint ret;\n+\n+\tret = fprintf(f, \"%d,0x%\" PRIx64 \",0x%\" PRIx64 \",%d,%d,0x%\" PRIx64,\n+\t\t MLX5DR_DEBUG_RES_TYPE_MATCHER,\n+\t\t (uint64_t)(uintptr_t)matcher,\n+\t\t (uint64_t)(uintptr_t)matcher->tbl,\n+\t\t matcher->num_of_mt,\n+\t\t is_root ? 0 : matcher->end_ft->id,\n+\t\t matcher->col_matcher ? (uint64_t)(uintptr_t)matcher->col_matcher : 0);\n+\tif (ret < 0)\n+\t\tgoto out_err;\n+\n+\tste = &matcher->match_ste.ste;\n+\tste_pool = matcher->match_ste.pool;\n+\tif (ste_pool) {\n+\t\tste_0 = mlx5dr_pool_chunk_get_base_devx_obj(ste_pool, ste);\n+\t\tif (tbl_type == MLX5DR_TABLE_TYPE_FDB)\n+\t\t\tste_1 = mlx5dr_pool_chunk_get_base_devx_obj_mirror(ste_pool, ste);\n+\t} else {\n+\t\tste_0 = NULL;\n+\t\tste_1 = NULL;\n+\t}\n+\n+\tret = fprintf(f, \",%d,%d,%d,%d\",\n+\t\t matcher->match_ste.rtc_0 ? matcher->match_ste.rtc_0->id : 0,\n+\t\t ste_0 ? (int)ste_0->id : -1,\n+\t\t matcher->match_ste.rtc_1 ? matcher->match_ste.rtc_1->id : 0,\n+\t\t ste_1 ? (int)ste_1->id : -1);\n+\tif (ret < 0)\n+\t\tgoto out_err;\n+\n+\tste = &matcher->action_ste.ste;\n+\tste_pool = matcher->action_ste.pool;\n+\tif (ste_pool) {\n+\t\tste_0 = mlx5dr_pool_chunk_get_base_devx_obj(ste_pool, ste);\n+\t\tif (tbl_type == MLX5DR_TABLE_TYPE_FDB)\n+\t\t\tste_1 = mlx5dr_pool_chunk_get_base_devx_obj_mirror(ste_pool, ste);\n+\t} else {\n+\t\tste_0 = NULL;\n+\t\tste_1 = NULL;\n+\t}\n+\n+\tret = fprintf(f, \",%d,%d,%d,%d\\n\",\n+\t\t matcher->action_ste.rtc_0 ? matcher->action_ste.rtc_0->id : 0,\n+\t\t ste_0 ? (int)ste_0->id : -1,\n+\t\t matcher->action_ste.rtc_1 ? matcher->action_ste.rtc_1->id : 0,\n+\t\t ste_1 ? (int)ste_1->id : -1);\n+\tif (ret < 0)\n+\t\tgoto out_err;\n+\n+\tret = mlx5dr_debug_dump_matcher_attr(f, matcher);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mlx5dr_debug_dump_matcher_match_template(f, matcher);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mlx5dr_debug_dump_matcher_action_template(f, matcher);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+\n+out_err:\n+\trte_errno = EINVAL;\n+\treturn rte_errno;\n+}\n+\n+static int mlx5dr_debug_dump_table(FILE *f, struct mlx5dr_table *tbl)\n+{\n+\tbool is_root = tbl->level == MLX5DR_ROOT_LEVEL;\n+\tstruct mlx5dr_matcher *matcher;\n+\tint ret;\n+\n+\tret = fprintf(f, \"%d,0x%\" PRIx64 \",0x%\" PRIx64 \",%d,%d,%d,%d\\n\",\n+\t\t MLX5DR_DEBUG_RES_TYPE_TABLE,\n+\t\t (uint64_t)(uintptr_t)tbl,\n+\t\t (uint64_t)(uintptr_t)tbl->ctx,\n+\t\t is_root ? 0 : tbl->ft->id,\n+\t\t tbl->type,\n+\t\t is_root ? 0 : tbl->fw_ft_type,\n+\t\t tbl->level);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tLIST_FOREACH(matcher, &tbl->head, next) {\n+\t\tret = mlx5dr_debug_dump_matcher(f, matcher);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+mlx5dr_debug_dump_context_send_engine(FILE *f, struct mlx5dr_context *ctx)\n+{\n+\tstruct mlx5dr_send_engine *send_queue;\n+\tint ret, i, j;\n+\n+\tfor (i = 0; i < (int)ctx->queues; i++) {\n+\t\tsend_queue = &ctx->send_queue[i];\n+\t\tret = fprintf(f, \"%d,0x%\" PRIx64 \",%d,%d,%d,%d,%d,%d,%d,%d,%d\\n\",\n+\t\t\t MLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_ENGINE,\n+\t\t\t (uint64_t)(uintptr_t)ctx,\n+\t\t\t i,\n+\t\t\t send_queue->used_entries,\n+\t\t\t send_queue->th_entries,\n+\t\t\t send_queue->rings,\n+\t\t\t send_queue->num_entries,\n+\t\t\t send_queue->err,\n+\t\t\t send_queue->completed.ci,\n+\t\t\t send_queue->completed.pi,\n+\t\t\t send_queue->completed.mask);\n+\t\tif (ret < 0) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn rte_errno;\n+\t\t}\n+\n+\t\tfor (j = 0; j < MLX5DR_NUM_SEND_RINGS; j++) {\n+\t\t\tstruct mlx5dr_send_ring *send_ring = &send_queue->send_ring[j];\n+\t\t\tstruct mlx5dr_send_ring_cq *cq = &send_ring->send_cq;\n+\t\t\tstruct mlx5dr_send_ring_sq *sq = &send_ring->send_sq;\n+\n+\t\t\tret = fprintf(f, \"%d,0x%\" PRIx64 \",%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\\n\",\n+\t\t\t\t MLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_RING,\n+\t\t\t\t (uint64_t)(uintptr_t)ctx,\n+\t\t\t\t j,\n+\t\t\t\t i,\n+\t\t\t\t cq->cqn,\n+\t\t\t\t cq->cons_index,\n+\t\t\t\t cq->ncqe_mask,\n+\t\t\t\t cq->buf_sz,\n+\t\t\t\t cq->ncqe,\n+\t\t\t\t cq->cqe_log_sz,\n+\t\t\t\t cq->poll_wqe,\n+\t\t\t\t cq->cqe_sz,\n+\t\t\t\t sq->sqn,\n+\t\t\t\t sq->obj->id,\n+\t\t\t\t sq->cur_post,\n+\t\t\t\t sq->buf_mask);\n+\t\t\tif (ret < 0) {\n+\t\t\t\trte_errno = EINVAL;\n+\t\t\t\treturn rte_errno;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mlx5dr_debug_dump_context_caps(FILE *f, struct mlx5dr_context *ctx)\n+{\n+\tstruct mlx5dr_cmd_query_caps *caps = ctx->caps;\n+\tint ret;\n+\n+\tret = fprintf(f, \"%d,0x%\" PRIx64 \",%s,%d,%d,%d,%d,\",\n+\t\t MLX5DR_DEBUG_RES_TYPE_CONTEXT_CAPS,\n+\t\t (uint64_t)(uintptr_t)ctx,\n+\t\t caps->fw_ver,\n+\t\t caps->wqe_based_update,\n+\t\t caps->ste_format,\n+\t\t caps->ste_alloc_log_max,\n+\t\t caps->log_header_modify_argument_max_alloc);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tret = fprintf(f, \"%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\\n\",\n+\t\t caps->flex_protocols,\n+\t\t caps->rtc_reparse_mode,\n+\t\t caps->rtc_index_mode,\n+\t\t caps->ste_alloc_log_gran,\n+\t\t caps->stc_alloc_log_max,\n+\t\t caps->stc_alloc_log_gran,\n+\t\t caps->rtc_log_depth_max,\n+\t\t caps->format_select_gtpu_dw_0,\n+\t\t caps->format_select_gtpu_dw_1,\n+\t\t caps->format_select_gtpu_dw_2,\n+\t\t caps->format_select_gtpu_ext_dw_0,\n+\t\t caps->nic_ft.max_level,\n+\t\t caps->nic_ft.reparse,\n+\t\t caps->fdb_ft.max_level,\n+\t\t caps->fdb_ft.reparse,\n+\t\t caps->log_header_modify_argument_granularity);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mlx5dr_debug_dump_context_attr(FILE *f, struct mlx5dr_context *ctx)\n+{\n+\tint ret;\n+\n+\tret = fprintf(f, \"%u,0x%\" PRIx64 \",%d,%zu,%d\\n\",\n+\t\t MLX5DR_DEBUG_RES_TYPE_CONTEXT_ATTR,\n+\t\t (uint64_t)(uintptr_t)ctx,\n+\t\t ctx->pd_num,\n+\t\t ctx->queues,\n+\t\t ctx->send_queue->num_entries);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int mlx5dr_debug_dump_context_info(FILE *f, struct mlx5dr_context *ctx)\n+{\n+\tint ret;\n+\n+\tret = fprintf(f, \"%d,0x%\" PRIx64 \",%d,%s,%s\\n\",\n+\t\t MLX5DR_DEBUG_RES_TYPE_CONTEXT,\n+\t\t (uint64_t)(uintptr_t)ctx,\n+\t\t ctx->flags & MLX5DR_CONTEXT_FLAG_HWS_SUPPORT,\n+\t\t mlx5_glue->get_device_name(ctx->ibv_ctx->device),\n+\t\t DEBUG_VERSION);\n+\tif (ret < 0) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tret = mlx5dr_debug_dump_context_attr(f, ctx);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mlx5dr_debug_dump_context_caps(f, ctx);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static int mlx5dr_debug_dump_context(FILE *f, struct mlx5dr_context *ctx)\n+{\n+\tstruct mlx5dr_table *tbl;\n+\tint ret;\n+\n+\tret = mlx5dr_debug_dump_context_info(f, ctx);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = mlx5dr_debug_dump_context_send_engine(f, ctx);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tLIST_FOREACH(tbl, &ctx->head, next) {\n+\t\tret = mlx5dr_debug_dump_table(f, tbl);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int mlx5dr_debug_dump(struct mlx5dr_context *ctx, FILE *f)\n+{\n+\tint ret;\n+\n+\tif (!f || !ctx) {\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\n+\tpthread_spin_lock(&ctx->ctrl_lock);\n+\tret = mlx5dr_debug_dump_context(f, ctx);\n+\tpthread_spin_unlock(&ctx->ctrl_lock);\n+\n+\treturn -ret;\n+}\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_debug.h b/drivers/net/mlx5/hws/mlx5dr_debug.h\nnew file mode 100644\nindex 0000000000..cf00170f7d\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_debug.h\n@@ -0,0 +1,28 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#ifndef MLX5DR_DEBUG_H_\n+#define MLX5DR_DEBUG_H_\n+\n+#define DEBUG_VERSION \"1.0.DPDK\"\n+\n+enum mlx5dr_debug_res_type {\n+\tMLX5DR_DEBUG_RES_TYPE_CONTEXT = 4000,\n+\tMLX5DR_DEBUG_RES_TYPE_CONTEXT_ATTR = 4001,\n+\tMLX5DR_DEBUG_RES_TYPE_CONTEXT_CAPS = 4002,\n+\tMLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_ENGINE = 4003,\n+\tMLX5DR_DEBUG_RES_TYPE_CONTEXT_SEND_RING = 4004,\n+\n+\tMLX5DR_DEBUG_RES_TYPE_TABLE = 4100,\n+\n+\tMLX5DR_DEBUG_RES_TYPE_MATCHER = 4200,\n+\tMLX5DR_DEBUG_RES_TYPE_MATCHER_ATTR = 4201,\n+\tMLX5DR_DEBUG_RES_TYPE_MATCHER_MATCH_TEMPLATE = 4202,\n+\tMLX5DR_DEBUG_RES_TYPE_MATCHER_ACTION_TEMPLATE = 4204,\n+\tMLX5DR_DEBUG_RES_TYPE_MATCHER_TEMPLATE_DEFINER = 4203,\n+};\n+\n+const char *mlx5dr_debug_action_type_to_str(enum mlx5dr_action_type action_type);\n+\n+#endif /* MLX5DR_DEBUG_H_ */\n", "prefixes": [ "v3", "17/18" ] }