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GET /api/patches/118209/?format=api
{ "id": 118209, "url": "http://patches.dpdk.org/api/patches/118209/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221014114833.13389-7-valex@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221014114833.13389-7-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221014114833.13389-7-valex@nvidia.com", "date": "2022-10-14T11:48:21", "name": "[v3,06/18] net/mlx5: provide the available tag registers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2aa8c2267430e19094a2942733e0e899c0607919", "submitter": { "id": 2858, "url": "http://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221014114833.13389-7-valex@nvidia.com/mbox/", "series": [ { "id": 25236, "url": "http://patches.dpdk.org/api/series/25236/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25236", "date": "2022-10-14T11:48:15", "name": "net/mlx5: Add HW steering low level support", "version": 3, "mbox": "http://patches.dpdk.org/series/25236/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/118209/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/118209/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2C8DFA00C2;\n\tFri, 14 Oct 2022 13:50:14 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7D69042D8E;\n\tFri, 14 Oct 2022 13:49:36 +0200 (CEST)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2042.outbound.protection.outlook.com [40.107.93.42])\n by mails.dpdk.org (Postfix) with ESMTP id D0DE642D8E\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>, Bing Zhao <bingz@nvidia.com>", "Subject": "[v3 06/18] net/mlx5: provide the available tag registers", "Date": "Fri, 14 Oct 2022 14:48:21 +0300", "Message-ID": "<20221014114833.13389-7-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221014114833.13389-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221014114833.13389-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT093:EE_|BL1PR12MB5064:EE_", "X-MS-Office365-Filtering-Correlation-Id": "89b66372-b8f5-4a1d-3306-08daadda27d2", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n SghlwPFpSRSZ9DxaVeg49Z9SJuPvuJdJZLzYTs7XknkSjrlCghWNjq0uQlntBvijMoBf337z18fDlBWfBkh9cFWkxYzKfx6ppdWb65ke/WSEpdyvkDl+azUi1o3SrriTC/mlsi1TFz6JTya5c1u4ng5u1ul4Mrot8FXJwH81Buc9b9mmkP7BMh9y72zmM9boZX5eAG6zM1tNFJ8Psigd/cyrp+CATFj4ghbmGrTNSPfGaZI4IP0Vv68i4AlFj8uJlJRCQBBJ1UnUPqRiE/+AO+skV0QgkdcgmVbQixgxhsWqCQ3C5uwttFrxyz2nXe8rFQJ6jzkNyEdVev37k8FxYeiRCcUiE02QomPASkQ8VkBInS2xLdiWk11qp4zfTYCB1gr/v6R8Bp3AF/nCVylQzVWUKKIMMqkAtcsJk5K00KvnIjdGmCpyUrkz+fZEtWiAWL4KmejDNPUAxVl/9zZEu+5erd15TGy9M6mDRWyRUiSRVqRL9fMH/nRdnofTepikjq8rUurgTuLjqCW17gKNiBFKzWFWEuu8UWyvdsXecYnOYqSySOiOjDahjpAgYPpKuJHUp123ebTL4eJquNkdMzW28+f9vVwMavcmx6Wo6vmqHIGbjnu6bSI3SNSp3Sx8FamXwOjnVaHnR/YuZB1/0pfcYaHUgi5eXa8H23FK2B6YPKwxdXepcsKn0yXG2Qsj5GlHFJH1d/TG2ld7aElUWuFV4TF3gWIvdQkaYnlR6RbchFvfYTJm4wrE6Doqc/zubPW+JYxJ0pgdmVpfQ7IyLAHJ+INSIJVWx6Y7ELPZ+EU=", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(136003)(396003)(376002)(346002)(39860400002)(451199015)(46966006)(40470700004)(36840700001)(54906003)(6636002)(110136005)(316002)(478600001)(70206006)(107886003)(6666004)(70586007)(4326008)(8676002)(26005)(6286002)(7696005)(41300700001)(186003)(1076003)(16526019)(5660300002)(8936002)(2906002)(336012)(2616005)(426003)(47076005)(83380400001)(36756003)(36860700001)(82740400003)(82310400005)(7636003)(356005)(55016003)(40480700001)(86362001)(40460700003)(21314003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "14 Oct 2022 11:49:30.6878 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 89b66372-b8f5-4a1d-3306-08daadda27d2", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT093.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL1PR12MB5064", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Bing Zhao <bingz@nvidia.com>\n\nThe available tags that can be used by the application are fixed\nafter startup.\n\nA global array is used to store the information and transfer the TAG\nitem directly from the ID to the REG_C_x.\n\nSigned-off-by: Bing Zhao <bingz@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 2 +\n drivers/net/mlx5/mlx5.c | 2 +\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_defs.h | 2 +\n drivers/net/mlx5/mlx5_flow.c | 11 +++++\n drivers/net/mlx5/mlx5_flow.h | 27 ++++++++++++\n drivers/net/mlx5/mlx5_flow_hw.c | 76 ++++++++++++++++++++++++++++++++\n 7 files changed, 121 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 98c6374547..aed55e6a62 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1545,6 +1545,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n \t\tif (priv->vport_meta_mask)\n \t\t\tflow_hw_set_port_info(eth_dev);\n+\t\t/* Only HWS requires this information. */\n+\t\tflow_hw_init_tags_set(eth_dev);\n \t\treturn eth_dev;\n #else\n \t\tDRV_LOG(ERR, \"DV support is missing for HWS.\");\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 1d10932619..b39ef1ecbe 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1945,6 +1945,8 @@ mlx5_dev_close(struct rte_eth_dev *dev)\n #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n \tflow_hw_resource_release(dev);\n \tflow_hw_clear_port_info(dev);\n+\tif (priv->sh->config.dv_flow_en == 2)\n+\t\tflow_hw_clear_tags_set(dev);\n #endif\n \tif (priv->rxq_privs != NULL) {\n \t\t/* XXX race condition if mlx5_rx_burst() is still running. */\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 3c9e6bad53..741be2df98 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1200,6 +1200,7 @@ struct mlx5_dev_ctx_shared {\n \tuint32_t drop_action_check_flag:1; /* Check Flag for drop action. */\n \tuint32_t flow_priority_check_flag:1; /* Check Flag for flow priority. */\n \tuint32_t metadata_regc_check_flag:1; /* Check Flag for metadata REGC. */\n+\tuint32_t hws_tags:1; /* Check if tags info for HWS initialized. */\n \tuint32_t max_port; /* Maximal IB device port index. */\n \tstruct mlx5_bond_info bond; /* Bonding information. */\n \tstruct mlx5_common_device *cdev; /* Backend mlx5 device. */\ndiff --git a/drivers/net/mlx5/mlx5_defs.h b/drivers/net/mlx5/mlx5_defs.h\nindex 018d3f0f0c..585afb0a98 100644\n--- a/drivers/net/mlx5/mlx5_defs.h\n+++ b/drivers/net/mlx5/mlx5_defs.h\n@@ -139,6 +139,8 @@\n #define MLX5_XMETA_MODE_META32 2\n /* Provide info on patrial hw miss. Implies MLX5_XMETA_MODE_META16 */\n #define MLX5_XMETA_MODE_MISS_INFO 3\n+/* Only valid in HWS, 32bits extended META without MARK support in FDB. */\n+#define MLX5_XMETA_MODE_META32_HWS 4\n \n /* Tx accurate scheduling on timestamps parameters. */\n #define MLX5_TXPP_WAIT_INIT_TS 1000ul /* How long to wait timestamp. */\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex bdb0613d4a..84bc471392 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -39,6 +39,17 @@\n */\n struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS];\n \n+/*\n+ * A global structure to save the available REG_C_x for tags usage.\n+ * The Meter color REG (ASO) and the last available one will be reserved\n+ * for PMD internal usage.\n+ * Since there is no \"port\" concept in the driver, it is assumed that the\n+ * available tags set will be the minimum intersection.\n+ * 3 - in FDB mode / 5 - in legacy mode\n+ */\n+uint32_t mlx5_flow_hw_avl_tags_init_cnt;\n+enum modify_reg mlx5_flow_hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX] = {REG_NON};\n+\n struct tunnel_default_miss_ctx {\n \tuint16_t *queue;\n \t__extension__\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 17102623c1..2002f6ef4b 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1331,6 +1331,10 @@ struct flow_hw_port_info {\n \n extern struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS];\n \n+#define MLX5_FLOW_HW_TAGS_MAX 8\n+extern uint32_t mlx5_flow_hw_avl_tags_init_cnt;\n+extern enum modify_reg mlx5_flow_hw_avl_tags[];\n+\n /*\n * Get metadata match tag and mask for given rte_eth_dev port.\n * Used in HWS rule creation.\n@@ -1372,9 +1376,32 @@ flow_hw_get_wire_port(struct ibv_context *ibctx)\n }\n #endif\n \n+/*\n+ * Convert metadata or tag to the actual register.\n+ * META: Can only be used to match in the FDB in this stage, fixed C_1.\n+ * TAG: C_x expect meter color reg and the reserved ones.\n+ * TODO: Per port / device, FDB or NIC for Meta matching.\n+ */\n+static __rte_always_inline int\n+flow_hw_get_reg_id(enum rte_flow_item_type type, uint32_t id)\n+{\n+\tswitch (type) {\n+\tcase RTE_FLOW_ITEM_TYPE_META:\n+\t\treturn REG_C_1;\n+\tcase RTE_FLOW_ITEM_TYPE_TAG:\n+\t\tMLX5_ASSERT(id < MLX5_FLOW_HW_TAGS_MAX);\n+\t\treturn mlx5_flow_hw_avl_tags[id];\n+\tdefault:\n+\t\treturn REG_NON;\n+\t}\n+}\n+\n void flow_hw_set_port_info(struct rte_eth_dev *dev);\n void flow_hw_clear_port_info(struct rte_eth_dev *dev);\n \n+void flow_hw_init_tags_set(struct rte_eth_dev *dev);\n+void flow_hw_clear_tags_set(struct rte_eth_dev *dev);\n+\n typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev,\n \t\t\t\t const struct rte_flow_attr *attr,\n \t\t\t\t const struct rte_flow_item items[],\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex fe809a83b9..78c741bb91 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -2237,6 +2237,82 @@ flow_hw_clear_port_info(struct rte_eth_dev *dev)\n \tinfo->is_wire = 0;\n }\n \n+/*\n+ * Initialize the information of available tag registers and an intersection\n+ * of all the probed devices' REG_C_Xs.\n+ * PS. No port concept in steering part, right now it cannot be per port level.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ */\n+void flow_hw_init_tags_set(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tuint32_t meta_mode = priv->sh->config.dv_xmeta_en;\n+\tuint8_t masks = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;\n+\tuint32_t i, j;\n+\tenum modify_reg copy[MLX5_FLOW_HW_TAGS_MAX] = {REG_NON};\n+\tuint8_t unset = 0;\n+\tuint8_t copy_masks = 0;\n+\n+\t/*\n+\t * The CAPA is global for common device but only used in net.\n+\t * It is shared per eswitch domain.\n+\t */\n+\tif (!!priv->sh->hws_tags)\n+\t\treturn;\n+\tunset |= 1 << (priv->mtr_color_reg - REG_C_0);\n+\tunset |= 1 << (REG_C_6 - REG_C_0);\n+\tif (meta_mode == MLX5_XMETA_MODE_META32_HWS) {\n+\t\tunset |= 1 << (REG_C_1 - REG_C_0);\n+\t\tunset |= 1 << (REG_C_0 - REG_C_0);\n+\t}\n+\tmasks &= ~unset;\n+\tif (mlx5_flow_hw_avl_tags_init_cnt) {\n+\t\tfor (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) {\n+\t\t\tif (mlx5_flow_hw_avl_tags[i] != REG_NON && !!((1 << i) & masks)) {\n+\t\t\t\tcopy[mlx5_flow_hw_avl_tags[i] - REG_C_0] =\n+\t\t\t\t\t\tmlx5_flow_hw_avl_tags[i];\n+\t\t\t\tcopy_masks |= (1 << i);\n+\t\t\t}\n+\t\t}\n+\t\tif (copy_masks != masks) {\n+\t\t\tj = 0;\n+\t\t\tfor (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++)\n+\t\t\t\tif (!!((1 << i) & copy_masks))\n+\t\t\t\t\tmlx5_flow_hw_avl_tags[j++] = copy[i];\n+\t\t}\n+\t} else {\n+\t\tj = 0;\n+\t\tfor (i = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) {\n+\t\t\tif (!!((1 << i) & masks))\n+\t\t\t\tmlx5_flow_hw_avl_tags[j++] =\n+\t\t\t\t\t(enum modify_reg)(i + (uint32_t)REG_C_0);\n+\t\t}\n+\t}\n+\tpriv->sh->hws_tags = 1;\n+\tmlx5_flow_hw_avl_tags_init_cnt++;\n+}\n+\n+/*\n+ * Reset the available tag registers information to NONE.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ */\n+void flow_hw_clear_tags_set(struct rte_eth_dev *dev)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\n+\tif (!priv->sh->hws_tags)\n+\t\treturn;\n+\tpriv->sh->hws_tags = 0;\n+\tmlx5_flow_hw_avl_tags_init_cnt--;\n+\tif (!mlx5_flow_hw_avl_tags_init_cnt)\n+\t\tmemset(mlx5_flow_hw_avl_tags, REG_NON,\n+\t\t sizeof(enum modify_reg) * MLX5_FLOW_HW_TAGS_MAX);\n+}\n+\n /**\n * Create shared action.\n *\n", "prefixes": [ "v3", "06/18" ] }