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GET /api/patches/118207/?format=api
{ "id": 118207, "url": "http://patches.dpdk.org/api/patches/118207/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221014114833.13389-4-valex@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221014114833.13389-4-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221014114833.13389-4-valex@nvidia.com", "date": "2022-10-14T11:48:18", "name": "[v3,03/18] net/mlx5: add hardware steering item translation function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "35f5ec70c0df86d5f202ca4576167644cf4cd639", "submitter": { "id": 2858, "url": "http://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221014114833.13389-4-valex@nvidia.com/mbox/", "series": [ { "id": 25236, "url": "http://patches.dpdk.org/api/series/25236/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25236", "date": "2022-10-14T11:48:15", "name": "net/mlx5: Add HW steering low level support", "version": 3, "mbox": "http://patches.dpdk.org/series/25236/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/118207/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/118207/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A51A1A00C2;\n\tFri, 14 Oct 2022 13:49:56 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id F271C42DC4;\n\tFri, 14 Oct 2022 13:49:28 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2040.outbound.protection.outlook.com [40.107.236.40])\n by mails.dpdk.org (Postfix) with ESMTP id 93A6242D9B\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Alex Vesker <valex@nvidia.com>", "To": "<valex@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <orika@nvidia.com>", "Subject": "[v3 03/18] net/mlx5: add hardware steering item translation function", "Date": "Fri, 14 Oct 2022 14:48:18 +0300", "Message-ID": "<20221014114833.13389-4-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221014114833.13389-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221014114833.13389-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT069:EE_|MW5PR12MB5621:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5c693ee3-9277-4655-c5b8-08daadda2345", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n GKiUXle6VIKHwPAUrJ6huwGCzBBkzCV5YIz5MuHq9eTc2mxw/Usc5U13jrdmcJBTOFzEkXmn/X/riJmOgRrFujvltDaIm9jn5vwmUEU6n1QX12el0g52ljpl3okmc3SnfonbdxsgCXHqhx2to7C3pIsDmrX1DdhMxcSkEWyu84j+kp2OgwThJSc/xWwyhc/To8Q8sJHEC3l3EgxHbJAo76nT08NpK2YmynRYEGstqZn/0ck+37QdpR191X7sAKq7sad2uLRJgpzC13xnjDoslHHI+p+30a4ht36n29Gz9xprnufQ0sF3A7JXWV+cL+pjIK8F6GYSnS5tVmRyuv7RCTo0J9DGNLsfvuHX4ZKzKq60NfAFoVneT7mBxwJj86L1DRJufJCfkwp6e4JNaoYS2Mz168OvN3W5YhsQelzItBFX/ilvcHizMaYDLQz2hxkQwCqSERbT4nm4fSSM3wsvKyA5WIC0h5x9VQJsW+6pTmum/91slg61Xh7nbLvaWGKcS0soYeI8YmcCkmJr93LFz/QCTS+AUmySttM9cT962FggHVRBBrsftCbiOAAMNq0nwNtVazsymk4uHfDAW0vJdTUdrvUYeEhGzE6qV7Xx1GLLTs5wzd96SdCBDAiT1T6LswcIyhEw3EbXTlZRvrRAW7VeVSMYRwRbvkbG1jczDzCTJhBGI+j9WFORrA8cN/wEZIsFwS8LjIbp5WNV2wre+EdzCUoqGCkSGRfYJpqkMpfzSni6xk0or3XznXIsA0kBst8poQF6cdiDVMMrA/y0kw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT069.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW5PR12MB5621", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Suanming Mou <suanmingm@nvidia.com>\n\nAs hardware steering root table flows still work under FW steering\nmode. This commit provides shared item tranlsation code for hardware\nsteering root table flows.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.c | 10 +--\n drivers/net/mlx5/mlx5_flow.h | 52 ++++++++++++-\n drivers/net/mlx5/mlx5_flow_dv.c | 134 ++++++++++++++++++++++++--------\n 3 files changed, 155 insertions(+), 41 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex e4744b0a67..81bed6f6a3 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -7108,7 +7108,7 @@ mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t txq)\n \tstruct rte_flow_item_port_id port_spec = {\n \t\t.id = MLX5_PORT_ESW_MGR,\n \t};\n-\tstruct mlx5_rte_flow_item_tx_queue txq_spec = {\n+\tstruct mlx5_rte_flow_item_sq txq_spec = {\n \t\t.queue = txq,\n \t};\n \tstruct rte_flow_item pattern[] = {\n@@ -7118,7 +7118,7 @@ mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t txq)\n \t\t},\n \t\t{\n \t\t\t.type = (enum rte_flow_item_type)\n-\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,\n+\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_SQ,\n \t\t\t.spec = &txq_spec,\n \t\t},\n \t\t{\n@@ -7504,16 +7504,16 @@ mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev,\n \t\t.egress = 1,\n \t\t.priority = 0,\n \t};\n-\tstruct mlx5_rte_flow_item_tx_queue queue_spec = {\n+\tstruct mlx5_rte_flow_item_sq queue_spec = {\n \t\t.queue = queue,\n \t};\n-\tstruct mlx5_rte_flow_item_tx_queue queue_mask = {\n+\tstruct mlx5_rte_flow_item_sq queue_mask = {\n \t\t.queue = UINT32_MAX,\n \t};\n \tstruct rte_flow_item items[] = {\n \t\t{\n \t\t\t.type = (enum rte_flow_item_type)\n-\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,\n+\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_SQ,\n \t\t\t.spec = &queue_spec,\n \t\t\t.last = NULL,\n \t\t\t.mask = &queue_mask,\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 2ebb8496f2..288e09d5ba 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -28,7 +28,7 @@\n enum mlx5_rte_flow_item_type {\n \tMLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,\n \tMLX5_RTE_FLOW_ITEM_TYPE_TAG,\n-\tMLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,\n+\tMLX5_RTE_FLOW_ITEM_TYPE_SQ,\n \tMLX5_RTE_FLOW_ITEM_TYPE_VLAN,\n \tMLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,\n };\n@@ -95,7 +95,7 @@ struct mlx5_flow_action_copy_mreg {\n };\n \n /* Matches on source queue. */\n-struct mlx5_rte_flow_item_tx_queue {\n+struct mlx5_rte_flow_item_sq {\n \tuint32_t queue;\n };\n \n@@ -159,7 +159,7 @@ enum mlx5_feature_name {\n #define MLX5_FLOW_LAYER_GENEVE (1u << 26)\n \n /* Queue items. */\n-#define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)\n+#define MLX5_FLOW_ITEM_SQ (1u << 27)\n \n /* Pattern tunnel Layer bits (continued). */\n #define MLX5_FLOW_LAYER_GTP (1u << 28)\n@@ -196,6 +196,9 @@ enum mlx5_feature_name {\n #define MLX5_FLOW_ITEM_PORT_REPRESENTOR (UINT64_C(1) << 41)\n #define MLX5_FLOW_ITEM_REPRESENTED_PORT (UINT64_C(1) << 42)\n \n+/* Meter color item */\n+#define MLX5_FLOW_ITEM_METER_COLOR (UINT64_C(1) << 44)\n+\n /* Outer Masks. */\n #define MLX5_FLOW_LAYER_OUTER_L3 \\\n \t(MLX5_FLOW_LAYER_OUTER_L3_IPV4 | MLX5_FLOW_LAYER_OUTER_L3_IPV6)\n@@ -1006,6 +1009,18 @@ flow_items_to_tunnel(const struct rte_flow_item items[])\n \treturn items[0].spec;\n }\n \n+/* HW steering flow attributes. */\n+struct mlx5_flow_attr {\n+\tuint32_t port_id; /* Port index. */\n+\tuint32_t group; /* Flow group. */\n+\tuint32_t priority; /* Original Priority. */\n+\t/* rss level, used by priority adjustment. */\n+\tuint32_t rss_level;\n+\t/* Action flags, used by priority adjustment. */\n+\tuint32_t act_flags;\n+\tuint32_t tbl_type; /* Flow table type. */\n+};\n+\n /* Flow structure. */\n struct rte_flow {\n \tuint32_t dev_handles;\n@@ -1766,6 +1781,32 @@ mlx5_translate_tunnel_etypes(uint64_t pattern_flags)\n \n int flow_hw_q_flow_flush(struct rte_eth_dev *dev,\n \t\t\t struct rte_flow_error *error);\n+\n+/*\n+ * Convert rte_mtr_color to mlx5 color.\n+ *\n+ * @param[in] rcol\n+ * rte_mtr_color.\n+ *\n+ * @return\n+ * mlx5 color.\n+ */\n+static inline int\n+rte_col_2_mlx5_col(enum rte_color rcol)\n+{\n+\tswitch (rcol) {\n+\tcase RTE_COLOR_GREEN:\n+\t\treturn MLX5_FLOW_COLOR_GREEN;\n+\tcase RTE_COLOR_YELLOW:\n+\t\treturn MLX5_FLOW_COLOR_YELLOW;\n+\tcase RTE_COLOR_RED:\n+\t\treturn MLX5_FLOW_COLOR_RED;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\treturn MLX5_FLOW_COLOR_UNDEFINED;\n+}\n+\n int mlx5_flow_group_to_table(struct rte_eth_dev *dev,\n \t\t\t const struct mlx5_flow_tunnel *tunnel,\n \t\t\t uint32_t group, uint32_t *table,\n@@ -2122,4 +2163,9 @@ int mlx5_flow_get_item_vport_id(struct rte_eth_dev *dev,\n \t\t\t\tbool *all_ports,\n \t\t\t\tstruct rte_flow_error *error);\n \n+int flow_dv_translate_items_hws(const struct rte_flow_item *items,\n+\t\t\t\tstruct mlx5_flow_attr *attr, void *key,\n+\t\t\t\tuint32_t key_type, uint64_t *item_flags,\n+\t\t\t\tuint8_t *match_criteria,\n+\t\t\t\tstruct rte_flow_error *error);\n #endif /* RTE_PMD_MLX5_FLOW_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 0589cafc30..0cf757898d 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -216,31 +216,6 @@ flow_dv_attr_init(const struct rte_flow_item *item, union flow_dv_attr *attr,\n \tattr->valid = 1;\n }\n \n-/*\n- * Convert rte_mtr_color to mlx5 color.\n- *\n- * @param[in] rcol\n- * rte_mtr_color.\n- *\n- * @return\n- * mlx5 color.\n- */\n-static inline int\n-rte_col_2_mlx5_col(enum rte_color rcol)\n-{\n-\tswitch (rcol) {\n-\tcase RTE_COLOR_GREEN:\n-\t\treturn MLX5_FLOW_COLOR_GREEN;\n-\tcase RTE_COLOR_YELLOW:\n-\t\treturn MLX5_FLOW_COLOR_YELLOW;\n-\tcase RTE_COLOR_RED:\n-\t\treturn MLX5_FLOW_COLOR_RED;\n-\tdefault:\n-\t\tbreak;\n-\t}\n-\treturn MLX5_FLOW_COLOR_UNDEFINED;\n-}\n-\n struct field_modify_info {\n \tuint32_t size; /* Size of field in protocol header, in bytes. */\n \tuint32_t offset; /* Offset of field in protocol header, in bytes. */\n@@ -7342,8 +7317,8 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t\t\t\treturn ret;\n \t\t\tlast_item = MLX5_FLOW_ITEM_TAG;\n \t\t\tbreak;\n-\t\tcase MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:\n-\t\t\tlast_item = MLX5_FLOW_ITEM_TX_QUEUE;\n+\t\tcase MLX5_RTE_FLOW_ITEM_TYPE_SQ:\n+\t\t\tlast_item = MLX5_FLOW_ITEM_SQ;\n \t\t\tbreak;\n \t\tcase MLX5_RTE_FLOW_ITEM_TYPE_TAG:\n \t\t\tbreak;\n@@ -8223,7 +8198,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t * work due to metadata regC0 mismatch.\n \t */\n \tif ((!attr->transfer && attr->egress) && priv->representor &&\n-\t !(item_flags & MLX5_FLOW_ITEM_TX_QUEUE))\n+\t !(item_flags & MLX5_FLOW_ITEM_SQ))\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t NULL,\n@@ -11242,9 +11217,9 @@ flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,\n \t\t\t\tconst struct rte_flow_item *item,\n \t\t\t\tuint32_t key_type)\n {\n-\tconst struct mlx5_rte_flow_item_tx_queue *queue_m;\n-\tconst struct mlx5_rte_flow_item_tx_queue *queue_v;\n-\tconst struct mlx5_rte_flow_item_tx_queue queue_mask = {\n+\tconst struct mlx5_rte_flow_item_sq *queue_m;\n+\tconst struct mlx5_rte_flow_item_sq *queue_v;\n+\tconst struct mlx5_rte_flow_item_sq queue_mask = {\n \t\t.queue = UINT32_MAX,\n \t};\n \tvoid *misc_v =\n@@ -13184,9 +13159,9 @@ flow_dv_translate_items(struct rte_eth_dev *dev,\n \t\tflow_dv_translate_mlx5_item_tag(dev, key, items, key_type);\n \t\tlast_item = MLX5_FLOW_ITEM_TAG;\n \t\tbreak;\n-\tcase MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:\n+\tcase MLX5_RTE_FLOW_ITEM_TYPE_SQ:\n \t\tflow_dv_translate_item_tx_queue(dev, key, items, key_type);\n-\t\tlast_item = MLX5_FLOW_ITEM_TX_QUEUE;\n+\t\tlast_item = MLX5_FLOW_ITEM_SQ;\n \t\tbreak;\n \tcase RTE_FLOW_ITEM_TYPE_GTP:\n \t\tflow_dv_translate_item_gtp(key, items, tunnel, key_type);\n@@ -13226,6 +13201,99 @@ flow_dv_translate_items(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+/**\n+ * Fill the HW steering flow with DV spec.\n+ *\n+ * @param[in] items\n+ * Pointer to the list of items.\n+ * @param[in] attr\n+ * Pointer to the flow attributes.\n+ * @param[in] key\n+ * Pointer to the flow matcher key.\n+ * @param[in] key_type\n+ * Key type.\n+ * @param[in, out] item_flags\n+ * Pointer to the flow item flags.\n+ * @param[out] error\n+ * Pointer to the error structure.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ */\n+int\n+flow_dv_translate_items_hws(const struct rte_flow_item *items,\n+\t\t\t struct mlx5_flow_attr *attr, void *key,\n+\t\t\t uint32_t key_type, uint64_t *item_flags,\n+\t\t\t uint8_t *match_criteria,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tstruct mlx5_flow_rss_desc rss_desc = { .level = attr->rss_level };\n+\tstruct rte_flow_attr rattr = {\n+\t\t.group = attr->group,\n+\t\t.priority = attr->priority,\n+\t\t.ingress = !!(attr->tbl_type == MLX5DR_TABLE_TYPE_NIC_RX),\n+\t\t.egress = !!(attr->tbl_type == MLX5DR_TABLE_TYPE_NIC_TX),\n+\t\t.transfer = !!(attr->tbl_type == MLX5DR_TABLE_TYPE_FDB),\n+\t};\n+\tstruct mlx5_dv_matcher_workspace wks = {\n+\t\t.action_flags = attr->act_flags,\n+\t\t.item_flags = item_flags ? *item_flags : 0,\n+\t\t.external = 0,\n+\t\t.next_protocol = 0xff,\n+\t\t.attr = &rattr,\n+\t\t.rss_desc = &rss_desc,\n+\t};\n+\tint ret;\n+\n+\tfor (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) {\n+\t\tif (!mlx5_flow_os_item_supported(items->type))\n+\t\t\treturn rte_flow_error_set(error, ENOTSUP,\n+\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n+\t\t\t\t\t\t NULL, \"item not supported\");\n+\t\tret = flow_dv_translate_items(&rte_eth_devices[attr->port_id],\n+\t\t\titems, &wks, key, key_type, NULL);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n+\tif (wks.item_flags & MLX5_FLOW_LAYER_VXLAN_GPE) {\n+\t\tflow_dv_translate_item_vxlan_gpe(key,\n+\t\t\t\t\t\t wks.tunnel_item,\n+\t\t\t\t\t\t wks.item_flags,\n+\t\t\t\t\t\t key_type);\n+\t} else if (wks.item_flags & MLX5_FLOW_LAYER_GENEVE) {\n+\t\tflow_dv_translate_item_geneve(key,\n+\t\t\t\t\t wks.tunnel_item,\n+\t\t\t\t\t wks.item_flags,\n+\t\t\t\t\t key_type);\n+\t} else if (wks.item_flags & MLX5_FLOW_LAYER_GRE) {\n+\t\tif (wks.tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE) {\n+\t\t\tflow_dv_translate_item_gre(key,\n+\t\t\t\t\t\t wks.tunnel_item,\n+\t\t\t\t\t\t wks.item_flags,\n+\t\t\t\t\t\t key_type);\n+\t\t} else if (wks.tunnel_item->type == RTE_FLOW_ITEM_TYPE_GRE_OPTION) {\n+\t\t\tflow_dv_translate_item_gre_option(key,\n+\t\t\t\t\t\t\t wks.tunnel_item,\n+\t\t\t\t\t\t\t wks.gre_item,\n+\t\t\t\t\t\t\t wks.item_flags,\n+\t\t\t\t\t\t\t key_type);\n+\t\t} else if (wks.tunnel_item->type == RTE_FLOW_ITEM_TYPE_NVGRE) {\n+\t\t\tflow_dv_translate_item_nvgre(key,\n+\t\t\t\t\t\t wks.tunnel_item,\n+\t\t\t\t\t\t wks.item_flags,\n+\t\t\t\t\t\t key_type);\n+\t\t} else {\n+\t\t\tMLX5_ASSERT(false);\n+\t\t}\n+\t}\n+\n+\tif (match_criteria)\n+\t\t*match_criteria = flow_dv_matcher_enable(key);\n+\tif (item_flags)\n+\t\t*item_flags = wks.item_flags;\n+\treturn 0;\n+}\n+\n /**\n * Fill the SW steering flow with DV spec.\n *\n", "prefixes": [ "v3", "03/18" ] }