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GET /api/patches/118072/?format=api
{ "id": 118072, "url": "http://patches.dpdk.org/api/patches/118072/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221012143247.3239356-1-abdullah.sevincer@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221012143247.3239356-1-abdullah.sevincer@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221012143247.3239356-1-abdullah.sevincer@intel.com", "date": "2022-10-12T14:32:47", "name": "[v1] event/dlb2: add port probing enhancements", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "42829eae1f9fe7f67c503f3dccd0b595beaeb1f6", "submitter": { "id": 2843, "url": "http://patches.dpdk.org/api/people/2843/?format=api", "name": "Sevincer, Abdullah", "email": "abdullah.sevincer@intel.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221012143247.3239356-1-abdullah.sevincer@intel.com/mbox/", "series": [ { "id": 25188, "url": "http://patches.dpdk.org/api/series/25188/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25188", "date": "2022-10-12T14:32:47", "name": "[v1] event/dlb2: add port probing enhancements", "version": 1, "mbox": "http://patches.dpdk.org/series/25188/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/118072/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/118072/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 75BF6A0543;\n\tWed, 12 Oct 2022 16:32:53 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 62D4D4307A;\n\tWed, 12 Oct 2022 16:32:53 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n by mails.dpdk.org (Postfix) with ESMTP id 3CC6B42EF7\n for <dev@dpdk.org>; Wed, 12 Oct 2022 16:32:51 +0200 (CEST)", "from fmsmga006.fm.intel.com ([10.253.24.20])\n by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Oct 2022 07:32:50 -0700", "from txanpdk02.an.intel.com ([10.123.117.76])\n by fmsmga006.fm.intel.com with ESMTP; 12 Oct 2022 07:32:49 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1665585171; x=1697121171;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=YUJlQFiF1IqDyW25mnP3ETbSPcPED3aKuy2jexMWi10=;\n b=KfQmgitA3s5s8F0cuIUWtVa3/IvaJxa9SYNu+JAH6W3ORNmwaOjwDYUt\n ji0RM0d4tjEv4Q6/P6fMLt+mcCV9KPwSZYickfW//J5Gxjrd63spJ6F1g\n xUeJ4JdwPc9tQ6s0vel9S8wsyrj2d03FoQQQl+IN3YvzrSPHNAi9J2XZ+\n n8ONfgbMQhjPtDu3sQT4Gu5JJqElA481gZwmVYDmvsCvLvZyBoZrfaLYo\n upsH51NPXZ9PY4hjbbVgeUBfOOZnF+0u6T/KWwglXNU4gv/moEoPi8U2v\n h7m6bDiGZa1VWx7iItkJZ6k7NMS0x/ZBc6DiKXnAT/6pO5H864EMRZi6A Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10497\"; a=\"331301487\"", "E=Sophos;i=\"5.95,179,1661842800\"; d=\"scan'208\";a=\"331301487\"", "E=McAfee;i=\"6500,9779,10497\"; a=\"871931372\"", "E=Sophos;i=\"5.95,179,1661842800\"; d=\"scan'208\";a=\"871931372\"" ], "X-ExtLoop1": "1", "From": "Abdullah Sevincer <abdullah.sevincer@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com, shivani.doneria@intel.com,\n Abdullah Sevincer <abdullah.sevincer@intel.com>", "Subject": "[PATCH v1] event/dlb2: add port probing enhancements", "Date": "Wed, 12 Oct 2022 09:32:47 -0500", "Message-Id": "<20221012143247.3239356-1-abdullah.sevincer@intel.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This commit is an enhancement for previously\nimplemented port probing optimizations. Changes\nare below:\n\n1-Since cos is now per port, remove the device and\ndomain specific cos from dev_args struct.\n\n2-Changes for using best cos as default cos during\nLDB port selection.\n\n3-Changed LDB_COS_DEFAULT to 255 (UINT8_MAX) from -1.\n\n4-Add check for valid producer coremask during probing dbl2\nresources.\n\nSigned-off-by: Abdullah Sevincer <abdullah.sevincer@intel.com>\n---\n drivers/event/dlb2/dlb2.c | 9 +-\n drivers/event/dlb2/dlb2_priv.h | 4 +-\n drivers/event/dlb2/dlb2_user.h | 2 +-\n drivers/event/dlb2/pf/base/dlb2_hw_types.h | 2 +-\n drivers/event/dlb2/pf/base/dlb2_resource.c | 106 +++++++++++++--------\n 5 files changed, 72 insertions(+), 51 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex 7fd89e940b..02f0e57208 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -180,11 +180,12 @@ dlb2_init_port_cos(struct dlb2_eventdev *dlb2, int *port_cos)\n {\n \tint q;\n \n-\tfor (q = 0; q < DLB2_MAX_NUM_PORTS_ALL; q++)\n+\tfor (q = 0; q < DLB2_MAX_NUM_PORTS_ALL; q++) {\n+\t\tdlb2->ev_ports[q].cos_id = port_cos[q];\n \t\tif (port_cos[q] != DLB2_COS_DEFAULT) {\n-\t\t\tdlb2->ev_ports[q].cos_id = port_cos[q];\n \t\t\tdlb2->cos_ports[port_cos[q]]++;\n \t\t}\n+\t}\n }\n \n static void\n@@ -847,10 +848,11 @@ dlb2_hw_create_sched_domain(struct dlb2_eventdev *dlb2,\n \t}\n \n \tcfg->cos_strict = 0; /* Best effort */\n-\tcfg->num_cos_ldb_ports[0] = resources_asked->num_ldb_ports - cos_ports;\n+\tcfg->num_cos_ldb_ports[0] = dlb2->cos_ports[0];\n \tcfg->num_cos_ldb_ports[1] = dlb2->cos_ports[1];\n \tcfg->num_cos_ldb_ports[2] = dlb2->cos_ports[2];\n \tcfg->num_cos_ldb_ports[3] = dlb2->cos_ports[3];\n+\tcfg->num_ldb_ports = resources_asked->num_ldb_ports - cos_ports;\n \n \tif (device_version == DLB2_HW_V2)\n \t\tcfg->num_ldb_credits = resources_asked->num_ldb_credits;\n@@ -4762,7 +4764,6 @@ dlb2_parse_params(const char *params,\n \t\t\t\t\t DLB2_NUM_DIR_CREDITS,\n \t\t\t\t\t DEV_ID_ARG,\n \t\t\t\t\t DLB2_QID_DEPTH_THRESH_ARG,\n-\t\t\t\t\t DLB2_COS_ARG,\n \t\t\t\t\t DLB2_POLL_INTERVAL_ARG,\n \t\t\t\t\t DLB2_SW_CREDIT_QUANTA_ARG,\n \t\t\t\t\t DLB2_HW_CREDIT_QUANTA_ARG,\ndiff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nindex 9ef5bcb901..085dcf9bdc 100644\n--- a/drivers/event/dlb2/dlb2_priv.h\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -40,7 +40,6 @@\n #define DLB2_NUM_DIR_CREDITS \"num_dir_credits\"\n #define DEV_ID_ARG \"dev_id\"\n #define DLB2_QID_DEPTH_THRESH_ARG \"qid_depth_thresh\"\n-#define DLB2_COS_ARG \"cos\"\n #define DLB2_POLL_INTERVAL_ARG \"poll_interval\"\n #define DLB2_SW_CREDIT_QUANTA_ARG \"sw_credit_quanta\"\n #define DLB2_HW_CREDIT_QUANTA_ARG \"hw_credit_quanta\"\n@@ -421,7 +420,7 @@ struct dlb2_config {\n };\n \n enum dlb2_cos {\n-\tDLB2_COS_DEFAULT = -1,\n+\tDLB2_COS_DEFAULT = 255,\n \tDLB2_COS_0 = 0,\n \tDLB2_COS_1,\n \tDLB2_COS_2,\n@@ -661,7 +660,6 @@ struct dlb2_devargs {\n \tint num_dir_credits_override;\n \tint dev_id;\n \tstruct dlb2_qid_depth_thresholds qid_depth_thresholds;\n-\tenum dlb2_cos cos_id;\n \tint poll_interval;\n \tint sw_credit_quanta;\n \tint hw_credit_quanta;\ndiff --git a/drivers/event/dlb2/dlb2_user.h b/drivers/event/dlb2/dlb2_user.h\nindex 28c6aaaf43..8739e2a5ac 100644\n--- a/drivers/event/dlb2/dlb2_user.h\n+++ b/drivers/event/dlb2/dlb2_user.h\n@@ -450,7 +450,7 @@ struct dlb2_create_dir_queue_args {\n * - num_hist_list_entries: Number of history list entries. This must be\n *\tgreater than or equal cq_depth.\n * - cos_id: class-of-service to allocate this port from. Must be between 0 and\n- *\t3, inclusive.\n+ *\t3, inclusive. Should be 255 if default.\n * - cos_strict: If set, return an error if there are no available ports in the\n *\trequested class-of-service. Else, allocate the port from a different\n *\tclass-of-service if the requested class has no available ports.\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_hw_types.h b/drivers/event/dlb2/pf/base/dlb2_hw_types.h\nindex 87996ef621..be09363893 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_hw_types.h\n+++ b/drivers/event/dlb2/pf/base/dlb2_hw_types.h\n@@ -351,7 +351,7 @@ struct dlb2_hw {\n \tint prod_core_list[RTE_MAX_LCORE];\n \tu8 num_prod_cores;\n \tint dir_pp_allocations[DLB2_MAX_NUM_DIR_PORTS_V2_5];\n-\tint ldb_pp_allocations[DLB2_MAX_NUM_LDB_PORTS];\n+\tint ldb_pp_allocations[DLB2_MAX_NUM_LDB_PORTS + DLB2_NUM_COS_DOMAINS];\n \n \t/* Virtualization */\n \tint virt_mode;\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex 280a8e51b1..005447f471 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -577,11 +577,14 @@ static int dlb2_attach_ldb_ports(struct dlb2_hw *hw,\n \t/* Allocate num_ldb_ports from any class-of-service */\n \tfor (i = 0; i < args->num_ldb_ports; i++) {\n \t\tfor (j = 0; j < DLB2_NUM_COS_DOMAINS; j++) {\n+\t\t\t/* Allocate from best performing cos */\n+\t\t\tu32 cos_idx = j + DLB2_MAX_NUM_LDB_PORTS;\n+\t\t\tu32 cos_id = hw->ldb_pp_allocations[cos_idx];\n \t\t\tret = __dlb2_attach_ldb_ports(hw,\n \t\t\t\t\t\t rsrcs,\n \t\t\t\t\t\t domain,\n \t\t\t\t\t\t 1,\n-\t\t\t\t\t\t j,\n+\t\t\t\t\t\t cos_id,\n \t\t\t\t\t\t resp);\n \t\t\tif (ret == 0)\n \t\t\t\tbreak;\n@@ -819,30 +822,38 @@ static int dlb2_pp_cycle_comp(const void *a, const void *b)\n \n /* Probe producer ports from different CPU cores */\n static void\n-dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type, int cos_id)\n+dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type)\n {\n+\tstruct dlb2_pp_thread_data dlb2_thread_data[DLB2_MAX_NUM_DIR_PORTS_V2_5];\n \tstruct dlb2_dev *dlb2_dev = container_of(hw, struct dlb2_dev, hw);\n-\tint i, err, ver = DLB2_HW_DEVICE_FROM_PCI_ID(dlb2_dev->pdev);\n+\tstruct dlb2_pp_thread_data cos_cycles[DLB2_NUM_COS_DOMAINS];\n+\tint ver = DLB2_HW_DEVICE_FROM_PCI_ID(dlb2_dev->pdev);\n+\tint num_ports_per_sort, num_ports, num_sort, i, err;\n \tbool is_ldb = (port_type == DLB2_LDB_PORT);\n-\tint num_ports = is_ldb ? DLB2_MAX_NUM_LDB_PORTS :\n-\tDLB2_MAX_NUM_DIR_PORTS(ver);\n-\tstruct dlb2_pp_thread_data dlb2_thread_data[num_ports];\n-\tint *port_allocations = is_ldb ? hw->ldb_pp_allocations :\n-\t\t\t\t\t hw->dir_pp_allocations;\n-\tint num_sort = is_ldb ? DLB2_NUM_COS_DOMAINS : 1;\n-\tstruct dlb2_pp_thread_data cos_cycles[num_sort];\n-\tint num_ports_per_sort = num_ports / num_sort;\n+\tint *port_allocations;\n \tpthread_t pthread;\n \n+\tif (is_ldb) {\n+\t\tport_allocations = hw->ldb_pp_allocations;\n+\t\tnum_ports = DLB2_MAX_NUM_LDB_PORTS;\n+\t\tnum_sort = DLB2_NUM_COS_DOMAINS;\n+\t} else {\n+\t\tport_allocations = hw->dir_pp_allocations;\n+\t\tnum_ports = DLB2_MAX_NUM_DIR_PORTS(ver);\n+\t\tnum_sort = 1;\n+\t}\n+\n+\tnum_ports_per_sort = num_ports / num_sort;\n+\n \tdlb2_dev->enqueue_four = dlb2_movdir64b;\n \n \tDLB2_LOG_INFO(\" for %s: cpu core used in pp profiling: %d\\n\",\n \t\t is_ldb ? \"LDB\" : \"DIR\", cpu);\n \n \tmemset(cos_cycles, 0, num_sort * sizeof(struct dlb2_pp_thread_data));\n-\tfor (i = 0; i < num_ports; i++) {\n-\t\tint cos = is_ldb ? (i >> DLB2_NUM_COS_DOMAINS) : 0;\n \n+\tfor (i = 0; i < num_ports; i++) {\n+\t\tint cos = (i >> DLB2_NUM_COS_DOMAINS) % DLB2_NUM_COS_DOMAINS;\n \t\tdlb2_thread_data[i].is_ldb = is_ldb;\n \t\tdlb2_thread_data[i].pp = i;\n \t\tdlb2_thread_data[i].cycles = 0;\n@@ -861,12 +872,17 @@ dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type, int cos_id)\n \t\t\tDLB2_LOG_ERR(\": thread join failed! err=%d\", err);\n \t\t\treturn;\n \t\t}\n-\t\tcos_cycles[cos].cycles += dlb2_thread_data[i].cycles;\n+\n+\t\tif (is_ldb)\n+\t\t\tcos_cycles[cos].cycles += dlb2_thread_data[i].cycles;\n \n \t\tif ((i + 1) % num_ports_per_sort == 0) {\n-\t\t\tint index = cos * num_ports_per_sort;\n+\t\t\tint index = 0;\n \n-\t\t\tcos_cycles[cos].pp = index;\n+\t\t\tif (is_ldb) {\n+\t\t\t\tcos_cycles[cos].pp = cos;\n+\t\t\t\tindex = cos * num_ports_per_sort;\n+\t\t\t}\n \t\t\t/*\n \t\t\t * For LDB ports first sort with in a cos. Later sort\n \t\t\t * the best cos based on total cycles for the cos.\n@@ -880,35 +896,31 @@ dlb2_get_pp_allocation(struct dlb2_hw *hw, int cpu, int port_type, int cos_id)\n \t}\n \n \t/*\n-\t * Re-arrange best ports by cos if default cos is used.\n+\t * Sort by best cos aggregated over all ports per cos\n+\t * Note: After DLB2_MAX_NUM_LDB_PORTS sorted cos is stored and so'pp'\n+\t * is cos_id and not port id.\n \t */\n-\tif (is_ldb && cos_id == DLB2_COS_DEFAULT)\n-\t\tqsort(cos_cycles, num_sort,\n-\t\t sizeof(struct dlb2_pp_thread_data),\n+\tif (is_ldb) {\n+\t\tqsort(cos_cycles, num_sort, sizeof(struct dlb2_pp_thread_data),\n \t\t dlb2_pp_cycle_comp);\n+\t\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\t\tport_allocations[i + DLB2_MAX_NUM_LDB_PORTS] = cos_cycles[i].pp;\n+\t}\n \n \tfor (i = 0; i < num_ports; i++) {\n-\t\tint start = is_ldb ? cos_cycles[i / num_ports_per_sort].pp : 0;\n-\t\tint index = i % num_ports_per_sort;\n-\n-\t\tport_allocations[i] = dlb2_thread_data[start + index].pp;\n+\t\tport_allocations[i] = dlb2_thread_data[i].pp;\n \t\tDLB2_LOG_INFO(\": pp %d cycles %d\", port_allocations[i],\n-\t\t\t dlb2_thread_data[start + index].cycles);\n+\t\t\t dlb2_thread_data[i].cycles);\n \t}\n+\n }\n \n int\n dlb2_resource_probe(struct dlb2_hw *hw, const void *probe_args)\n {\n \tconst struct dlb2_devargs *args = (const struct dlb2_devargs *)probe_args;\n-\tconst char *mask = NULL;\n-\tint cpu = 0, cnt = 0, cores[RTE_MAX_LCORE];\n-\tint i, cos_id = DLB2_COS_DEFAULT;\n-\n-\tif (args) {\n-\t\tmask = (const char *)args->producer_coremask;\n-\t\tcos_id = args->cos_id;\n-\t}\n+\tconst char *mask = args ? args->producer_coremask : NULL;\n+\tint cpu = 0, cnt = 0, cores[RTE_MAX_LCORE], i;\n \n \tif (mask && rte_eal_parse_coremask(mask, cores)) {\n \t\tDLB2_LOG_ERR(\": Invalid producer coremask=%s\", mask);\n@@ -917,16 +929,15 @@ dlb2_resource_probe(struct dlb2_hw *hw, const void *probe_args)\n \n \thw->num_prod_cores = 0;\n \tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n+\t\tbool is_pcore = (mask && cores[i] != -1);\n \t\tif (rte_lcore_is_enabled(i)) {\n-\t\t\tif (mask) {\n+\t\t\tif (is_pcore) {\n \t\t\t\t/*\n \t\t\t\t * Populate the producer cores from parsed\n \t\t\t\t * coremask\n \t\t\t\t */\n-\t\t\t\tif (cores[i] != -1) {\n-\t\t\t\t\thw->prod_core_list[cores[i]] = i;\n-\t\t\t\t\thw->num_prod_cores++;\n-\t\t\t\t}\n+\t\t\t\thw->prod_core_list[cores[i]] = i;\n+\t\t\t\thw->num_prod_cores++;\n \t\t\t} else if ((++cnt == DLB2_EAL_PROBE_CORE ||\n \t\t\t rte_lcore_count() < DLB2_EAL_PROBE_CORE)) {\n \t\t\t\t/*\n@@ -936,14 +947,18 @@ dlb2_resource_probe(struct dlb2_hw *hw, const void *probe_args)\n \t\t\t\tcpu = i;\n \t\t\t\tbreak;\n \t\t\t}\n+\t\t} else if (is_pcore) {\n+\t\t\tDLB2_LOG_ERR(\"Producer coremask(%s) must be a subset of EAL coremask\",\n+\t\t\t\t mask);\n+\t\t\treturn -1;\n \t\t}\n \t}\n \t/* Use the first core in producer coremask to probe */\n \tif (hw->num_prod_cores)\n \t\tcpu = hw->prod_core_list[0];\n \n-\tdlb2_get_pp_allocation(hw, cpu, DLB2_LDB_PORT, cos_id);\n-\tdlb2_get_pp_allocation(hw, cpu, DLB2_DIR_PORT, DLB2_COS_DEFAULT);\n+\tdlb2_get_pp_allocation(hw, cpu, DLB2_LDB_PORT);\n+\tdlb2_get_pp_allocation(hw, cpu, DLB2_DIR_PORT);\n \n \treturn 0;\n }\n@@ -4543,7 +4558,8 @@ dlb2_verify_create_ldb_port_args(struct dlb2_hw *hw,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (args->cos_id >= DLB2_NUM_COS_DOMAINS) {\n+\tif (args->cos_id >= DLB2_NUM_COS_DOMAINS &&\n+\t (args->cos_id != DLB2_COS_DEFAULT || args->cos_strict)) {\n \t\tresp->status = DLB2_ST_INVALID_COS_ID;\n \t\treturn -EINVAL;\n \t}\n@@ -4554,7 +4570,13 @@ dlb2_verify_create_ldb_port_args(struct dlb2_hw *hw,\n \t\t\t\t\t typeof(*port));\n \t} else {\n \t\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n-\t\t\tid = (args->cos_id + i) % DLB2_NUM_COS_DOMAINS;\n+\t\t\tif (args->cos_id == DLB2_COS_DEFAULT) {\n+\t\t\t\t/* Allocate from best performing cos */\n+\t\t\t\tu32 cos_idx = i + DLB2_MAX_NUM_LDB_PORTS;\n+\t\t\t\tid = hw->ldb_pp_allocations[cos_idx];\n+\t\t\t} else {\n+\t\t\t\tid = (args->cos_id + i) % DLB2_NUM_COS_DOMAINS;\n+\t\t\t}\n \n \t\t\tport = DLB2_DOM_LIST_HEAD(domain->avail_ldb_ports[id],\n \t\t\t\t\t\t typeof(*port));\n", "prefixes": [ "v1" ] }