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{
    "id": 117659,
    "url": "http://patches.dpdk.org/api/patches/117659/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221007213851.31524-14-nicolas.chautru@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20221007213851.31524-14-nicolas.chautru@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20221007213851.31524-14-nicolas.chautru@intel.com",
    "date": "2022-10-07T21:38:50",
    "name": "[v9,13/14] baseband/acc: add PF configure companion function",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "7dbf2f822c643041005eb8cb2994cdbf132a2a44",
    "submitter": {
        "id": 1314,
        "url": "http://patches.dpdk.org/api/people/1314/?format=api",
        "name": "Chautru, Nicolas",
        "email": "nicolas.chautru@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patches.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221007213851.31524-14-nicolas.chautru@intel.com/mbox/",
    "series": [
        {
            "id": 25041,
            "url": "http://patches.dpdk.org/api/series/25041/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25041",
            "date": "2022-10-07T21:38:37",
            "name": "bbdev ACC200 PMD",
            "version": 9,
            "mbox": "http://patches.dpdk.org/series/25041/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/117659/comments/",
    "check": "warning",
    "checks": "http://patches.dpdk.org/api/patches/117659/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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            "E=McAfee;i=\"6500,9779,10493\"; a=\"291118518\"",
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        ],
        "X-ExtLoop1": "1",
        "From": "Nicolas Chautru <nicolas.chautru@intel.com>",
        "To": "dev@dpdk.org,\n\tgakhil@marvell.com,\n\tmaxime.coquelin@redhat.com",
        "Cc": "trix@redhat.com, mdr@ashroe.eu, bruce.richardson@intel.com,\n hemant.agrawal@nxp.com, david.marchand@redhat.com,\n stephen@networkplumber.org, hernan.vargas@intel.com,\n Nic Chautru <nicolas.chautru@intel.com>",
        "Subject": "[PATCH v9 13/14] baseband/acc: add PF configure companion function",
        "Date": "Fri,  7 Oct 2022 14:38:50 -0700",
        "Message-Id": "<20221007213851.31524-14-nicolas.chautru@intel.com>",
        "X-Mailer": "git-send-email 2.37.1",
        "In-Reply-To": "<20221007213851.31524-1-nicolas.chautru@intel.com>",
        "References": "<20221007213851.31524-1-nicolas.chautru@intel.com>",
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        "X-BeenThere": "dev@dpdk.org",
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        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "From: Nic Chautru <nicolas.chautru@intel.com>\n\nAdded configure function notably to configure the device from\nthe PF within DPDK and bbdev-test (without external dependency).\n\nSigned-off-by: Nic Chautru <nicolas.chautru@intel.com>\nAcked-by: Hernan Vargas <hernan.vargas@intel.com>\n---\n app/test-bbdev/test_bbdev_perf.c      |  71 ++++\n drivers/baseband/acc/meson.build      |   2 +-\n drivers/baseband/acc/rte_acc200_cfg.h |  48 +++\n drivers/baseband/acc/rte_acc200_pmd.c | 455 ++++++++++++++++++++++++++\n drivers/baseband/acc/version.map      |   1 +\n 5 files changed, 576 insertions(+), 1 deletion(-)\n create mode 100644 drivers/baseband/acc/rte_acc200_cfg.h",
    "diff": "diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c\nindex e46a0c3b46..ac3e62ab16 100644\n--- a/app/test-bbdev/test_bbdev_perf.c\n+++ b/app/test-bbdev/test_bbdev_perf.c\n@@ -63,6 +63,15 @@\n #define ACC100_QMGR_INVALID_IDX -1\n #define ACC100_QMGR_RR 1\n #define ACC100_QOS_GBR 0\n+#include <rte_acc200_cfg.h>\n+#define ACC200PF_DRIVER_NAME   (\"intel_acc200_pf\")\n+#define ACC200VF_DRIVER_NAME   (\"intel_acc200_vf\")\n+#define ACC200_QMGR_NUM_AQS 16\n+#define ACC200_QMGR_NUM_QGS 2\n+#define ACC200_QMGR_AQ_DEPTH 5\n+#define ACC200_QMGR_INVALID_IDX -1\n+#define ACC200_QMGR_RR 1\n+#define ACC200_QOS_GBR 0\n #endif\n \n #define OPS_CACHE_SIZE 256U\n@@ -762,6 +771,68 @@ add_bbdev_dev(uint8_t dev_id, struct rte_bbdev_info *info,\n \t\t\t\t\"Failed to configure ACC100 PF for bbdev %s\",\n \t\t\t\tinfo->dev_name);\n \t}\n+\tif ((get_init_device() == true) &&\n+\t\t(!strcmp(info->drv.driver_name, ACC200PF_DRIVER_NAME))) {\n+\t\tstruct rte_acc_conf conf;\n+\t\tunsigned int i;\n+\n+\t\tprintf(\"Configure ACC200 FEC Driver %s with default values\\n\",\n+\t\t\t\tinfo->drv.driver_name);\n+\n+\t\t/* clear default configuration before initialization */\n+\t\tmemset(&conf, 0, sizeof(struct rte_acc_conf));\n+\n+\t\t/* Always set in PF mode for built-in configuration */\n+\t\tconf.pf_mode_en = true;\n+\t\tfor (i = 0; i < RTE_ACC_NUM_VFS; ++i) {\n+\t\t\tconf.arb_dl_4g[i].gbr_threshold1 = ACC200_QOS_GBR;\n+\t\t\tconf.arb_dl_4g[i].gbr_threshold1 = ACC200_QOS_GBR;\n+\t\t\tconf.arb_dl_4g[i].round_robin_weight = ACC200_QMGR_RR;\n+\t\t\tconf.arb_ul_4g[i].gbr_threshold1 = ACC200_QOS_GBR;\n+\t\t\tconf.arb_ul_4g[i].gbr_threshold1 = ACC200_QOS_GBR;\n+\t\t\tconf.arb_ul_4g[i].round_robin_weight = ACC200_QMGR_RR;\n+\t\t\tconf.arb_dl_5g[i].gbr_threshold1 = ACC200_QOS_GBR;\n+\t\t\tconf.arb_dl_5g[i].gbr_threshold1 = ACC200_QOS_GBR;\n+\t\t\tconf.arb_dl_5g[i].round_robin_weight = ACC200_QMGR_RR;\n+\t\t\tconf.arb_ul_5g[i].gbr_threshold1 = ACC200_QOS_GBR;\n+\t\t\tconf.arb_ul_5g[i].gbr_threshold1 = ACC200_QOS_GBR;\n+\t\t\tconf.arb_ul_5g[i].round_robin_weight = ACC200_QMGR_RR;\n+\t\t\tconf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR;\n+\t\t\tconf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR;\n+\t\t\tconf.arb_fft[i].round_robin_weight = ACC200_QMGR_RR;\n+\t\t}\n+\n+\t\tconf.input_pos_llr_1_bit = true;\n+\t\tconf.output_pos_llr_1_bit = true;\n+\t\tconf.num_vf_bundles = 1; /**< Number of VF bundles to setup */\n+\n+\t\tconf.q_ul_4g.num_qgroups = ACC200_QMGR_NUM_QGS;\n+\t\tconf.q_ul_4g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;\n+\t\tconf.q_ul_4g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;\n+\t\tconf.q_ul_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;\n+\t\tconf.q_dl_4g.num_qgroups = ACC200_QMGR_NUM_QGS;\n+\t\tconf.q_dl_4g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;\n+\t\tconf.q_dl_4g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;\n+\t\tconf.q_dl_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;\n+\t\tconf.q_ul_5g.num_qgroups = ACC200_QMGR_NUM_QGS;\n+\t\tconf.q_ul_5g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;\n+\t\tconf.q_ul_5g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;\n+\t\tconf.q_ul_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;\n+\t\tconf.q_dl_5g.num_qgroups = ACC200_QMGR_NUM_QGS;\n+\t\tconf.q_dl_5g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;\n+\t\tconf.q_dl_5g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;\n+\t\tconf.q_dl_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;\n+\t\tconf.q_fft.num_qgroups = ACC200_QMGR_NUM_QGS;\n+\t\tconf.q_fft.first_qgroup_index = ACC200_QMGR_INVALID_IDX;\n+\t\tconf.q_fft.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;\n+\t\tconf.q_fft.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;\n+\n+\t\t/* setup PF with configuration information */\n+\t\tret = rte_acc200_configure(info->dev_name, &conf);\n+\t\tTEST_ASSERT_SUCCESS(ret,\n+\t\t\t\t\"Failed to configure ACC200 PF for bbdev %s\",\n+\t\t\t\tinfo->dev_name);\n+\t}\n #endif\n \t/* Let's refresh this now this is configured */\n \trte_bbdev_info_get(dev_id, info);\ndiff --git a/drivers/baseband/acc/meson.build b/drivers/baseband/acc/meson.build\nindex 63912f0621..7ae162aab8 100644\n--- a/drivers/baseband/acc/meson.build\n+++ b/drivers/baseband/acc/meson.build\n@@ -5,4 +5,4 @@ deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci']\n \n sources = files('rte_acc100_pmd.c', 'rte_acc200_pmd.c')\n \n-headers = files('rte_acc100_cfg.h')\n+headers = files('rte_acc100_cfg.h', 'rte_acc200_cfg.h')\ndiff --git a/drivers/baseband/acc/rte_acc200_cfg.h b/drivers/baseband/acc/rte_acc200_cfg.h\nnew file mode 100644\nindex 0000000000..3eea1b5848\n--- /dev/null\n+++ b/drivers/baseband/acc/rte_acc200_cfg.h\n@@ -0,0 +1,48 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ */\n+\n+#ifndef _RTE_ACC200_CFG_H_\n+#define _RTE_ACC200_CFG_H_\n+\n+/**\n+ * @file rte_acc200_cfg.h\n+ *\n+ * Functions for configuring ACC200 HW, exposed directly to applications.\n+ * Configuration related to encoding/decoding is done through the\n+ * librte_bbdev library.\n+ *\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice.\n+ */\n+\n+#include <stdint.h>\n+#include <stdbool.h>\n+#include \"rte_acc_common_cfg.h\"\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+/**\n+ * Configure a ACC200 device.\n+ *\n+ * @param dev_name\n+ *   The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.\n+ *   It can also be retrieved for a bbdev device from the dev_name field in the\n+ *   rte_bbdev_info structure returned by rte_bbdev_info_get().\n+ * @param conf\n+ *   Configuration to apply to ACC200 HW.\n+ *\n+ * @return\n+ *   Zero on success, negative value on failure.\n+ */\n+__rte_experimental\n+int\n+rte_acc200_configure(const char *dev_name, struct rte_acc_conf *conf);\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _RTE_ACC200_CFG_H_ */\ndiff --git a/drivers/baseband/acc/rte_acc200_pmd.c b/drivers/baseband/acc/rte_acc200_pmd.c\nindex fe032efc83..bb20678349 100644\n--- a/drivers/baseband/acc/rte_acc200_pmd.c\n+++ b/drivers/baseband/acc/rte_acc200_pmd.c\n@@ -43,6 +43,27 @@ queue_offset(bool pf_device, uint8_t vf_id, uint8_t qgrp_id, uint16_t aq_id)\n \n enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, FFT, NUM_ACC};\n \n+/* Return the accelerator enum for a Queue Group Index. */\n+static inline int\n+accFromQgid(int qg_idx, const struct rte_acc_conf *acc_conf)\n+{\n+\tint accQg[ACC200_NUM_QGRPS];\n+\tint NumQGroupsPerFn[NUM_ACC];\n+\tint acc, qgIdx, qgIndex = 0;\n+\tfor (qgIdx = 0; qgIdx < ACC200_NUM_QGRPS; qgIdx++)\n+\t\taccQg[qgIdx] = 0;\n+\tNumQGroupsPerFn[UL_4G] = acc_conf->q_ul_4g.num_qgroups;\n+\tNumQGroupsPerFn[UL_5G] = acc_conf->q_ul_5g.num_qgroups;\n+\tNumQGroupsPerFn[DL_4G] = acc_conf->q_dl_4g.num_qgroups;\n+\tNumQGroupsPerFn[DL_5G] = acc_conf->q_dl_5g.num_qgroups;\n+\tNumQGroupsPerFn[FFT] = acc_conf->q_fft.num_qgroups;\n+\tfor (acc = UL_4G;  acc < NUM_ACC; acc++)\n+\t\tfor (qgIdx = 0; qgIdx < NumQGroupsPerFn[acc]; qgIdx++)\n+\t\t\taccQg[qgIndex++] = acc;\n+\tacc = accQg[qg_idx];\n+\treturn acc;\n+}\n+\n /* Return the queue topology for a Queue Group Index. */\n static inline void\n qtopFromAcc(struct rte_acc_queue_topology **qtop, int acc_enum, struct rte_acc_conf *acc_conf)\n@@ -74,6 +95,36 @@ qtopFromAcc(struct rte_acc_queue_topology **qtop, int acc_enum, struct rte_acc_c\n \t*qtop = p_qtop;\n }\n \n+/* Return the AQ depth for a Queue Group Index. */\n+static inline int\n+aqDepth(int qg_idx, struct rte_acc_conf *acc_conf)\n+{\n+\tstruct rte_acc_queue_topology *q_top = NULL;\n+\n+\tint acc_enum = accFromQgid(qg_idx, acc_conf);\n+\tqtopFromAcc(&q_top, acc_enum, acc_conf);\n+\n+\tif (unlikely(q_top == NULL))\n+\t\treturn 0;\n+\n+\treturn q_top->aq_depth_log2;\n+}\n+\n+/* Return the AQ depth for a Queue Group Index. */\n+static inline int\n+aqNum(int qg_idx, struct rte_acc_conf *acc_conf)\n+{\n+\tstruct rte_acc_queue_topology *q_top = NULL;\n+\n+\tint acc_enum = accFromQgid(qg_idx, acc_conf);\n+\tqtopFromAcc(&q_top, acc_enum, acc_conf);\n+\n+\tif (unlikely(q_top == NULL))\n+\t\treturn 0;\n+\n+\treturn q_top->num_aqs_per_groups;\n+}\n+\n static void\n initQTop(struct rte_acc_conf *acc_conf)\n {\n@@ -3475,3 +3526,407 @@ RTE_PMD_REGISTER_PCI(ACC200PF_DRIVER_NAME, acc200_pci_pf_driver);\n RTE_PMD_REGISTER_PCI_TABLE(ACC200PF_DRIVER_NAME, pci_id_acc200_pf_map);\n RTE_PMD_REGISTER_PCI(ACC200VF_DRIVER_NAME, acc200_pci_vf_driver);\n RTE_PMD_REGISTER_PCI_TABLE(ACC200VF_DRIVER_NAME, pci_id_acc200_vf_map);\n+\n+/* Initial configuration of a ACC200 device prior to running configure(). */\n+int\n+rte_acc200_configure(const char *dev_name, struct rte_acc_conf *conf)\n+{\n+\trte_bbdev_log(INFO, \"rte_acc200_configure\");\n+\tuint32_t value, address, status;\n+\tint qg_idx, template_idx, vf_idx, acc, i, rlim, alen, timestamp, totalQgs, numEngines;\n+\tint numQgs, numQqsAcc;\n+\tstruct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);\n+\n+\t/* Compile time checks. */\n+\tRTE_BUILD_BUG_ON(sizeof(struct acc_dma_req_desc) != 256);\n+\tRTE_BUILD_BUG_ON(sizeof(union acc_dma_desc) != 256);\n+\tRTE_BUILD_BUG_ON(sizeof(struct acc_fcw_td) != 24);\n+\tRTE_BUILD_BUG_ON(sizeof(struct acc_fcw_te) != 32);\n+\n+\tif (bbdev == NULL) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\"Invalid dev_name (%s), or device is not yet initialised\",\n+\t\tdev_name);\n+\t\treturn -ENODEV;\n+\t}\n+\tstruct acc_device *d = bbdev->data->dev_private;\n+\n+\t/* Store configuration. */\n+\trte_memcpy(&d->acc_conf, conf, sizeof(d->acc_conf));\n+\n+\t/* Check we are already out of PG. */\n+\tstatus = acc_reg_read(d, HWPfHiSectionPowerGatingAck);\n+\tif (status > 0) {\n+\t\tif (status != ACC200_PG_MASK_0) {\n+\t\t\trte_bbdev_log(ERR, \"Unexpected status %x %x\",\n+\t\t\t\t\tstatus, ACC200_PG_MASK_0);\n+\t\t\treturn -ENODEV;\n+\t\t}\n+\t\t/* Clock gate sections that will be un-PG. */\n+\t\tacc_reg_write(d, HWPfHiClkGateHystReg, ACC200_CLK_DIS);\n+\t\t/* Un-PG required sections. */\n+\t\tacc_reg_write(d, HWPfHiSectionPowerGatingReq,\n+\t\t\t\tACC200_PG_MASK_1);\n+\t\tstatus = acc_reg_read(d, HWPfHiSectionPowerGatingAck);\n+\t\tif (status != ACC200_PG_MASK_1) {\n+\t\t\trte_bbdev_log(ERR, \"Unexpected status %x %x\",\n+\t\t\t\t\tstatus, ACC200_PG_MASK_1);\n+\t\t\treturn -ENODEV;\n+\t\t}\n+\t\tacc_reg_write(d, HWPfHiSectionPowerGatingReq,\n+\t\t\t\tACC200_PG_MASK_2);\n+\t\tstatus = acc_reg_read(d, HWPfHiSectionPowerGatingAck);\n+\t\tif (status != ACC200_PG_MASK_2) {\n+\t\t\trte_bbdev_log(ERR, \"Unexpected status %x %x\",\n+\t\t\t\t\tstatus, ACC200_PG_MASK_2);\n+\t\t\treturn -ENODEV;\n+\t\t}\n+\t\tacc_reg_write(d, HWPfHiSectionPowerGatingReq,\n+\t\t\t\tACC200_PG_MASK_3);\n+\t\tstatus = acc_reg_read(d, HWPfHiSectionPowerGatingAck);\n+\t\tif (status != ACC200_PG_MASK_3) {\n+\t\t\trte_bbdev_log(ERR, \"Unexpected status %x %x\",\n+\t\t\t\t\tstatus, ACC200_PG_MASK_3);\n+\t\t\treturn -ENODEV;\n+\t\t}\n+\t\t/* Enable clocks for all sections. */\n+\t\tacc_reg_write(d, HWPfHiClkGateHystReg, ACC200_CLK_EN);\n+\t}\n+\n+\t/* Explicitly releasing AXI as this may be stopped after PF FLR/BME. */\n+\taddress = HWPfDmaAxiControl;\n+\tvalue = 1;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Set the fabric mode. */\n+\taddress = HWPfFabricM2iBufferReg;\n+\tvalue = ACC200_FABRIC_MODE;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Set default descriptor signature. */\n+\taddress = HWPfDmaDescriptorSignatuture;\n+\tvalue = 0;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Enable the Error Detection in DMA. */\n+\tvalue = ACC200_CFG_DMA_ERROR;\n+\taddress = HWPfDmaErrorDetectionEn;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* AXI Cache configuration. */\n+\tvalue = ACC200_CFG_AXI_CACHE;\n+\taddress = HWPfDmaAxcacheReg;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Default DMA Configuration (Qmgr Enabled). */\n+\taddress = HWPfDmaConfig0Reg;\n+\tvalue = 0;\n+\tacc_reg_write(d, address, value);\n+\taddress = HWPfDmaQmanen;\n+\tvalue = 0;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Default RLIM/ALEN configuration. */\n+\trlim = 0;\n+\talen = 1;\n+\ttimestamp = 0;\n+\taddress = HWPfDmaConfig1Reg;\n+\tvalue = (1 << 31) + (rlim << 8) + (timestamp << 6) + alen;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Default FFT configuration. */\n+\taddress = HWPfFftConfig0;\n+\tvalue = ACC200_FFT_CFG_0;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Configure DMA Qmanager addresses. */\n+\taddress = HWPfDmaQmgrAddrReg;\n+\tvalue = HWPfQmgrEgressQueuesTemplate;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* ===== Qmgr Configuration ===== */\n+\t/* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL. */\n+\ttotalQgs = conf->q_ul_4g.num_qgroups +\n+\t\t\tconf->q_ul_5g.num_qgroups +\n+\t\t\tconf->q_dl_4g.num_qgroups +\n+\t\t\tconf->q_dl_5g.num_qgroups +\n+\t\t\tconf->q_fft.num_qgroups;\n+\tfor (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) {\n+\t\taddress = HWPfQmgrDepthLog2Grp +\n+\t\t\t\tACC_BYTES_IN_WORD * qg_idx;\n+\t\tvalue = aqDepth(qg_idx, conf);\n+\t\tacc_reg_write(d, address, value);\n+\t\taddress = HWPfQmgrTholdGrp +\n+\t\t\t\tACC_BYTES_IN_WORD * qg_idx;\n+\t\tvalue = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\n+\t/* Template Priority in incremental order. */\n+\tfor (template_idx = 0; template_idx < ACC_NUM_TMPL;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg0Indx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC_TMPL_PRI_0;\n+\t\tacc_reg_write(d, address, value);\n+\t\taddress = HWPfQmgrGrpTmplateReg1Indx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC_TMPL_PRI_1;\n+\t\tacc_reg_write(d, address, value);\n+\t\taddress = HWPfQmgrGrpTmplateReg2indx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC_TMPL_PRI_2;\n+\t\tacc_reg_write(d, address, value);\n+\t\taddress = HWPfQmgrGrpTmplateReg3Indx + ACC_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC_TMPL_PRI_3;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\n+\taddress = HWPfQmgrGrpPriority;\n+\tvalue = ACC200_CFG_QMGR_HI_P;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Template Configuration. */\n+\tfor (template_idx = 0; template_idx < ACC_NUM_TMPL;\n+\t\t\ttemplate_idx++) {\n+\t\tvalue = 0;\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ ACC_BYTES_IN_WORD * template_idx;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\t/* 4GUL */\n+\tnumQgs = conf->q_ul_4g.num_qgroups;\n+\tnumQqsAcc = 0;\n+\tvalue = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = ACC200_SIG_UL_4G;\n+\t\t\ttemplate_idx <= ACC200_SIG_UL_4G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ ACC_BYTES_IN_WORD * template_idx;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\t/* 5GUL */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_ul_5g.num_qgroups;\n+\tvalue = 0;\n+\tnumEngines = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = ACC200_SIG_UL_5G;\n+\t\t\ttemplate_idx <= ACC200_SIG_UL_5G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\t/* Check engine power-on status */\n+\t\taddress = HwPfFecUl5gIbDebugReg + ACC_ENGINE_OFFSET * template_idx;\n+\t\tstatus = (acc_reg_read(d, address) >> 4) & 0x7;\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ ACC_BYTES_IN_WORD * template_idx;\n+\t\tif (status == 1) {\n+\t\t\tacc_reg_write(d, address, value);\n+\t\t\tnumEngines++;\n+\t\t} else\n+\t\t\tacc_reg_write(d, address, 0);\n+\t}\n+\tprintf(\"Number of 5GUL engines %d\\n\", numEngines);\n+\t/* 4GDL */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_dl_4g.num_qgroups;\n+\tvalue = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = ACC200_SIG_DL_4G;\n+\t\t\ttemplate_idx <= ACC200_SIG_DL_4G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ ACC_BYTES_IN_WORD * template_idx;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\t/* 5GDL */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_dl_5g.num_qgroups;\n+\tvalue = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = ACC200_SIG_DL_5G;\n+\t\t\ttemplate_idx <= ACC200_SIG_DL_5G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ ACC_BYTES_IN_WORD * template_idx;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\t/* FFT */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_fft.num_qgroups;\n+\tvalue = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = ACC200_SIG_FFT;\n+\t\t\ttemplate_idx <= ACC200_SIG_FFT_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ ACC_BYTES_IN_WORD * template_idx;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\n+\t/* Queue Group Function mapping. */\n+\tint qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};\n+\tvalue = 0;\n+\tfor (qg_idx = 0; qg_idx < ACC_NUM_QGRPS_PER_WORD; qg_idx++) {\n+\t\tacc = accFromQgid(qg_idx, conf);\n+\t\tvalue |= qman_func_id[acc] << (qg_idx * 4);\n+\t}\n+\tacc_reg_write(d, HWPfQmgrGrpFunction0, value);\n+\tvalue = 0;\n+\tfor (qg_idx = 0; qg_idx < ACC_NUM_QGRPS_PER_WORD; qg_idx++) {\n+\t\tacc = accFromQgid(qg_idx + ACC_NUM_QGRPS_PER_WORD, conf);\n+\t\tvalue |= qman_func_id[acc] << (qg_idx * 4);\n+\t}\n+\tacc_reg_write(d, HWPfQmgrGrpFunction1, value);\n+\n+\t/* Configuration of the Arbitration QGroup depth to 1. */\n+\tfor (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) {\n+\t\taddress = HWPfQmgrArbQDepthGrp +\n+\t\t\t\tACC_BYTES_IN_WORD * qg_idx;\n+\t\tvalue = 0;\n+\t\tacc_reg_write(d, address, value);\n+\t}\n+\n+\t/* This pointer to ARAM (256kB) is shifted by 2 (4B per register). */\n+\tuint32_t aram_address = 0;\n+\tfor (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {\n+\t\tfor (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {\n+\t\t\taddress = HWPfQmgrVfBaseAddr + vf_idx\n+\t\t\t\t\t* ACC_BYTES_IN_WORD + qg_idx\n+\t\t\t\t\t* ACC_BYTES_IN_WORD * 64;\n+\t\t\tvalue = aram_address;\n+\t\t\tacc_reg_write(d, address, value);\n+\t\t\t/* Offset ARAM Address for next memory bank - increment of 4B */\n+\t\t\taram_address += aqNum(qg_idx, conf) *\n+\t\t\t\t\t(1 << aqDepth(qg_idx, conf));\n+\t\t}\n+\t}\n+\n+\tif (aram_address > ACC200_WORDS_IN_ARAM_SIZE) {\n+\t\trte_bbdev_log(ERR, \"ARAM Configuration not fitting %d %d\\n\",\n+\t\t\t\taram_address, ACC200_WORDS_IN_ARAM_SIZE);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Performance tuning. */\n+\tacc_reg_write(d, HWPfFabricI2Mdma_weight, 0x0FFF);\n+\tacc_reg_write(d, HWPfDma4gdlIbThld, 0x1f10);\n+\n+\t/* ==== HI Configuration ==== */\n+\n+\t/* No Info Ring/MSI by default. */\n+\taddress = HWPfHiInfoRingIntWrEnRegPf;\n+\tvalue = 0;\n+\tacc_reg_write(d, address, value);\n+\taddress = HWPfHiCfgMsiIntWrEnRegPf;\n+\tvalue = 0xFFFFFFFF;\n+\tacc_reg_write(d, address, value);\n+\t/* Prevent Block on Transmit Error. */\n+\taddress = HWPfHiBlockTransmitOnErrorEn;\n+\tvalue = 0;\n+\tacc_reg_write(d, address, value);\n+\t/* Prevents to drop MSI. */\n+\taddress = HWPfHiMsiDropEnableReg;\n+\tvalue = 0;\n+\tacc_reg_write(d, address, value);\n+\t/* Set the PF Mode register. */\n+\taddress = HWPfHiPfMode;\n+\tvalue = (conf->pf_mode_en) ? ACC_PF_VAL : 0;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* QoS overflow init. */\n+\tvalue = 1;\n+\taddress = HWPfQosmonAEvalOverflow0;\n+\tacc_reg_write(d, address, value);\n+\taddress = HWPfQosmonBEvalOverflow0;\n+\tacc_reg_write(d, address, value);\n+\n+\t/* Configure the FFT RAM LUT. */\n+\tuint32_t fft_lut[ACC200_FFT_RAM_SIZE] = {\n+\t0x1FFFF, 0x1FFFF, 0x1FFFE, 0x1FFFA, 0x1FFF6, 0x1FFF1, 0x1FFEA, 0x1FFE2,\n+\t0x1FFD9, 0x1FFCE, 0x1FFC2, 0x1FFB5, 0x1FFA7, 0x1FF98, 0x1FF87, 0x1FF75,\n+\t0x1FF62, 0x1FF4E, 0x1FF38, 0x1FF21, 0x1FF09, 0x1FEF0, 0x1FED6, 0x1FEBA,\n+\t0x1FE9D, 0x1FE7F, 0x1FE5F, 0x1FE3F, 0x1FE1D, 0x1FDFA, 0x1FDD5, 0x1FDB0,\n+\t0x1FD89, 0x1FD61, 0x1FD38, 0x1FD0D, 0x1FCE1, 0x1FCB4, 0x1FC86, 0x1FC57,\n+\t0x1FC26, 0x1FBF4, 0x1FBC1, 0x1FB8D, 0x1FB58, 0x1FB21, 0x1FAE9, 0x1FAB0,\n+\t0x1FA75, 0x1FA3A, 0x1F9FD, 0x1F9BF, 0x1F980, 0x1F93F, 0x1F8FD, 0x1F8BA,\n+\t0x1F876, 0x1F831, 0x1F7EA, 0x1F7A3, 0x1F75A, 0x1F70F, 0x1F6C4, 0x1F677,\n+\t0x1F629, 0x1F5DA, 0x1F58A, 0x1F539, 0x1F4E6, 0x1F492, 0x1F43D, 0x1F3E7,\n+\t0x1F38F, 0x1F337, 0x1F2DD, 0x1F281, 0x1F225, 0x1F1C8, 0x1F169, 0x1F109,\n+\t0x1F0A8, 0x1F046, 0x1EFE2, 0x1EF7D, 0x1EF18, 0x1EEB0, 0x1EE48, 0x1EDDF,\n+\t0x1ED74, 0x1ED08, 0x1EC9B, 0x1EC2D, 0x1EBBE, 0x1EB4D, 0x1EADB, 0x1EA68,\n+\t0x1E9F4, 0x1E97F, 0x1E908, 0x1E891, 0x1E818, 0x1E79E, 0x1E722, 0x1E6A6,\n+\t0x1E629, 0x1E5AA, 0x1E52A, 0x1E4A9, 0x1E427, 0x1E3A3, 0x1E31F, 0x1E299,\n+\t0x1E212, 0x1E18A, 0x1E101, 0x1E076, 0x1DFEB, 0x1DF5E, 0x1dED0, 0x1DE41,\n+\t0x1DDB1, 0x1DD20, 0x1DC8D, 0x1DBFA, 0x1DB65, 0x1DACF, 0x1DA38, 0x1D9A0,\n+\t0x1D907, 0x1D86C, 0x1D7D1, 0x1D734, 0x1D696, 0x1D5F7, 0x1D557, 0x1D4B6,\n+\t0x1D413, 0x1D370, 0x1D2CB, 0x1D225, 0x1D17E, 0x1D0D6, 0x1D02D, 0x1CF83,\n+\t0x1CED8, 0x1CE2B, 0x1CD7E, 0x1CCCF, 0x1CC1F, 0x1CB6E, 0x1CABC, 0x1CA09,\n+\t0x1C955, 0x1C89F, 0x1C7E9, 0x1C731, 0x1C679, 0x1C5BF, 0x1C504, 0x1C448,\n+\t0x1C38B, 0x1C2CD, 0x1C20E, 0x1C14E, 0x1C08C, 0x1BFCA, 0x1BF06, 0x1BE42,\n+\t0x1BD7C, 0x1BCB5, 0x1BBED, 0x1BB25, 0x1BA5B, 0x1B990, 0x1B8C4, 0x1B7F6,\n+\t0x1B728, 0x1B659, 0x1B589, 0x1B4B7, 0x1B3E5, 0x1B311, 0x1B23D, 0x1B167,\n+\t0x1B091, 0x1AFB9, 0x1AEE0, 0x1AE07, 0x1AD2C, 0x1AC50, 0x1AB73, 0x1AA95,\n+\t0x1A9B6, 0x1A8D6, 0x1A7F6, 0x1A714, 0x1A631, 0x1A54D, 0x1A468, 0x1A382,\n+\t0x1A29A, 0x1A1B2, 0x1A0C9, 0x19FDF, 0x19EF4, 0x19E08, 0x19D1B, 0x19C2D,\n+\t0x19B3E, 0x19A4E, 0x1995D, 0x1986B, 0x19778, 0x19684, 0x1958F, 0x19499,\n+\t0x193A2, 0x192AA, 0x191B1, 0x190B8, 0x18FBD, 0x18EC1, 0x18DC4, 0x18CC7,\n+\t0x18BC8, 0x18AC8, 0x189C8, 0x188C6, 0x187C4, 0x186C1, 0x185BC, 0x184B7,\n+\t0x183B1, 0x182AA, 0x181A2, 0x18099, 0x17F8F, 0x17E84, 0x17D78, 0x17C6C,\n+\t0x17B5E, 0x17A4F, 0x17940, 0x17830, 0x1771E, 0x1760C, 0x174F9, 0x173E5,\n+\t0x172D1, 0x171BB, 0x170A4, 0x16F8D, 0x16E74, 0x16D5B, 0x16C41, 0x16B26,\n+\t0x16A0A, 0x168ED, 0x167CF, 0x166B1, 0x16592, 0x16471, 0x16350, 0x1622E,\n+\t0x1610B, 0x15FE8, 0x15EC3, 0x15D9E, 0x15C78, 0x15B51, 0x15A29, 0x15900,\n+\t0x157D7, 0x156AC, 0x15581, 0x15455, 0x15328, 0x151FB, 0x150CC, 0x14F9D,\n+\t0x14E6D, 0x14D3C, 0x14C0A, 0x14AD8, 0x149A4, 0x14870, 0x1473B, 0x14606,\n+\t0x144CF, 0x14398, 0x14260, 0x14127, 0x13FEE, 0x13EB3, 0x13D78, 0x13C3C,\n+\t0x13B00, 0x139C2, 0x13884, 0x13745, 0x13606, 0x134C5, 0x13384, 0x13242,\n+\t0x130FF, 0x12FBC, 0x12E78, 0x12D33, 0x12BEE, 0x12AA7, 0x12960, 0x12819,\n+\t0x126D0, 0x12587, 0x1243D, 0x122F3, 0x121A8, 0x1205C, 0x11F0F, 0x11DC2,\n+\t0x11C74, 0x11B25, 0x119D6, 0x11886, 0x11735, 0x115E3, 0x11491, 0x1133F,\n+\t0x111EB, 0x11097, 0x10F42, 0x10dED, 0x10C97, 0x10B40, 0x109E9, 0x10891,\n+\t0x10738, 0x105DF, 0x10485, 0x1032B, 0x101D0, 0x10074, 0x0FF18, 0x0FDBB,\n+\t0x0FC5D, 0x0FAFF, 0x0F9A0, 0x0F841, 0x0F6E1, 0x0F580, 0x0F41F, 0x0F2BD,\n+\t0x0F15B, 0x0EFF8, 0x0EE94, 0x0ED30, 0x0EBCC, 0x0EA67, 0x0E901, 0x0E79A,\n+\t0x0E633, 0x0E4CC, 0x0E364, 0x0E1FB, 0x0E092, 0x0DF29, 0x0DDBE, 0x0DC54,\n+\t0x0DAE9, 0x0D97D, 0x0D810, 0x0D6A4, 0x0D536, 0x0D3C8, 0x0D25A, 0x0D0EB,\n+\t0x0CF7C, 0x0CE0C, 0x0CC9C, 0x0CB2B, 0x0C9B9, 0x0C847, 0x0C6D5, 0x0C562,\n+\t0x0C3EF, 0x0C27B, 0x0C107, 0x0BF92, 0x0BE1D, 0x0BCA8, 0x0BB32, 0x0B9BB,\n+\t0x0B844, 0x0B6CD, 0x0B555, 0x0B3DD, 0x0B264, 0x0B0EB, 0x0AF71, 0x0ADF7,\n+\t0x0AC7D, 0x0AB02, 0x0A987, 0x0A80B, 0x0A68F, 0x0A513, 0x0A396, 0x0A219,\n+\t0x0A09B, 0x09F1D, 0x09D9E, 0x09C20, 0x09AA1, 0x09921, 0x097A1, 0x09621,\n+\t0x094A0, 0x0931F, 0x0919E, 0x0901C, 0x08E9A, 0x08D18, 0x08B95, 0x08A12,\n+\t0x0888F, 0x0870B, 0x08587, 0x08402, 0x0827E, 0x080F9, 0x07F73, 0x07DEE,\n+\t0x07C68, 0x07AE2, 0x0795B, 0x077D4, 0x0764D, 0x074C6, 0x0733E, 0x071B6,\n+\t0x0702E, 0x06EA6, 0x06D1D, 0x06B94, 0x06A0B, 0x06881, 0x066F7, 0x0656D,\n+\t0x063E3, 0x06258, 0x060CE, 0x05F43, 0x05DB7, 0x05C2C, 0x05AA0, 0x05914,\n+\t0x05788, 0x055FC, 0x0546F, 0x052E3, 0x05156, 0x04FC9, 0x04E3B, 0x04CAE,\n+\t0x04B20, 0x04992, 0x04804, 0x04676, 0x044E8, 0x04359, 0x041CB, 0x0403C,\n+\t0x03EAD, 0x03D1D, 0x03B8E, 0x039FF, 0x0386F, 0x036DF, 0x0354F, 0x033BF,\n+\t0x0322F, 0x0309F, 0x02F0F, 0x02D7E, 0x02BEE, 0x02A5D, 0x028CC, 0x0273B,\n+\t0x025AA, 0x02419, 0x02288, 0x020F7, 0x01F65, 0x01DD4, 0x01C43, 0x01AB1,\n+\t0x0191F, 0x0178E, 0x015FC, 0x0146A, 0x012D8, 0x01147, 0x00FB5, 0x00E23,\n+\t0x00C91, 0x00AFF, 0x0096D, 0x007DB, 0x00648, 0x004B6, 0x00324, 0x00192};\n+\n+\tacc_reg_write(d, HWPfFftRamPageAccess, ACC200_FFT_RAM_EN + 64);\n+\tfor (i = 0; i < ACC200_FFT_RAM_SIZE; i++)\n+\t\tacc_reg_write(d, HWPfFftRamOff + i * 4, fft_lut[i]);\n+\tacc_reg_write(d, HWPfFftRamPageAccess, ACC200_FFT_RAM_DIS);\n+\n+\t/* Enabling AQueues through the Queue hierarchy. */\n+\tfor (vf_idx = 0; vf_idx < ACC200_NUM_VFS; vf_idx++) {\n+\t\tfor (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) {\n+\t\t\tvalue = 0;\n+\t\t\tif (vf_idx < conf->num_vf_bundles && qg_idx < totalQgs)\n+\t\t\t\tvalue = (1 << aqNum(qg_idx, conf)) - 1;\n+\t\t\taddress = HWPfQmgrAqEnableVf + vf_idx * ACC_BYTES_IN_WORD;\n+\t\t\tvalue += (qg_idx << 16);\n+\t\t\tacc_reg_write(d, address, value);\n+\t\t}\n+\t}\n+\n+\trte_bbdev_log_debug(\"PF Tip configuration complete for %s\", dev_name);\n+\treturn 0;\n+}\ndiff --git a/drivers/baseband/acc/version.map b/drivers/baseband/acc/version.map\nindex b4ff13e38f..27fbbe3de5 100644\n--- a/drivers/baseband/acc/version.map\n+++ b/drivers/baseband/acc/version.map\n@@ -6,4 +6,5 @@ EXPERIMENTAL {\n \tglobal:\n \n \trte_acc10x_configure;\n+\trte_acc200_configure;\n };\n",
    "prefixes": [
        "v9",
        "13/14"
    ]
}