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GET /api/patches/117657/?format=api
{ "id": 117657, "url": "http://patches.dpdk.org/api/patches/117657/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221007213851.31524-12-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221007213851.31524-12-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221007213851.31524-12-nicolas.chautru@intel.com", "date": "2022-10-07T21:38:48", "name": "[v9,11/14] baseband/acc: support interrupt", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "73d08e9ee6b2f42260923bb2e2b5973cce2cf4d6", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221007213851.31524-12-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 25041, "url": "http://patches.dpdk.org/api/series/25041/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25041", "date": "2022-10-07T21:38:37", "name": "bbdev ACC200 PMD", "version": 9, "mbox": "http://patches.dpdk.org/series/25041/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/117657/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/117657/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 99833A0543;\n\tFri, 7 Oct 2022 23:40:28 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8020C42BAC;\n\tFri, 7 Oct 2022 23:39:21 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 54A6642B6C\n for <dev@dpdk.org>; Fri, 7 Oct 2022 23:39:14 +0200 (CEST)", "from orsmga007.jf.intel.com ([10.7.209.58])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 07 Oct 2022 14:39:13 -0700", "from unknown (HELO icx-npg-scs1-cp1.localdomain) ([10.233.180.245])\n by orsmga007.jf.intel.com with ESMTP; 07 Oct 2022 14:39:13 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1665178754; x=1696714754;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=KmOG6NHAmIlRUGb4JqV4HiTlRNNSmwBloQgVNcTCUz8=;\n b=IA2w9nH0xqObGDGw+J65ED2JD4XtfBePqennL6dFowmzSe/z0PQC2M4t\n nnITOTFMY68UD1W76g04qgiZ6lsp9WxMjFjn3p0W4wKsAG9GlMainqGxu\n qVIm3Q53dw0hBuMveZf3BdH6U+4CRLgGf52Mqgd1WVUUKGe64sGspihVy\n n74Uzu6wMZ6M3CksmJ0I/viOsKBpRLdGOInRvYF4OvuvTjvI0ERY6Qvp9\n +rX55URFicUdiVYsaY3uIRmwh5+/3f2lG/02yAlPS+Cyb8CRf5bPesV06\n KwgCs042BZgryHmrFUEJ/8sYWV/PwZWT8fgHdFfqtdwazMxX/HlM5wKHV A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10493\"; a=\"291118515\"", "E=Sophos;i=\"5.95,167,1661842800\"; d=\"scan'208\";a=\"291118515\"", "E=McAfee;i=\"6500,9779,10493\"; a=\"620388478\"", "E=Sophos;i=\"5.95,167,1661842800\"; d=\"scan'208\";a=\"620388478\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tgakhil@marvell.com,\n\tmaxime.coquelin@redhat.com", "Cc": "trix@redhat.com, mdr@ashroe.eu, bruce.richardson@intel.com,\n hemant.agrawal@nxp.com, david.marchand@redhat.com,\n stephen@networkplumber.org, hernan.vargas@intel.com,\n Nic Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v9 11/14] baseband/acc: support interrupt", "Date": "Fri, 7 Oct 2022 14:38:48 -0700", "Message-Id": "<20221007213851.31524-12-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20221007213851.31524-1-nicolas.chautru@intel.com>", "References": "<20221007213851.31524-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Nic Chautru <nicolas.chautru@intel.com>\n\nAdded support for capability and functions for\nMSI/MSI-X interrupt and underlying information ring.\n\nSigned-off-by: Nic Chautru <nicolas.chautru@intel.com>\n---\n drivers/baseband/acc/rte_acc200_pmd.c | 302 +++++++++++++++++++++++++-\n 1 file changed, 299 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/baseband/acc/rte_acc200_pmd.c b/drivers/baseband/acc/rte_acc200_pmd.c\nindex 07fb41250c..99ac07ff01 100644\n--- a/drivers/baseband/acc/rte_acc200_pmd.c\n+++ b/drivers/baseband/acc/rte_acc200_pmd.c\n@@ -211,6 +211,149 @@ fetch_acc200_config(struct rte_bbdev *dev)\n \t\t\tacc_conf->q_fft.aq_depth_log2);\n }\n \n+/* Checks PF Info Ring to find the interrupt cause and handles it accordingly. */\n+static inline void\n+acc200_check_ir(struct acc_device *acc200_dev)\n+{\n+\tvolatile union acc_info_ring_data *ring_data;\n+\tuint16_t info_ring_head = acc200_dev->info_ring_head;\n+\tif (unlikely(acc200_dev->info_ring == NULL))\n+\t\treturn;\n+\n+\tring_data = acc200_dev->info_ring + (acc200_dev->info_ring_head & ACC_INFO_RING_MASK);\n+\n+\twhile (ring_data->valid) {\n+\t\tif ((ring_data->int_nb < ACC200_PF_INT_DMA_DL_DESC_IRQ) || (\n+\t\t\t\tring_data->int_nb > ACC200_PF_INT_DMA_DL5G_DESC_IRQ)) {\n+\t\t\trte_bbdev_log(WARNING, \"InfoRing: ITR:%d Info:0x%x\",\n+\t\t\t\tring_data->int_nb, ring_data->detailed_info);\n+\t\t\t/* Initialize Info Ring entry and move forward. */\n+\t\t\tring_data->val = 0;\n+\t\t}\n+\t\tinfo_ring_head++;\n+\t\tring_data = acc200_dev->info_ring + (info_ring_head & ACC_INFO_RING_MASK);\n+\t}\n+}\n+\n+/* Interrupt handler triggered by ACC200 dev for handling specific interrupt. */\n+static void\n+acc200_dev_interrupt_handler(void *cb_arg)\n+{\n+\tstruct rte_bbdev *dev = cb_arg;\n+\tstruct acc_device *acc200_dev = dev->data->dev_private;\n+\tvolatile union acc_info_ring_data *ring_data;\n+\tstruct acc_deq_intr_details deq_intr_det;\n+\n+\tring_data = acc200_dev->info_ring + (acc200_dev->info_ring_head & ACC_INFO_RING_MASK);\n+\n+\twhile (ring_data->valid) {\n+\t\tif (acc200_dev->pf_device) {\n+\t\t\trte_bbdev_log_debug(\n+\t\t\t\t\t\"ACC200 PF Interrupt received, Info Ring data: 0x%x -> %d\",\n+\t\t\t\t\tring_data->val, ring_data->int_nb);\n+\n+\t\t\tswitch (ring_data->int_nb) {\n+\t\t\tcase ACC200_PF_INT_DMA_DL_DESC_IRQ:\n+\t\t\tcase ACC200_PF_INT_DMA_UL_DESC_IRQ:\n+\t\t\tcase ACC200_PF_INT_DMA_FFT_DESC_IRQ:\n+\t\t\tcase ACC200_PF_INT_DMA_UL5G_DESC_IRQ:\n+\t\t\tcase ACC200_PF_INT_DMA_DL5G_DESC_IRQ:\n+\t\t\t\tdeq_intr_det.queue_id = get_queue_id_from_ring_info(\n+\t\t\t\t\t\tdev->data, *ring_data);\n+\t\t\t\tif (deq_intr_det.queue_id == UINT16_MAX) {\n+\t\t\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\t\t\"Couldn't find queue: aq_id: %u, qg_id: %u, vf_id: %u\",\n+\t\t\t\t\t\t\tring_data->aq_id,\n+\t\t\t\t\t\t\tring_data->qg_id,\n+\t\t\t\t\t\t\tring_data->vf_id);\n+\t\t\t\t\treturn;\n+\t\t\t\t}\n+\t\t\t\trte_bbdev_pmd_callback_process(dev,\n+\t\t\t\t\t\tRTE_BBDEV_EVENT_DEQUEUE, &deq_intr_det);\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\trte_bbdev_pmd_callback_process(dev, RTE_BBDEV_EVENT_ERROR, NULL);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t} else {\n+\t\t\trte_bbdev_log_debug(\n+\t\t\t\t\t\"ACC200 VF Interrupt received, Info Ring data: 0x%x\\n\",\n+\t\t\t\t\tring_data->val);\n+\t\t\tswitch (ring_data->int_nb) {\n+\t\t\tcase ACC200_VF_INT_DMA_DL_DESC_IRQ:\n+\t\t\tcase ACC200_VF_INT_DMA_UL_DESC_IRQ:\n+\t\t\tcase ACC200_VF_INT_DMA_FFT_DESC_IRQ:\n+\t\t\tcase ACC200_VF_INT_DMA_UL5G_DESC_IRQ:\n+\t\t\tcase ACC200_VF_INT_DMA_DL5G_DESC_IRQ:\n+\t\t\t\t/* VFs are not aware of their vf_id - it's set to 0. */\n+\t\t\t\tring_data->vf_id = 0;\n+\t\t\t\tdeq_intr_det.queue_id = get_queue_id_from_ring_info(\n+\t\t\t\t\t\tdev->data, *ring_data);\n+\t\t\t\tif (deq_intr_det.queue_id == UINT16_MAX) {\n+\t\t\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\t\t\"Couldn't find queue: aq_id: %u, qg_id: %u\",\n+\t\t\t\t\t\t\tring_data->aq_id,\n+\t\t\t\t\t\t\tring_data->qg_id);\n+\t\t\t\t\treturn;\n+\t\t\t\t}\n+\t\t\t\trte_bbdev_pmd_callback_process(dev,\n+\t\t\t\t\t\tRTE_BBDEV_EVENT_DEQUEUE, &deq_intr_det);\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\trte_bbdev_pmd_callback_process(dev, RTE_BBDEV_EVENT_ERROR, NULL);\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Initialize Info Ring entry and move forward. */\n+\t\tring_data->val = 0;\n+\t\t++acc200_dev->info_ring_head;\n+\t\tring_data = acc200_dev->info_ring +\n+\t\t\t\t(acc200_dev->info_ring_head & ACC_INFO_RING_MASK);\n+\t}\n+}\n+\n+/* Allocate and setup inforing. */\n+static int\n+allocate_info_ring(struct rte_bbdev *dev)\n+{\n+\tstruct acc_device *d = dev->data->dev_private;\n+\tconst struct acc200_registry_addr *reg_addr;\n+\trte_iova_t info_ring_iova;\n+\tuint32_t phys_low, phys_high;\n+\n+\tif (d->info_ring != NULL)\n+\t\treturn 0; /* Already configured. */\n+\n+\t/* Choose correct registry addresses for the device type. */\n+\tif (d->pf_device)\n+\t\treg_addr = &pf_reg_addr;\n+\telse\n+\t\treg_addr = &vf_reg_addr;\n+\t/* Allocate InfoRing */\n+\td->info_ring = rte_zmalloc_socket(\"Info Ring\", ACC_INFO_RING_NUM_ENTRIES *\n+\t\t\tsizeof(*d->info_ring), RTE_CACHE_LINE_SIZE, dev->data->socket_id);\n+\tif (d->info_ring == NULL) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\t\t\"Failed to allocate Info Ring for %s:%u\",\n+\t\t\t\tdev->device->driver->name,\n+\t\t\t\tdev->data->dev_id);\n+\t\treturn -ENOMEM;\n+\t}\n+\tinfo_ring_iova = rte_malloc_virt2iova(d->info_ring);\n+\n+\t/* Setup Info Ring. */\n+\tphys_high = (uint32_t)(info_ring_iova >> 32);\n+\tphys_low = (uint32_t)(info_ring_iova);\n+\tacc_reg_write(d, reg_addr->info_ring_hi, phys_high);\n+\tacc_reg_write(d, reg_addr->info_ring_lo, phys_low);\n+\tacc_reg_write(d, reg_addr->info_ring_en, ACC200_REG_IRQ_EN_ALL);\n+\td->info_ring_head = (acc_reg_read(d, reg_addr->info_ring_ptr) &\n+\t\t\t0xFFF) / sizeof(union acc_info_ring_data);\n+\treturn 0;\n+}\n+\n+\n /* Allocate 64MB memory used for all software rings. */\n static int\n acc200_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)\n@@ -319,6 +462,14 @@ acc200_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)\n \tacc_reg_write(d, reg_addr->tail_ptrs_fft_hi, phys_high);\n \tacc_reg_write(d, reg_addr->tail_ptrs_fft_lo, phys_low);\n \n+\tret = allocate_info_ring(dev);\n+\tif (ret < 0) {\n+\t\trte_bbdev_log(ERR, \"Failed to allocate info_ring for %s:%u\",\n+\t\t\t\tdev->device->driver->name,\n+\t\t\t\tdev->data->dev_id);\n+\t\t/* Continue */\n+\t}\n+\n \tif (d->harq_layout == NULL)\n \t\td->harq_layout = rte_zmalloc_socket(\"HARQ Layout\",\n \t\t\t\tACC_HARQ_LAYOUT * sizeof(*d->harq_layout),\n@@ -349,17 +500,120 @@ acc200_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)\n \treturn ret;\n }\n \n+static int\n+acc200_intr_enable(struct rte_bbdev *dev)\n+{\n+\tint ret;\n+\tstruct acc_device *d = dev->data->dev_private;\n+\t/*\n+\t * MSI/MSI-X are supported.\n+\t * Option controlled by vfio-intr through EAL parameter.\n+\t */\n+\tif (rte_intr_type_get(dev->intr_handle) == RTE_INTR_HANDLE_VFIO_MSI) {\n+\n+\t\tret = allocate_info_ring(dev);\n+\t\tif (ret < 0) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"Couldn't allocate info ring for device: %s\",\n+\t\t\t\t\tdev->data->name);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tret = rte_intr_enable(dev->intr_handle);\n+\t\tif (ret < 0) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"Couldn't enable interrupts for device: %s\",\n+\t\t\t\t\tdev->data->name);\n+\t\t\trte_free(d->info_ring);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tret = rte_intr_callback_register(dev->intr_handle,\n+\t\t\t\tacc200_dev_interrupt_handler, dev);\n+\t\tif (ret < 0) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"Couldn't register interrupt callback for device: %s\",\n+\t\t\t\t\tdev->data->name);\n+\t\t\trte_free(d->info_ring);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\treturn 0;\n+\t} else if (rte_intr_type_get(dev->intr_handle) == RTE_INTR_HANDLE_VFIO_MSIX) {\n+\t\tint i, max_queues;\n+\t\tstruct acc_device *acc200_dev = dev->data->dev_private;\n+\n+\t\tret = allocate_info_ring(dev);\n+\t\tif (ret < 0) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"Couldn't allocate info ring for device: %s\",\n+\t\t\t\t\tdev->data->name);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\tif (acc200_dev->pf_device)\n+\t\t\tmax_queues = ACC200_MAX_PF_MSIX;\n+\t\telse\n+\t\t\tmax_queues = ACC200_MAX_VF_MSIX;\n+\n+\t\tif (rte_intr_efd_enable(dev->intr_handle, max_queues)) {\n+\t\t\trte_bbdev_log(ERR, \"Failed to create fds for %u queues\",\n+\t\t\t\t\tdev->data->num_queues);\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tfor (i = 0; i < max_queues; ++i) {\n+\t\t\tif (rte_intr_efds_index_set(dev->intr_handle, i,\n+\t\t\t\t\trte_intr_fd_get(dev->intr_handle)))\n+\t\t\t\treturn -rte_errno;\n+\t\t}\n+\n+\t\tif (rte_intr_vec_list_alloc(dev->intr_handle, \"intr_vec\",\n+\t\t\t\tdev->data->num_queues)) {\n+\t\t\trte_bbdev_log(ERR, \"Failed to allocate %u vectors\",\n+\t\t\t\t\tdev->data->num_queues);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\n+\t\tret = rte_intr_enable(dev->intr_handle);\n+\n+\t\tif (ret < 0) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"Couldn't enable interrupts for device: %s\",\n+\t\t\t\t\tdev->data->name);\n+\t\t\trte_free(d->info_ring);\n+\t\t\treturn ret;\n+\t\t}\n+\t\tret = rte_intr_callback_register(dev->intr_handle,\n+\t\t\t\tacc200_dev_interrupt_handler, dev);\n+\t\tif (ret < 0) {\n+\t\t\trte_bbdev_log(ERR,\n+\t\t\t\t\t\"Couldn't register interrupt callback for device: %s\",\n+\t\t\t\t\tdev->data->name);\n+\t\t\trte_free(d->info_ring);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\treturn 0;\n+\t}\n+\n+\trte_bbdev_log(ERR, \"ACC200 (%s) supports only VFIO MSI/MSI-X interrupts\\n\",\n+\t\t\tdev->data->name);\n+\treturn -ENOTSUP;\n+}\n+\n /* Free memory used for software rings. */\n static int\n acc200_dev_close(struct rte_bbdev *dev)\n {\n \tstruct acc_device *d = dev->data->dev_private;\n+\tacc200_check_ir(d);\n \tif (d->sw_rings_base != NULL) {\n \t\trte_free(d->tail_ptrs);\n+\t\trte_free(d->info_ring);\n \t\trte_free(d->sw_rings_base);\n \t\trte_free(d->harq_layout);\n-\t\td->sw_rings_base = NULL;\n \t\td->tail_ptrs = NULL;\n+\t\td->info_ring = NULL;\n+\t\td->sw_rings_base = NULL;\n \t\td->harq_layout = NULL;\n \t}\n \t/* Ensure all in flight HW transactions are completed. */\n@@ -661,6 +915,7 @@ acc200_dev_info_get(struct rte_bbdev *dev,\n \t\t\t\t\tRTE_BBDEV_TURBO_CONTINUE_CRC_MATCH |\n \t\t\t\t\tRTE_BBDEV_TURBO_SOFT_OUTPUT |\n \t\t\t\t\tRTE_BBDEV_TURBO_EARLY_TERMINATION |\n+\t\t\t\t\tRTE_BBDEV_TURBO_DEC_INTERRUPTS |\n \t\t\t\t\tRTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN |\n \t\t\t\t\tRTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT |\n \t\t\t\t\tRTE_BBDEV_TURBO_MAP_DEC |\n@@ -682,6 +937,7 @@ acc200_dev_info_get(struct rte_bbdev *dev,\n \t\t\t\t\tRTE_BBDEV_TURBO_CRC_24B_ATTACH |\n \t\t\t\t\tRTE_BBDEV_TURBO_RV_INDEX_BYPASS |\n \t\t\t\t\tRTE_BBDEV_TURBO_RATE_MATCH |\n+\t\t\t\t\tRTE_BBDEV_TURBO_ENC_INTERRUPTS |\n \t\t\t\t\tRTE_BBDEV_TURBO_ENC_SCATTER_GATHER,\n \t\t\t\t.num_buffers_src =\n \t\t\t\t\t\tRTE_BBDEV_TURBO_MAX_CODE_BLOCKS,\n@@ -695,7 +951,8 @@ acc200_dev_info_get(struct rte_bbdev *dev,\n \t\t\t\t.capability_flags =\n \t\t\t\t\tRTE_BBDEV_LDPC_RATE_MATCH |\n \t\t\t\t\tRTE_BBDEV_LDPC_CRC_24B_ATTACH |\n-\t\t\t\t\tRTE_BBDEV_LDPC_INTERLEAVER_BYPASS,\n+\t\t\t\t\tRTE_BBDEV_LDPC_INTERLEAVER_BYPASS |\n+\t\t\t\t\tRTE_BBDEV_LDPC_ENC_INTERRUPTS,\n \t\t\t\t.num_buffers_src =\n \t\t\t\t\t\tRTE_BBDEV_LDPC_MAX_CODE_BLOCKS,\n \t\t\t\t.num_buffers_dst =\n@@ -716,7 +973,8 @@ acc200_dev_info_get(struct rte_bbdev *dev,\n \t\t\t\tRTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS |\n \t\t\t\tRTE_BBDEV_LDPC_DEC_SCATTER_GATHER |\n \t\t\t\tRTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION |\n-\t\t\t\tRTE_BBDEV_LDPC_LLR_COMPRESSION,\n+\t\t\t\tRTE_BBDEV_LDPC_LLR_COMPRESSION |\n+\t\t\t\tRTE_BBDEV_LDPC_DEC_INTERRUPTS,\n \t\t\t.llr_size = 8,\n \t\t\t.llr_decimals = 1,\n \t\t\t.num_buffers_src =\n@@ -784,15 +1042,46 @@ acc200_dev_info_get(struct rte_bbdev *dev,\n \tdev_info->min_alignment = 1;\n \tdev_info->capabilities = bbdev_capabilities;\n \tdev_info->harq_buffer_size = 0;\n+\n+\tacc200_check_ir(d);\n+}\n+\n+static int\n+acc200_queue_intr_enable(struct rte_bbdev *dev, uint16_t queue_id)\n+{\n+\tstruct acc_queue *q = dev->data->queues[queue_id].queue_private;\n+\n+\tif (rte_intr_type_get(dev->intr_handle) != RTE_INTR_HANDLE_VFIO_MSI &&\n+\t\t\trte_intr_type_get(dev->intr_handle) != RTE_INTR_HANDLE_VFIO_MSIX)\n+\t\treturn -ENOTSUP;\n+\n+\tq->irq_enable = 1;\n+\treturn 0;\n+}\n+\n+static int\n+acc200_queue_intr_disable(struct rte_bbdev *dev, uint16_t queue_id)\n+{\n+\tstruct acc_queue *q = dev->data->queues[queue_id].queue_private;\n+\n+\tif (rte_intr_type_get(dev->intr_handle) != RTE_INTR_HANDLE_VFIO_MSI &&\n+\t\t\trte_intr_type_get(dev->intr_handle) != RTE_INTR_HANDLE_VFIO_MSIX)\n+\t\treturn -ENOTSUP;\n+\n+\tq->irq_enable = 0;\n+\treturn 0;\n }\n \n static const struct rte_bbdev_ops acc200_bbdev_ops = {\n \t.setup_queues = acc200_setup_queues,\n+\t.intr_enable = acc200_intr_enable,\n \t.close = acc200_dev_close,\n \t.info_get = acc200_dev_info_get,\n \t.queue_setup = acc200_queue_setup,\n \t.queue_release = acc200_queue_release,\n \t.queue_stop = acc_queue_stop,\n+\t.queue_intr_enable = acc200_queue_intr_enable,\n+\t.queue_intr_disable = acc200_queue_intr_disable\n };\n \n /* ACC200 PCI PF address map. */\n@@ -2514,6 +2803,7 @@ dequeue_dec_one_op_cb(struct rte_bbdev_queue_data *q_data,\n \tif (op->status != 0) {\n \t\t/* These errors are not expected. */\n \t\tq_data->queue_stats.dequeue_err_count++;\n+\t\tacc200_check_ir(q->d);\n \t}\n \n \t/* CRC invalid if error exists. */\n@@ -2578,6 +2868,9 @@ dequeue_ldpc_dec_one_op_cb(struct rte_bbdev_queue_data *q_data,\n \n \top->ldpc_dec.iter_count = (uint8_t) rsp.iter_cnt;\n \n+\tif (op->status & (1 << RTE_BBDEV_DRV_ERROR))\n+\t\tacc200_check_ir(q->d);\n+\n \t/* Check if this is the last desc in batch (Atomic Queue). */\n \tif (desc->req.last_desc_in_batch) {\n \t\t(*aq_dequeued)++;\n@@ -3017,6 +3310,9 @@ dequeue_fft_one_op(struct rte_bbdev_queue_data *q_data,\n \tif (op->status != 0)\n \t\tq_data->queue_stats.dequeue_err_count++;\n \n+\tif (op->status & (1 << RTE_BBDEV_DRV_ERROR))\n+\t\tacc200_check_ir(q->d);\n+\n \t/* Check if this is the last desc in batch (Atomic Queue). */\n \tif (desc->req.last_desc_in_batch) {\n \t\t(*aq_dequeued)++;\n", "prefixes": [ "v9", "11/14" ] }