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GET /api/patches/117481/?format=api
{ "id": 117481, "url": "http://patches.dpdk.org/api/patches/117481/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20221006150325.660-20-valex@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20221006150325.660-20-valex@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20221006150325.660-20-valex@nvidia.com", "date": "2022-10-06T15:03:25", "name": "[v2,19/19] net/mlx5/hws: Enable HWS", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9d154977bfc9fc8d3875b9a613df1644944e8fb1", "submitter": { "id": 2858, "url": "http://patches.dpdk.org/api/people/2858/?format=api", "name": "Alex Vesker", "email": "valex@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20221006150325.660-20-valex@nvidia.com/mbox/", "series": [ { "id": 25012, "url": "http://patches.dpdk.org/api/series/25012/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=25012", "date": "2022-10-06T15:03:06", "name": "net/mlx5: Add HW steering low level support", "version": 2, "mbox": "http://patches.dpdk.org/series/25012/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/117481/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/117481/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", 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"[v2 19/19] net/mlx5/hws: Enable HWS", "Date": "Thu, 6 Oct 2022 18:03:25 +0300", "Message-ID": "<20221006150325.660-20-valex@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20221006150325.660-1-valex@nvidia.com>", "References": "<20220922190345.394-1-valex@nvidia.com>\n <20221006150325.660-1-valex@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BN8NAM11FT114:EE_|SJ1PR12MB6292:EE_", "X-MS-Office365-Filtering-Correlation-Id": "7912f769-4bd4-4e29-0105-08daa7ac2115", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 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SFS:(13230022)(4636009)(346002)(376002)(136003)(39860400002)(396003)(451199015)(40470700004)(36840700001)(46966006)(30864003)(47076005)(186003)(426003)(16526019)(41300700001)(83380400001)(82740400003)(40480700001)(26005)(356005)(110136005)(2906002)(6636002)(54906003)(4326008)(70206006)(8676002)(55016003)(316002)(7636003)(478600001)(6286002)(36756003)(70586007)(2616005)(1076003)(82310400005)(6666004)(7696005)(40460700003)(8936002)(5660300002)(86362001)(336012)(107886003)(36860700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Oct 2022 15:04:55.5241 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 7912f769-4bd4-4e29-0105-08daa7ac2115", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT114.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SJ1PR12MB6292", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Replace stub implenation of HWS with mlx5dr code.\n\nSigned-off-by: Alex Vesker <valex@nvidia.com>\n---\n drivers/net/mlx5/hws/meson.build | 18 +\n drivers/net/mlx5/hws/mlx5dr.h | 594 +++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_internal.h | 93 ++++\n drivers/net/mlx5/meson.build | 1 +\n drivers/net/mlx5/mlx5.h | 1 +\n drivers/net/mlx5/mlx5_flow.h | 2 +\n drivers/net/mlx5/mlx5_flow_hw.c | 4 +-\n 7 files changed, 711 insertions(+), 2 deletions(-)\n create mode 100644 drivers/net/mlx5/hws/meson.build\n create mode 100644 drivers/net/mlx5/hws/mlx5dr.h\n create mode 100644 drivers/net/mlx5/hws/mlx5dr_internal.h", "diff": "diff --git a/drivers/net/mlx5/hws/meson.build b/drivers/net/mlx5/hws/meson.build\nnew file mode 100644\nindex 0000000000..f94798dd2d\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/meson.build\n@@ -0,0 +1,18 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+\n+includes += include_directories('.')\n+sources += files(\n+\t'mlx5dr_context.c',\n+\t'mlx5dr_table.c',\n+\t'mlx5dr_matcher.c',\n+\t'mlx5dr_rule.c',\n+\t'mlx5dr_action.c',\n+\t'mlx5dr_buddy.c',\n+\t'mlx5dr_pool.c',\n+\t'mlx5dr_cmd.c',\n+\t'mlx5dr_send.c',\n+\t'mlx5dr_definer.c',\n+\t'mlx5dr_debug.c',\n+\t'mlx5dr_pat_arg.c',\n+)\ndiff --git a/drivers/net/mlx5/hws/mlx5dr.h b/drivers/net/mlx5/hws/mlx5dr.h\nnew file mode 100644\nindex 0000000000..980bda0d63\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr.h\n@@ -0,0 +1,594 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#ifndef MLX5DR_H_\n+#define MLX5DR_H_\n+\n+#include <rte_flow.h>\n+\n+struct mlx5dr_context;\n+struct mlx5dr_table;\n+struct mlx5dr_matcher;\n+struct mlx5dr_rule;\n+\n+enum mlx5dr_table_type {\n+\tMLX5DR_TABLE_TYPE_NIC_RX,\n+\tMLX5DR_TABLE_TYPE_NIC_TX,\n+\tMLX5DR_TABLE_TYPE_FDB,\n+\tMLX5DR_TABLE_TYPE_MAX,\n+};\n+\n+enum mlx5dr_matcher_resource_mode {\n+\t/* Allocate resources based on number of rules with minimal failure probability */\n+\tMLX5DR_MATCHER_RESOURCE_MODE_RULE,\n+\t/* Allocate fixed size hash table based on given column and rows */\n+\tMLX5DR_MATCHER_RESOURCE_MODE_HTABLE,\n+};\n+\n+enum mlx5dr_action_type {\n+\tMLX5DR_ACTION_TYP_LAST,\n+\tMLX5DR_ACTION_TYP_TNL_L2_TO_L2,\n+\tMLX5DR_ACTION_TYP_L2_TO_TNL_L2,\n+\tMLX5DR_ACTION_TYP_TNL_L3_TO_L2,\n+\tMLX5DR_ACTION_TYP_L2_TO_TNL_L3,\n+\tMLX5DR_ACTION_TYP_DROP,\n+\tMLX5DR_ACTION_TYP_TIR,\n+\tMLX5DR_ACTION_TYP_FT,\n+\tMLX5DR_ACTION_TYP_CTR,\n+\tMLX5DR_ACTION_TYP_TAG,\n+\tMLX5DR_ACTION_TYP_MODIFY_HDR,\n+\tMLX5DR_ACTION_TYP_VPORT,\n+\tMLX5DR_ACTION_TYP_MISS,\n+\tMLX5DR_ACTION_TYP_POP_VLAN,\n+\tMLX5DR_ACTION_TYP_PUSH_VLAN,\n+\tMLX5DR_ACTION_TYP_ASO_METER,\n+\tMLX5DR_ACTION_TYP_ASO_CT,\n+\tMLX5DR_ACTION_TYP_MAX,\n+};\n+\n+enum mlx5dr_action_flags {\n+\tMLX5DR_ACTION_FLAG_ROOT_RX = 1 << 0,\n+\tMLX5DR_ACTION_FLAG_ROOT_TX = 1 << 1,\n+\tMLX5DR_ACTION_FLAG_ROOT_FDB = 1 << 2,\n+\tMLX5DR_ACTION_FLAG_HWS_RX = 1 << 3,\n+\tMLX5DR_ACTION_FLAG_HWS_TX = 1 << 4,\n+\tMLX5DR_ACTION_FLAG_HWS_FDB = 1 << 5,\n+\t/* Shared action can be used over a few threads, since data is written\n+\t * only once at the creation of the action.\n+\t */\n+\tMLX5DR_ACTION_FLAG_SHARED = 1 << 6,\n+};\n+\n+enum mlx5dr_action_reformat_type {\n+\tMLX5DR_ACTION_REFORMAT_TYPE_TNL_L2_TO_L2,\n+\tMLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L2,\n+\tMLX5DR_ACTION_REFORMAT_TYPE_TNL_L3_TO_L2,\n+\tMLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L3,\n+};\n+\n+enum mlx5dr_action_aso_meter_color {\n+\tMLX5DR_ACTION_ASO_METER_COLOR_RED = 0x0,\n+\tMLX5DR_ACTION_ASO_METER_COLOR_YELLOW = 0x1,\n+\tMLX5DR_ACTION_ASO_METER_COLOR_GREEN = 0x2,\n+\tMLX5DR_ACTION_ASO_METER_COLOR_UNDEFINED = 0x3,\n+};\n+\n+enum mlx5dr_action_aso_ct_flags {\n+\tMLX5DR_ACTION_ASO_CT_DIRECTION_INITIATOR = 0 << 0,\n+\tMLX5DR_ACTION_ASO_CT_DIRECTION_RESPONDER = 1 << 0,\n+};\n+\n+enum mlx5dr_match_template_flags {\n+\t/* Allow relaxed matching by skipping derived dependent match fields. */\n+\tMLX5DR_MATCH_TEMPLATE_FLAG_RELAXED_MATCH = 1,\n+};\n+\n+enum mlx5dr_send_queue_actions {\n+\t/* Start executing all pending queued rules and write to HW */\n+\tMLX5DR_SEND_QUEUE_ACTION_DRAIN = 1 << 0,\n+};\n+\n+struct mlx5dr_context_attr {\n+\tuint16_t queues;\n+\tuint16_t queue_size;\n+\tsize_t initial_log_ste_memory; /* Currently not in use */\n+\t/* Optional PD used for allocating res ources */\n+\tstruct ibv_pd *pd;\n+};\n+\n+struct mlx5dr_table_attr {\n+\tenum mlx5dr_table_type type;\n+\tuint32_t level;\n+};\n+\n+enum mlx5dr_matcher_flow_src {\n+\tMLX5DR_MATCHER_FLOW_SRC_ANY = 0x0,\n+\tMLX5DR_MATCHER_FLOW_SRC_WIRE = 0x1,\n+\tMLX5DR_MATCHER_FLOW_SRC_VPORT = 0x2,\n+};\n+\n+struct mlx5dr_matcher_attr {\n+\t/* Processing priority inside table */\n+\tuint32_t priority;\n+\t/* Provide all rules with unique rule_idx in num_log range to reduce locking */\n+\tbool optimize_using_rule_idx;\n+\t/* Resource mode and corresponding size */\n+\tenum mlx5dr_matcher_resource_mode mode;\n+\t/* Optimize insertion in case packet origin is the same for all rules */\n+\tenum mlx5dr_matcher_flow_src optimize_flow_src;\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint8_t sz_row_log;\n+\t\t\tuint8_t sz_col_log;\n+\t\t} table;\n+\n+\t\tstruct {\n+\t\t\tuint8_t num_log;\n+\t\t} rule;\n+\t};\n+};\n+\n+struct mlx5dr_rule_attr {\n+\tuint16_t queue_id;\n+\tvoid *user_data;\n+\t/* Valid if matcher optimize_using_rule_idx is set */\n+\tuint32_t rule_idx;\n+\tuint32_t burst:1;\n+};\n+\n+struct mlx5dr_devx_obj {\n+\tstruct mlx5dv_devx_obj *obj;\n+\tuint32_t id;\n+};\n+\n+/* In actions that take offset, the offset is unique, and the user should not\n+ * reuse the same index because data changing is not atomic.\n+ */\n+struct mlx5dr_rule_action {\n+\tstruct mlx5dr_action *action;\n+\tunion {\n+\t\tstruct {\n+\t\t\tuint32_t value;\n+\t\t} tag;\n+\n+\t\tstruct {\n+\t\t\tuint32_t offset;\n+\t\t} counter;\n+\n+\t\tstruct {\n+\t\t\tuint32_t offset;\n+\t\t\tuint8_t *data;\n+\t\t} modify_header;\n+\n+\t\tstruct {\n+\t\t\tuint32_t offset;\n+\t\t\tuint8_t *data;\n+\t\t} reformat;\n+\n+\t\tstruct {\n+\t\t\t__be32 vlan_hdr;\n+\t\t} push_vlan;\n+\n+\t\tstruct {\n+\t\t\tuint32_t offset;\n+\t\t\tenum mlx5dr_action_aso_meter_color init_color;\n+\t\t} aso_meter;\n+\n+\t\tstruct {\n+\t\t\tuint32_t offset;\n+\t\t\tenum mlx5dr_action_aso_ct_flags direction;\n+\t\t} aso_ct;\n+\t};\n+};\n+\n+/* Open a context used for direct rule insertion using hardware steering.\n+ * Each context can contain multiple tables of different types.\n+ *\n+ * @param[in] ibv_ctx\n+ *\tThe ibv context to used for HWS.\n+ * @param[in] attr\n+ *\tAttributes used for context open.\n+ * @return pointer to mlx5dr_context on success NULL otherwise.\n+ */\n+struct mlx5dr_context *\n+mlx5dr_context_open(struct ibv_context *ibv_ctx,\n+\t\t struct mlx5dr_context_attr *attr);\n+\n+/* Close a context used for direct hardware steering.\n+ *\n+ * @param[in] ctx\n+ *\tmlx5dr context to close.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_context_close(struct mlx5dr_context *ctx);\n+\n+/* Create a new direct rule table. Each table can contain multiple matchers.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new table will be opened.\n+ * @param[in] attr\n+ *\tAttributes used for table creation.\n+ * @return pointer to mlx5dr_table on success NULL otherwise.\n+ */\n+struct mlx5dr_table *\n+mlx5dr_table_create(struct mlx5dr_context *ctx,\n+\t\t struct mlx5dr_table_attr *attr);\n+\n+/* Destroy direct rule table.\n+ *\n+ * @param[in] tbl\n+ *\tmlx5dr table to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_table_destroy(struct mlx5dr_table *tbl);\n+\n+/* Create new match template based on items mask, the match template\n+ * will be used for matcher creation.\n+ *\n+ * @param[in] items\n+ *\tDescribe the mask for template creation\n+ * @param[in] flags\n+ *\tTemplate creation flags\n+ * @return pointer to mlx5dr_match_template on success NULL otherwise\n+ */\n+struct mlx5dr_match_template *\n+mlx5dr_match_template_create(const struct rte_flow_item items[],\n+\t\t\t enum mlx5dr_match_template_flags flags);\n+\n+/* Destroy match template.\n+ *\n+ * @param[in] mt\n+ *\tMatch template to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_match_template_destroy(struct mlx5dr_match_template *mt);\n+\n+/* Create new action template based on action_type array, the action template\n+ * will be used for matcher creation.\n+ *\n+ * @param[in] action_type\n+ *\tAn array of actions based on the order of actions which will be provided\n+ *\twith rule_actions to mlx5dr_rule_create. The last action is marked\n+ *\tusing MLX5DR_ACTION_TYP_LAST.\n+ * @return pointer to mlx5dr_action_template on success NULL otherwise\n+ */\n+struct mlx5dr_action_template *\n+mlx5dr_action_template_create(const enum mlx5dr_action_type action_type[]);\n+\n+/* Destroy action template.\n+ *\n+ * @param[in] at\n+ *\tAction template to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_action_template_destroy(struct mlx5dr_action_template *at);\n+\n+/* Create a new direct rule matcher. Each matcher can contain multiple rules.\n+ * Matchers on the table will be processed by priority. Matching fields and\n+ * mask are described by the match template. In some cases multiple match\n+ * templates can be used on the same matcher.\n+ *\n+ * @param[in] table\n+ *\tThe table in which the new matcher will be opened.\n+ * @param[in] mt\n+ *\tArray of match templates to be used on matcher.\n+ * @param[in] num_of_mt\n+ *\tNumber of match templates in mt array.\n+ * @param[in] at\n+ *\tArray of action templates to be used on matcher.\n+ * @param[in] num_of_at\n+ *\tNumber of action templates in mt array.\n+ * @param[in] attr\n+ *\tAttributes used for matcher creation.\n+ * @return pointer to mlx5dr_matcher on success NULL otherwise.\n+ */\n+struct mlx5dr_matcher *\n+mlx5dr_matcher_create(struct mlx5dr_table *table,\n+\t\t struct mlx5dr_match_template *mt[],\n+\t\t uint8_t num_of_mt,\n+\t\t struct mlx5dr_action_template *at[],\n+\t\t uint8_t num_of_at,\n+\t\t struct mlx5dr_matcher_attr *attr);\n+\n+/* Destroy direct rule matcher.\n+ *\n+ * @param[in] matcher\n+ *\tMatcher to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_matcher_destroy(struct mlx5dr_matcher *matcher);\n+\n+/* Get the size of the rule handle (mlx5dr_rule) to be used on rule creation.\n+ *\n+ * @return size in bytes of rule handle struct.\n+ */\n+size_t mlx5dr_rule_get_handle_size(void);\n+\n+/* Enqueue create rule operation.\n+ *\n+ * @param[in] matcher\n+ *\tThe matcher in which the new rule will be created.\n+ * @param[in] mt_idx\n+ *\tMatch template index to create the match with.\n+ * @param[in] items\n+ *\tThe items used for the value matching.\n+ * @param[in] rule_actions\n+ *\tRule action to be executed on match.\n+ * @param[in] at_idx\n+ *\tAction template index to apply the actions with.\n+ * @param[in] num_of_actions\n+ *\tNumber of rule actions.\n+ * @param[in] attr\n+ *\tRule creation attributes.\n+ * @param[in, out] rule_handle\n+ *\tA valid rule handle. The handle doesn't require any initialization.\n+ * @return zero on successful enqueue non zero otherwise.\n+ */\n+int mlx5dr_rule_create(struct mlx5dr_matcher *matcher,\n+\t\t uint8_t mt_idx,\n+\t\t const struct rte_flow_item items[],\n+\t\t uint8_t at_idx,\n+\t\t struct mlx5dr_rule_action rule_actions[],\n+\t\t struct mlx5dr_rule_attr *attr,\n+\t\t struct mlx5dr_rule *rule_handle);\n+\n+/* Enqueue destroy rule operation.\n+ *\n+ * @param[in] rule\n+ *\tThe rule destruction to enqueue.\n+ * @param[in] attr\n+ *\tRule destruction attributes.\n+ * @return zero on successful enqueue non zero otherwise.\n+ */\n+int mlx5dr_rule_destroy(struct mlx5dr_rule *rule,\n+\t\t\tstruct mlx5dr_rule_attr *attr);\n+\n+/* Create direct rule drop action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_dest_drop(struct mlx5dr_context *ctx,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule default miss action.\n+ * Defaults are RX: Drop TX: Wire.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_default_miss(struct mlx5dr_context *ctx,\n+\t\t\t\t uint32_t flags);\n+\n+/* Create direct rule goto table action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] tbl\n+ *\tDestination table.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_dest_table(struct mlx5dr_context *ctx,\n+\t\t\t\tstruct mlx5dr_table *tbl,\n+\t\t\t\tuint32_t flags);\n+\n+/* Create direct rule goto vport action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] ib_port_num\n+ *\tDestination ib_port number.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_dest_vport(struct mlx5dr_context *ctx,\n+\t\t\t\tuint32_t ib_port_num,\n+\t\t\t\tuint32_t flags);\n+\n+/* Create direct rule goto TIR action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] obj\n+ *\tDirect rule TIR devx object.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_dest_tir(struct mlx5dr_context *ctx,\n+\t\t\t struct mlx5dr_devx_obj *obj,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule TAG action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_tag(struct mlx5dr_context *ctx,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule counter action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] obj\n+ *\tDirect rule counter devx object.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_counter(struct mlx5dr_context *ctx,\n+\t\t\t struct mlx5dr_devx_obj *obj,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule reformat action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] reformat_type\n+ *\tType of reformat.\n+ * @param[in] data_sz\n+ *\tSize in bytes of data.\n+ * @param[in] inline_data\n+ *\tHeader data array in case of inline action.\n+ * @param[in] log_bulk_size\n+ *\tNumber of unique values used with this pattern.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_reformat(struct mlx5dr_context *ctx,\n+\t\t\t enum mlx5dr_action_reformat_type reformat_type,\n+\t\t\t size_t data_sz,\n+\t\t\t void *inline_data,\n+\t\t\t uint32_t log_bulk_size,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule modify header action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] pattern_sz\n+ *\tByte size of the pattern array.\n+ * @param[in] pattern\n+ *\tPRM format modify pattern action array.\n+ * @param[in] log_bulk_size\n+ *\tNumber of unique values used with this pattern.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_modify_header(struct mlx5dr_context *ctx,\n+\t\t\t\t size_t pattern_sz,\n+\t\t\t\t __be64 pattern[],\n+\t\t\t\t uint32_t log_bulk_size,\n+\t\t\t\t uint32_t flags);\n+\n+/* Create direct rule ASO flow meter action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] devx_obj\n+ *\tThe DEVX ASO object.\n+ * @param[in] return_reg_c\n+ *\tCopy the ASO object value into this reg_c, after a packet hits a rule with this ASO object.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_aso_meter(struct mlx5dr_context *ctx,\n+\t\t\t struct mlx5dr_devx_obj *devx_obj,\n+\t\t\t uint8_t return_reg_c,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule ASO CT action.\n+ *\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] devx_obj\n+ *\tThe DEVX ASO object.\n+ * @param[in] return_reg_id\n+ * \tCopy the ASO object value into this reg_id, after a packet hits a rule with this ASO object.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_aso_ct(struct mlx5dr_context *ctx,\n+\t\t\t struct mlx5dr_devx_obj *devx_obj,\n+\t\t\t uint8_t return_reg_id,\n+\t\t\t uint32_t flags);\n+\n+/* Create direct rule pop vlan action.\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_pop_vlan(struct mlx5dr_context *ctx, uint32_t flags);\n+\n+/* Create direct rule push vlan action.\n+ * @param[in] ctx\n+ *\tThe context in which the new action will be created.\n+ * @param[in] flags\n+ *\tAction creation flags. (enum mlx5dr_action_flags)\n+ * @return pointer to mlx5dr_action on success NULL otherwise.\n+ */\n+struct mlx5dr_action *\n+mlx5dr_action_create_push_vlan(struct mlx5dr_context *ctx, uint32_t flags);\n+\n+/* Destroy direct rule action.\n+ *\n+ * @param[in] action\n+ *\tThe action to destroy.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_action_destroy(struct mlx5dr_action *action);\n+\n+/* Poll queue for rule creation and deletions completions.\n+ *\n+ * @param[in] ctx\n+ *\tThe context to which the queue belong to.\n+ * @param[in] queue_id\n+ *\tThe id of the queue to poll.\n+ * @param[in, out] res\n+ *\tCompletion array.\n+ * @param[in] res_nb\n+ *\tMaximum number of results to return.\n+ * @return negative number on failure, the number of completions otherwise.\n+ */\n+int mlx5dr_send_queue_poll(struct mlx5dr_context *ctx,\n+\t\t\t uint16_t queue_id,\n+\t\t\t struct rte_flow_op_result res[],\n+\t\t\t uint32_t res_nb);\n+\n+/* Perform an action on the queue\n+ *\n+ * @param[in] ctx\n+ * \tThe context to which the queue belong to.\n+ * @param[in] queue_id\n+ * \tThe id of the queue to perform the action on.\n+ * @param[in] actions\n+ * \tActions to perform on the queue. (enum mlx5dr_send_queue_actions)\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_send_queue_action(struct mlx5dr_context *ctx,\n+\t\t\t uint16_t queue_id,\n+\t\t\t uint32_t actions);\n+\n+/* Dump HWS info\n+ *\n+ * @param[in] ctx\n+ *\tThe context which to dump the info from.\n+ * @param[in] f\n+ * \tThe file to write the dump to.\n+ * @return zero on success non zero otherwise.\n+ */\n+int mlx5dr_debug_dump(struct mlx5dr_context *ctx, FILE *f);\n+\n+#endif\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_internal.h b/drivers/net/mlx5/hws/mlx5dr_internal.h\nnew file mode 100644\nindex 0000000000..dbd77b9c66\n--- /dev/null\n+++ b/drivers/net/mlx5/hws/mlx5dr_internal.h\n@@ -0,0 +1,93 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2022 NVIDIA Corporation & Affiliates\n+ */\n+\n+#ifndef MLX5DR_INTERNAL_H_\n+#define MLX5DR_INTERNAL_H_\n+\n+#include <stdint.h>\n+#include <sys/queue.h>\n+/* Verbs headers do not support -pedantic. */\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-Wpedantic\"\n+#endif\n+#include <infiniband/verbs.h>\n+#include <infiniband/mlx5dv.h>\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic error \"-Wpedantic\"\n+#endif\n+#include <rte_flow.h>\n+#include <rte_gtp.h>\n+\n+#include \"mlx5_prm.h\"\n+#include \"mlx5_glue.h\"\n+#include \"mlx5_flow.h\"\n+#include \"mlx5_utils.h\"\n+#include \"mlx5_malloc.h\"\n+\n+#include \"mlx5dr.h\"\n+#include \"mlx5dr_pool.h\"\n+#include \"mlx5dr_context.h\"\n+#include \"mlx5dr_table.h\"\n+#include \"mlx5dr_matcher.h\"\n+#include \"mlx5dr_send.h\"\n+#include \"mlx5dr_rule.h\"\n+#include \"mlx5dr_cmd.h\"\n+#include \"mlx5dr_action.h\"\n+#include \"mlx5dr_definer.h\"\n+#include \"mlx5dr_debug.h\"\n+#include \"mlx5dr_pat_arg.h\"\n+\n+#define DW_SIZE\t\t4\n+#define BITS_IN_BYTE\t8\n+#define BITS_IN_DW\t(BITS_IN_BYTE * DW_SIZE)\n+\n+#define BIT(_bit) (1ULL << (_bit))\n+#define IS_BIT_SET(_value, _bit) (_value & (1ULL << (_bit)))\n+\n+#ifndef ARRAY_SIZE\n+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))\n+#endif\n+\n+#ifdef RTE_LIBRTE_MLX5_DEBUG\n+/* Prevent double function name print when debug is set */\n+#define DR_LOG DRV_LOG\n+#else\n+/* Print function name as part of the log */\n+#define DR_LOG(level, ...) \\\n+\tDRV_LOG(level, RTE_FMT(\"[%s]: \" RTE_FMT_HEAD(__VA_ARGS__,), __func__, RTE_FMT_TAIL(__VA_ARGS__,)))\n+#endif\n+\n+static inline void *simple_malloc(size_t size)\n+{\n+\treturn mlx5_malloc(MLX5_MEM_SYS,\n+\t\t\t size,\n+\t\t\t MLX5_MALLOC_ALIGNMENT,\n+\t\t\t SOCKET_ID_ANY);\n+}\n+\n+static inline void *simple_calloc(size_t nmemb, size_t size)\n+{\n+\treturn mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO,\n+\t\t\t nmemb * size,\n+\t\t\t MLX5_MALLOC_ALIGNMENT,\n+\t\t\t SOCKET_ID_ANY);\n+}\n+\n+static inline void simple_free(void *addr)\n+{\n+\tmlx5_free(addr);\n+}\n+\n+static inline bool is_mem_zero(const uint8_t *mem, size_t size)\n+{\n+\tassert(size);\n+\treturn (*mem == 0) && memcmp(mem, mem + 1, size - 1) == 0;\n+}\n+\n+static inline uint64_t roundup_pow_of_two(uint64_t n)\n+{\n+\treturn n == 1 ? 1 : 1ULL << log2above(n);\n+}\n+\n+#endif /* MLX5DR_INTERNAL_H_ */\ndiff --git a/drivers/net/mlx5/meson.build b/drivers/net/mlx5/meson.build\nindex c7ddd4b65c..f9b266c900 100644\n--- a/drivers/net/mlx5/meson.build\n+++ b/drivers/net/mlx5/meson.build\n@@ -71,3 +71,4 @@ endif\n testpmd_sources += files('mlx5_testpmd.c')\n \n subdir(exec_env)\n+subdir('hws')\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 29657ab273..77309e32a0 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -34,6 +34,7 @@\n #include \"mlx5_os.h\"\n #include \"mlx5_autoconf.h\"\n #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)\n+#include \"hws/mlx5dr.h\"\n #endif\n \n #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh)\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex cae1a64def..1ad75fc8c6 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -17,6 +17,8 @@\n #include <mlx5_prm.h>\n \n #include \"mlx5.h\"\n+#include \"hws/mlx5dr.h\"\n+#include \"hws/mlx5dr_rule.h\"\n \n /* E-Switch Manager port, used for rte_flow_item_port_id. */\n #define MLX5_PORT_ESW_MGR UINT32_MAX\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 78c741bb91..7343d59f1f 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -1107,7 +1107,7 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev,\n \t\t\t\t actions, rule_acts, &acts_num);\n \tret = mlx5dr_rule_create(table->matcher,\n \t\t\t\t pattern_template_index, items,\n-\t\t\t\t rule_acts, acts_num,\n+\t\t\t\t action_template_index, rule_acts,\n \t\t\t\t &rule_attr, &flow->rule);\n \tif (likely(!ret))\n \t\treturn (struct rte_flow *)flow;\n@@ -1498,7 +1498,7 @@ flow_hw_table_create(struct rte_eth_dev *dev,\n \t\ttbl->its[i] = item_templates[i];\n \t}\n \ttbl->matcher = mlx5dr_matcher_create\n-\t\t(tbl->grp->tbl, mt, nb_item_templates, &matcher_attr);\n+\t\t(tbl->grp->tbl, mt, nb_item_templates, NULL, 0, &matcher_attr);\n \tif (!tbl->matcher)\n \t\tgoto it_error;\n \ttbl->nb_item_templates = nb_item_templates;\n", "prefixes": [ "v2", "19/19" ] }