Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/117213/?format=api
{ "id": 117213, "url": "http://patches.dpdk.org/api/patches/117213/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220930125315.5079-4-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220930125315.5079-4-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220930125315.5079-4-suanmingm@nvidia.com", "date": "2022-09-30T12:53:01", "name": "[v3,03/17] net/mlx5: add shared header reformat support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a79ad452df6cb905ad89f00f57d8e35bfd4733dc", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220930125315.5079-4-suanmingm@nvidia.com/mbox/", "series": [ { "id": 24935, "url": "http://patches.dpdk.org/api/series/24935/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24935", "date": "2022-09-30T12:52:58", "name": "net/mlx5: HW steering PMD update", "version": 3, "mbox": "http://patches.dpdk.org/series/24935/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/117213/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/117213/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 38E64A00C4;\n\tFri, 30 Sep 2022 14:53:55 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id D56044280E;\n\tFri, 30 Sep 2022 14:53:47 +0200 (CEST)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2053.outbound.protection.outlook.com [40.107.220.53])\n by mails.dpdk.org (Postfix) with ESMTP id B0890427F7\n for <dev@dpdk.org>; Fri, 30 Sep 2022 14:53:45 +0200 (CEST)", "from DS7PR06CA0038.namprd06.prod.outlook.com (2603:10b6:8:54::19) by\n LV2PR12MB5800.namprd12.prod.outlook.com (2603:10b6:408:178::12) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.20; Fri, 30 Sep\n 2022 12:53:43 +0000", "from DM6NAM11FT031.eop-nam11.prod.protection.outlook.com\n (2603:10b6:8:54:cafe::1e) by DS7PR06CA0038.outlook.office365.com\n (2603:10b6:8:54::19) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5676.23 via Frontend\n Transport; Fri, 30 Sep 2022 12:53:43 +0000", "from mail.nvidia.com (216.228.117.160) by\n DM6NAM11FT031.mail.protection.outlook.com (10.13.172.203) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.5676.17 via Frontend Transport; Fri, 30 Sep 2022 12:53:43 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 30 Sep\n 2022 05:53:39 -0700", "from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep\n 2022 05:53:37 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=exRU0qYbjCaW5q7Z5NhmqXskkkJO4iJPVhTapXyhmpEjvthKpqKpFbd8DgVitiHaCspR/PB323jhYVxXUKRhBWcJpF1/pAZCuXEBFHWq/ACF+b3T1+NprGvxW2rqDUWDggoP40acIgDk+C/vjBNLMXX9zk6NSuskVK2+26kdt4lBCug6ZteoVyWDndQJTx/Ul3sqO55wlhcB5ivmayp84JacxB23HnSWUbHRPObIMEkRticvSvtf9xIzzxd/V3PQU1DWm2izONA/6tCPvWeeKZCqgbvUf+u8tu511oA4G+vkrH647l351kP3YuM/LlC8C+ozEMOkQnN4/AAv32A5QQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=ybLPPrfAx5pOZBmLeKwO8WikZMPmbcU7ZawPMEOSslY=;\n b=jWsUm73LRqnMzxiL4vbBisgt+j9LScJ9sQEiEaNP5bHEJi36JQgOpYpQsf+VfZ/qStxfgzuQU23ZBw278u4pZeEtcT222Z1ANeibfzkX3qIySuDGqTLrgVvuhAq9OGo9jRGzuNz0ijEImjt5ExQHrVNI+gLZyJB3dDAFpl0LGAGmQKx72+TV8aubLcwXu2z0FGje7P3QaGm6m5U/Jt/9QGZgtfKUt8I76p+yiPEV2fzqAZFs9P4HaED0bPrsdUWLJ/9UViEkGnwtUBC3cQU3SBU5hvfdZ6IpZQxZ1qeuhy6RXmEtJSHt22WMvlnDaq/GqrBZOmnM3A4LJg3bbXMYQg==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=ybLPPrfAx5pOZBmLeKwO8WikZMPmbcU7ZawPMEOSslY=;\n b=hQ9NwbrmASgBLLg3AHxvR/xjZHAZfvYrH/C5sXsUC8+jE12/TaCYNIealgtsOhD3uwLntjOPaESzaWtKqnZ96/i0FsI0NFMaLWlQCTwvGQN41tFrlUtxQmnc/GMOaq0+rON8NNDR0pOJ0KwmuXKoIFM8SBzTu9MQB6cGV1eBoBQ2yKxjCbWwM2fCx4mhlzLpoMQi8N4VeRTylIFZuRg4aUJiRQ2LZhYwqLiUgzJx9k+WvXAnC6kJQMkCb/PFXc8V+QtVqsEp0juxXRRrjseCSvmUIgnSKm2FUUVqSJCH0Eq0+zPCgx9x84NcZVWk5SoSe9E30mvzEwLasfxk+7/4Jg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>, <orika@nvidia.com>", "Subject": "[PATCH v3 03/17] net/mlx5: add shared header reformat support", "Date": "Fri, 30 Sep 2022 15:53:01 +0300", "Message-ID": "<20220930125315.5079-4-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220930125315.5079-1-suanmingm@nvidia.com>", "References": "<20220923144334.27736-1-suanmingm@nvidia.com>\n <20220930125315.5079-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT031:EE_|LV2PR12MB5800:EE_", "X-MS-Office365-Filtering-Correlation-Id": "d248b72d-59cb-44f9-f8bc-08daa2e2ce68", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n vQiCeSYOa+CYrs4s/ZE3kAciGAOY517vUKn9J/bbSpqOf0W8C52DCM8+iDKKSWJcTI6CfuL8ldBRlOM4iZMUnZryWQ0JVo7+ZJAP4ZwKimYfpi5tLsHe1U6BAMb7dJuGwKByX8oRvPIpCCeqpnf7XGvTFsMp6PMBvPTR/Itl7RzXFqTE25kUKAUS6bzRo/Uwx58ojomgUCTHrthx986KlF2egTTbLKZqvfmv+6g31HofkSJtvYSpaqmsnOkq28J7jY0IqRXGDvxK8CZHT/JsFTIS6zYHWB/nUcYn0KgWgxjwRKvhdhwMXiel3DMhdIOySe5I/vZcA6mI5qB48kfo+HsoVrq524krqRRHPfpx0F4m8WZPyqx8a26I1EQnlfTiQYqfmVEIuuBeO3nFYvpaPksD6z/4PeldPCb0DpuE6g/ZClLQXeG3NalSmPEXHKSx5bKAfxEqCuRrcBpMIQvET6nSrjenLsiPJTeqaqf/XBByQ8cS10EVj3oOwc57arH/fTz0g56VEUsvTzj/HB7jDCznT5KIkzb/qexHWcqnmsacHTOVz4aBtKEgPCcLKIOHq42YoAidTEFVALNJuC7Kkelk/bXCAYmhQXL16+847TU4ZuTNamDOpgNDEBUJZaEOUVWMDxIIlYshC+//l0dg5u4s1rmbbZOtQr61okAMxpN5NJU7joSsybM/y+hgk3fDz0yYO20wzEKA8w40PVWCA5yvaOof5FOELtmhhyYGjsckieROyO2cJRbxUS/UkxUM9zZdoIg4CeS2DxZQV92vzg==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(376002)(396003)(39860400002)(346002)(136003)(451199015)(40470700004)(46966006)(36840700001)(47076005)(7636003)(82310400005)(8676002)(336012)(316002)(4326008)(426003)(86362001)(54906003)(1076003)(186003)(110136005)(6636002)(2616005)(16526019)(82740400003)(478600001)(26005)(70206006)(40460700003)(70586007)(356005)(7696005)(6286002)(6666004)(107886003)(83380400001)(2906002)(55016003)(36756003)(36860700001)(40480700001)(5660300002)(41300700001)(8936002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Sep 2022 12:53:43.4234 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n d248b72d-59cb-44f9-f8bc-08daa2e2ce68", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT031.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV2PR12MB5800", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "As the rte_flow_async API defines, the action mask with field value\nnot be 0 means the action will be used as shared in all the flows in\nthe table.\n\nThe header reformat action with action mask field not be 0 will be\ncreated as constant shared action. For encapsulation header reformat\naction, there are two kinds of encapsulation data, raw_encap_data\nand rte_flow_item encap_data. Both of these two kinds of data can be\nidentified from the action mask conf as constant or not.\n\nExamples:\n1. VXLAN encap (encap_data: rte_flow_item)\n\taction conf (eth/ipv4/udp/vxlan_hdr)\n\n\ta. action mask conf (eth/ipv4/udp/vxlan_hdr)\n\t - items are constant.\n\tb. action mask conf (NULL)\n\t - items will change.\n\n2. RAW encap (encap_data: raw)\n\taction conf (raw_data)\n\n\ta. action mask conf (not NULL)\n\t - encap_data constant.\n\tb. action mask conf (NULL)\n\t - encap_data will change.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 6 +-\n drivers/net/mlx5/mlx5_flow_hw.c | 124 ++++++++++----------------------\n 2 files changed, 39 insertions(+), 91 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 4b53912b79..1c9f5fc1d5 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1064,10 +1064,6 @@ struct mlx5_action_construct_data {\n \tuint16_t action_dst; /* mlx5dr_rule_action dst offset. */\n \tunion {\n \t\tstruct {\n-\t\t\t/* encap src(item) offset. */\n-\t\t\tuint16_t src;\n-\t\t\t/* encap dst data offset. */\n-\t\t\tuint16_t dst;\n \t\t\t/* encap data len. */\n \t\t\tuint16_t len;\n \t\t} encap;\n@@ -1110,6 +1106,8 @@ struct mlx5_hw_jump_action {\n /* Encap decap action struct. */\n struct mlx5_hw_encap_decap_action {\n \tstruct mlx5dr_action *action; /* Action object. */\n+\t/* Is header_reformat action shared across flows in table. */\n+\tbool shared;\n \tsize_t data_size; /* Action metadata size. */\n \tuint8_t data[]; /* Action data. */\n };\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 46c4169b4f..b6978bd051 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -402,10 +402,6 @@ __flow_hw_act_data_general_append(struct mlx5_priv *priv,\n * Offset of source rte flow action.\n * @param[in] action_dst\n * Offset of destination DR action.\n- * @param[in] encap_src\n- * Offset of source encap raw data.\n- * @param[in] encap_dst\n- * Offset of destination encap raw data.\n * @param[in] len\n * Length of the data to be updated.\n *\n@@ -418,16 +414,12 @@ __flow_hw_act_data_encap_append(struct mlx5_priv *priv,\n \t\t\t\tenum rte_flow_action_type type,\n \t\t\t\tuint16_t action_src,\n \t\t\t\tuint16_t action_dst,\n-\t\t\t\tuint16_t encap_src,\n-\t\t\t\tuint16_t encap_dst,\n \t\t\t\tuint16_t len)\n {\tstruct mlx5_action_construct_data *act_data;\n \n \tact_data = __flow_hw_act_data_alloc(priv, type, action_src, action_dst);\n \tif (!act_data)\n \t\treturn -1;\n-\tact_data->encap.src = encap_src;\n-\tact_data->encap.dst = encap_dst;\n \tact_data->encap.len = len;\n \tLIST_INSERT_HEAD(&acts->act_list, act_data, next);\n \treturn 0;\n@@ -523,53 +515,6 @@ flow_hw_shared_action_translate(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n-/**\n- * Translate encap items to encapsulation list.\n- *\n- * @param[in] dev\n- * Pointer to the rte_eth_dev data structure.\n- * @param[in] acts\n- * Pointer to the template HW steering DR actions.\n- * @param[in] type\n- * Action type.\n- * @param[in] action_src\n- * Offset of source rte flow action.\n- * @param[in] action_dst\n- * Offset of destination DR action.\n- * @param[in] items\n- * Encap item pattern.\n- * @param[in] items_m\n- * Encap item mask indicates which part are constant and dynamic.\n- *\n- * @return\n- * 0 on success, negative value otherwise and rte_errno is set.\n- */\n-static __rte_always_inline int\n-flow_hw_encap_item_translate(struct rte_eth_dev *dev,\n-\t\t\t struct mlx5_hw_actions *acts,\n-\t\t\t enum rte_flow_action_type type,\n-\t\t\t uint16_t action_src,\n-\t\t\t uint16_t action_dst,\n-\t\t\t const struct rte_flow_item *items,\n-\t\t\t const struct rte_flow_item *items_m)\n-{\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tsize_t len, total_len = 0;\n-\tuint32_t i = 0;\n-\n-\tfor (; items->type != RTE_FLOW_ITEM_TYPE_END; items++, items_m++, i++) {\n-\t\tlen = flow_dv_get_item_hdr_len(items->type);\n-\t\tif ((!items_m->spec ||\n-\t\t memcmp(items_m->spec, items->spec, len)) &&\n-\t\t __flow_hw_act_data_encap_append(priv, acts, type,\n-\t\t\t\t\t\t action_src, action_dst, i,\n-\t\t\t\t\t\t total_len, len))\n-\t\t\treturn -1;\n-\t\ttotal_len += len;\n-\t}\n-\treturn 0;\n-}\n-\n /**\n * Translate rte_flow actions to DR action.\n *\n@@ -611,7 +556,7 @@ flow_hw_actions_translate(struct rte_eth_dev *dev,\n \tconst struct rte_flow_action_raw_encap *raw_encap_data;\n \tconst struct rte_flow_item *enc_item = NULL, *enc_item_m = NULL;\n \tuint16_t reformat_pos = MLX5_HW_MAX_ACTS, reformat_src = 0;\n-\tuint8_t *encap_data = NULL;\n+\tuint8_t *encap_data = NULL, *encap_data_m = NULL;\n \tsize_t data_size = 0;\n \tbool actions_end = false;\n \tuint32_t type, i;\n@@ -718,9 +663,9 @@ flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\tMLX5_ASSERT(reformat_pos == MLX5_HW_MAX_ACTS);\n \t\t\tenc_item = ((const struct rte_flow_action_vxlan_encap *)\n \t\t\t\t actions->conf)->definition;\n-\t\t\tenc_item_m =\n-\t\t\t\t((const struct rte_flow_action_vxlan_encap *)\n-\t\t\t\t masks->conf)->definition;\n+\t\t\tif (masks->conf)\n+\t\t\t\tenc_item_m = ((const struct rte_flow_action_vxlan_encap *)\n+\t\t\t\t\t masks->conf)->definition;\n \t\t\treformat_pos = i++;\n \t\t\treformat_src = actions - action_start;\n \t\t\trefmt_type = MLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L2;\n@@ -729,9 +674,9 @@ flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\tMLX5_ASSERT(reformat_pos == MLX5_HW_MAX_ACTS);\n \t\t\tenc_item = ((const struct rte_flow_action_nvgre_encap *)\n \t\t\t\t actions->conf)->definition;\n-\t\t\tenc_item_m =\n-\t\t\t\t((const struct rte_flow_action_nvgre_encap *)\n-\t\t\t\tactions->conf)->definition;\n+\t\t\tif (masks->conf)\n+\t\t\t\tenc_item_m = ((const struct rte_flow_action_nvgre_encap *)\n+\t\t\t\t\t masks->conf)->definition;\n \t\t\treformat_pos = i++;\n \t\t\treformat_src = actions - action_start;\n \t\t\trefmt_type = MLX5DR_ACTION_REFORMAT_TYPE_L2_TO_TNL_L2;\n@@ -743,6 +688,11 @@ flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\trefmt_type = MLX5DR_ACTION_REFORMAT_TYPE_TNL_L2_TO_L2;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_RAW_ENCAP:\n+\t\t\traw_encap_data =\n+\t\t\t\t(const struct rte_flow_action_raw_encap *)\n+\t\t\t\t masks->conf;\n+\t\t\tif (raw_encap_data)\n+\t\t\t\tencap_data_m = raw_encap_data->data;\n \t\t\traw_encap_data =\n \t\t\t\t(const struct rte_flow_action_raw_encap *)\n \t\t\t\t actions->conf;\n@@ -773,22 +723,17 @@ flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t}\n \tif (reformat_pos != MLX5_HW_MAX_ACTS) {\n \t\tuint8_t buf[MLX5_ENCAP_MAX_LEN];\n+\t\tbool shared_rfmt = true;\n \n \t\tif (enc_item) {\n \t\t\tMLX5_ASSERT(!encap_data);\n-\t\t\tif (flow_dv_convert_encap_data\n-\t\t\t\t(enc_item, buf, &data_size, error) ||\n-\t\t\t flow_hw_encap_item_translate\n-\t\t\t\t(dev, acts, (action_start + reformat_src)->type,\n-\t\t\t\t reformat_src, reformat_pos,\n-\t\t\t\t enc_item, enc_item_m))\n+\t\t\tif (flow_dv_convert_encap_data(enc_item, buf, &data_size, error))\n \t\t\t\tgoto err;\n \t\t\tencap_data = buf;\n-\t\t} else if (encap_data && __flow_hw_act_data_encap_append\n-\t\t\t\t(priv, acts,\n-\t\t\t\t (action_start + reformat_src)->type,\n-\t\t\t\t reformat_src, reformat_pos, 0, 0, data_size)) {\n-\t\t\tgoto err;\n+\t\t\tif (!enc_item_m)\n+\t\t\t\tshared_rfmt = false;\n+\t\t} else if (encap_data && !encap_data_m) {\n+\t\t\tshared_rfmt = false;\n \t\t}\n \t\tacts->encap_decap = mlx5_malloc(MLX5_MEM_ZERO,\n \t\t\t\t sizeof(*acts->encap_decap) + data_size,\n@@ -802,12 +747,22 @@ flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\tacts->encap_decap->action = mlx5dr_action_create_reformat\n \t\t\t\t(priv->dr_ctx, refmt_type,\n \t\t\t\t data_size, encap_data,\n-\t\t\t\t rte_log2_u32(table_attr->nb_flows),\n-\t\t\t\t mlx5_hw_act_flag[!!attr->group][type]);\n+\t\t\t\t shared_rfmt ? 0 : rte_log2_u32(table_attr->nb_flows),\n+\t\t\t\t mlx5_hw_act_flag[!!attr->group][type] |\n+\t\t\t\t (shared_rfmt ? MLX5DR_ACTION_FLAG_SHARED : 0));\n \t\tif (!acts->encap_decap->action)\n \t\t\tgoto err;\n \t\tacts->rule_acts[reformat_pos].action =\n \t\t\t\t\t\tacts->encap_decap->action;\n+\t\tacts->rule_acts[reformat_pos].reformat.data =\n+\t\t\t\t\t\tacts->encap_decap->data;\n+\t\tif (shared_rfmt)\n+\t\t\tacts->rule_acts[reformat_pos].reformat.offset = 0;\n+\t\telse if (__flow_hw_act_data_encap_append(priv, acts,\n+\t\t\t\t (action_start + reformat_src)->type,\n+\t\t\t\t reformat_src, reformat_pos, data_size))\n+\t\t\tgoto err;\n+\t\tacts->encap_decap->shared = shared_rfmt;\n \t\tacts->encap_decap_pos = reformat_pos;\n \t}\n \tacts->acts_num = i;\n@@ -972,6 +927,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t.ingress = 1,\n \t};\n \tuint32_t ft_flag;\n+\tsize_t encap_len = 0;\n \n \tmemcpy(rule_acts, hw_acts->rule_acts,\n \t sizeof(*rule_acts) * hw_acts->acts_num);\n@@ -989,9 +945,6 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t} else {\n \t\tattr.ingress = 1;\n \t}\n-\tif (hw_acts->encap_decap && hw_acts->encap_decap->data_size)\n-\t\tmemcpy(buf, hw_acts->encap_decap->data,\n-\t\t hw_acts->encap_decap->data_size);\n \tLIST_FOREACH(act_data, &hw_acts->act_list, next) {\n \t\tuint32_t jump_group;\n \t\tuint32_t tag;\n@@ -1050,23 +1003,20 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP:\n \t\t\tenc_item = ((const struct rte_flow_action_vxlan_encap *)\n \t\t\t\t action->conf)->definition;\n-\t\t\trte_memcpy((void *)&buf[act_data->encap.dst],\n-\t\t\t\t enc_item[act_data->encap.src].spec,\n-\t\t\t\t act_data->encap.len);\n+\t\t\tif (flow_dv_convert_encap_data(enc_item, buf, &encap_len, NULL))\n+\t\t\t\treturn -1;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP:\n \t\t\tenc_item = ((const struct rte_flow_action_nvgre_encap *)\n \t\t\t\t action->conf)->definition;\n-\t\t\trte_memcpy((void *)&buf[act_data->encap.dst],\n-\t\t\t\t enc_item[act_data->encap.src].spec,\n-\t\t\t\t act_data->encap.len);\n+\t\t\tif (flow_dv_convert_encap_data(enc_item, buf, &encap_len, NULL))\n+\t\t\t\treturn -1;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_RAW_ENCAP:\n \t\t\traw_encap_data =\n \t\t\t\t(const struct rte_flow_action_raw_encap *)\n \t\t\t\t action->conf;\n-\t\t\trte_memcpy((void *)&buf[act_data->encap.dst],\n-\t\t\t\t raw_encap_data->data, act_data->encap.len);\n+\t\t\trte_memcpy((void *)buf, raw_encap_data->data, act_data->encap.len);\n \t\t\tMLX5_ASSERT(raw_encap_data->size ==\n \t\t\t\t act_data->encap.len);\n \t\t\tbreak;\n@@ -1074,7 +1024,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\tbreak;\n \t\t}\n \t}\n-\tif (hw_acts->encap_decap) {\n+\tif (hw_acts->encap_decap && !hw_acts->encap_decap->shared) {\n \t\trule_acts[hw_acts->encap_decap_pos].reformat.offset =\n \t\t\t\tjob->flow->idx - 1;\n \t\trule_acts[hw_acts->encap_decap_pos].reformat.data = buf;\n", "prefixes": [ "v3", "03/17" ] }