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GET /api/patches/117212/?format=api
{ "id": 117212, "url": "http://patches.dpdk.org/api/patches/117212/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220930125315.5079-3-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220930125315.5079-3-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220930125315.5079-3-suanmingm@nvidia.com", "date": "2022-09-30T12:53:00", "name": "[v3,02/17] net/mlx5: fix IPv6 and TCP RSS hash fields", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "4412349130564eb21a110a4e817ef9f4c46d2c1e", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220930125315.5079-3-suanmingm@nvidia.com/mbox/", "series": [ { "id": 24935, "url": "http://patches.dpdk.org/api/series/24935/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24935", "date": "2022-09-30T12:52:58", "name": "net/mlx5: HW steering PMD update", "version": 3, "mbox": "http://patches.dpdk.org/series/24935/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/117212/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/117212/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 16528A00C4;\n\tFri, 30 Sep 2022 14:53:47 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 99FF3427FF;\n\tFri, 30 Sep 2022 14:53:41 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2056.outbound.protection.outlook.com [40.107.223.56])\n by mails.dpdk.org (Postfix) with ESMTP id 359A2427F7\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>, <orika@nvidia.com>", "Subject": "[PATCH v3 02/17] net/mlx5: fix IPv6 and TCP RSS hash fields", "Date": "Fri, 30 Sep 2022 15:53:00 +0300", "Message-ID": "<20220930125315.5079-3-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220930125315.5079-1-suanmingm@nvidia.com>", "References": "<20220923144334.27736-1-suanmingm@nvidia.com>\n <20220930125315.5079-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT105:EE_|DM4PR12MB5391:EE_", "X-MS-Office365-Filtering-Correlation-Id": "32b25d43-0a83-40c4-76f3-08daa2e2cb05", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n lpo0jFLiFASb6KgFN0yZNbqnxnxigA1L1OVZgPdYum6zqiA3ZdD4suRchvq7A9F/hCRG+Qq6CGO15OYbTESoNzesxyzSZoeCTdWIPpVcDF5AtfBrA7nSPE/uup22frK2NU6JgPiJzt0geFUqzBED1D2+cOQWM5lE0/d2V/KNOa11VhgvzNMQPfjVEpEA8ezQojVHwcN8ms4EvoENhNiITYUl3mnZdgA8i515XX+vAPubfP32V3LLEOx3uC2qCphR3GkkOXYBZKkKmvCn1ZAdIiQ4W3YVngwCQWaJkbGgvlwAT0P9NWYYNTRpdwpHeF7HgR9pQVrv75yl8zPI5i3iGte6VJKifagSZMF70cPva+gzSApbuW0r4bOuGfsBk+6CWw165ltz92Ub7agwkbXVQuzrg6wdtvP6Hb1IzT7t7HmqbYIOTcOFU4oKXD/bcT/Rt5sGwrKmvP6asBjnPKf99OvFnGf1GoF3LB77OB43kx1hUOh8d8DiCQhQ9tP6zrxZCmynK5KtyJ7gkDe65pZP8qcBvaPBKPq/lIJgJe8/AobdQtNseKYgTDtQXbGrBQ+YjrMDMdhWFeKpDwaadYuTobWd1i7IAoNzzdDbIynBUdVT319YBnEfKSzOrLKAlyyT/Z1I38Rq5u1s8Z7lJ7HZzQv3kvYNFKkOLiZAHoTufq98vty/+32zP9TjQFqivbC3S8yd+SQa/uB2a6mdlXm4lPz1rzwwnrVQUQzG/6vAUZuTDuhyiCcRR3GkzKfP1h+EGBsa93l+Obt9ySbKSnjZ8Q==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(39860400002)(346002)(136003)(376002)(396003)(451199015)(46966006)(36840700001)(40470700004)(54906003)(6636002)(336012)(1076003)(55016003)(2906002)(110136005)(7636003)(356005)(40480700001)(40460700003)(36860700001)(36756003)(8936002)(70206006)(83380400001)(41300700001)(16526019)(8676002)(5660300002)(4326008)(70586007)(82740400003)(47076005)(426003)(316002)(2616005)(26005)(6286002)(86362001)(7696005)(107886003)(6666004)(82310400005)(478600001)(186003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Sep 2022 12:53:37.7225 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 32b25d43-0a83-40c4-76f3-08daa2e2cb05", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT105.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB5391", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "In the flow_dv_hashfields_set() function, while item_flags was 0,\nthe code went directly to the first if and the else case would\nnever have chance be checked. This caused the IPv6 and TCP hash\nfileds in the else case would never be set.\n\nThis commit adds the dedicate HW steering hash field set function\nto generate the RSS hash fields.\n\nFixes: 6540da0b93b5 (\"net/mlx5: fix RSS scaling issue\")\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow_dv.c | 12 +++----\n drivers/net/mlx5/mlx5_flow_hw.c | 59 ++++++++++++++++++++++++++++++++-\n 2 files changed, 62 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex fb08684114..cb034a01f9 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -11299,8 +11299,7 @@ flow_dv_hashfields_set(uint64_t item_flags,\n \t\trss_inner = 1;\n #endif\n \tif ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV4)) ||\n-\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4)) ||\n-\t !items) {\n+\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV4))) {\n \t\tif (rss_types & MLX5_IPV4_LAYER_TYPES) {\n \t\t\tif (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)\n \t\t\t\tfields |= IBV_RX_HASH_SRC_IPV4;\n@@ -11310,8 +11309,7 @@ flow_dv_hashfields_set(uint64_t item_flags,\n \t\t\t\tfields |= MLX5_IPV4_IBV_RX_HASH;\n \t\t}\n \t} else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L3_IPV6)) ||\n-\t\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6)) ||\n-\t\t !items) {\n+\t\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L3_IPV6))) {\n \t\tif (rss_types & MLX5_IPV6_LAYER_TYPES) {\n \t\t\tif (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)\n \t\t\t\tfields |= IBV_RX_HASH_SRC_IPV6;\n@@ -11334,8 +11332,7 @@ flow_dv_hashfields_set(uint64_t item_flags,\n \t\treturn;\n \t}\n \tif ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_UDP)) ||\n-\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP)) ||\n-\t !items) {\n+\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_UDP))) {\n \t\tif (rss_types & RTE_ETH_RSS_UDP) {\n \t\t\tif (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)\n \t\t\t\tfields |= IBV_RX_HASH_SRC_PORT_UDP;\n@@ -11345,8 +11342,7 @@ flow_dv_hashfields_set(uint64_t item_flags,\n \t\t\t\tfields |= MLX5_UDP_IBV_RX_HASH;\n \t\t}\n \t} else if ((rss_inner && (items & MLX5_FLOW_LAYER_INNER_L4_TCP)) ||\n-\t\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP)) ||\n-\t\t !items) {\n+\t\t (!rss_inner && (items & MLX5_FLOW_LAYER_OUTER_L4_TCP))) {\n \t\tif (rss_types & RTE_ETH_RSS_TCP) {\n \t\t\tif (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)\n \t\t\t\tfields |= IBV_RX_HASH_SRC_PORT_TCP;\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 7343d59f1f..46c4169b4f 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -62,6 +62,63 @@ flow_hw_rxq_flag_set(struct rte_eth_dev *dev, bool enable)\n \tpriv->mark_enabled = enable;\n }\n \n+/**\n+ * Set the hash fields according to the @p rss_desc information.\n+ *\n+ * @param[in] rss_desc\n+ * Pointer to the mlx5_flow_rss_desc.\n+ * @param[out] hash_fields\n+ * Pointer to the RSS hash fields.\n+ */\n+static void\n+flow_hw_hashfields_set(struct mlx5_flow_rss_desc *rss_desc,\n+\t\t uint64_t *hash_fields)\n+{\n+\tuint64_t fields = 0;\n+\tint rss_inner = 0;\n+\tuint64_t rss_types = rte_eth_rss_hf_refine(rss_desc->types);\n+\n+#ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT\n+\tif (rss_desc->level >= 2)\n+\t\trss_inner = 1;\n+#endif\n+\tif (rss_types & MLX5_IPV4_LAYER_TYPES) {\n+\t\tif (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_SRC_IPV4;\n+\t\telse if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_DST_IPV4;\n+\t\telse\n+\t\t\tfields |= MLX5_IPV4_IBV_RX_HASH;\n+\t} else if (rss_types & MLX5_IPV6_LAYER_TYPES) {\n+\t\tif (rss_types & RTE_ETH_RSS_L3_SRC_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_SRC_IPV6;\n+\t\telse if (rss_types & RTE_ETH_RSS_L3_DST_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_DST_IPV6;\n+\t\telse\n+\t\t\tfields |= MLX5_IPV6_IBV_RX_HASH;\n+\t}\n+\tif (rss_types & RTE_ETH_RSS_UDP) {\n+\t\tif (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_SRC_PORT_UDP;\n+\t\telse if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_DST_PORT_UDP;\n+\t\telse\n+\t\t\tfields |= MLX5_UDP_IBV_RX_HASH;\n+\t} else if (rss_types & RTE_ETH_RSS_TCP) {\n+\t\tif (rss_types & RTE_ETH_RSS_L4_SRC_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_SRC_PORT_TCP;\n+\t\telse if (rss_types & RTE_ETH_RSS_L4_DST_ONLY)\n+\t\t\tfields |= IBV_RX_HASH_DST_PORT_TCP;\n+\t\telse\n+\t\t\tfields |= MLX5_TCP_IBV_RX_HASH;\n+\t}\n+\tif (rss_types & RTE_ETH_RSS_ESP)\n+\t\tfields |= IBV_RX_HASH_IPSEC_SPI;\n+\tif (rss_inner)\n+\t\tfields |= IBV_RX_HASH_INNER;\n+\t*hash_fields = fields;\n+}\n+\n /**\n * Generate the pattern item flags.\n * Will be used for shared RSS action.\n@@ -225,7 +282,7 @@ flow_hw_tir_action_register(struct rte_eth_dev *dev,\n \t\t MLX5_RSS_HASH_KEY_LEN);\n \t\trss_desc.key_len = MLX5_RSS_HASH_KEY_LEN;\n \t\trss_desc.types = !rss->types ? RTE_ETH_RSS_IP : rss->types;\n-\t\tflow_dv_hashfields_set(0, &rss_desc, &rss_desc.hash_fields);\n+\t\tflow_hw_hashfields_set(&rss_desc, &rss_desc.hash_fields);\n \t\tflow_dv_action_rss_l34_hash_adjust(rss->types,\n \t\t\t\t\t\t &rss_desc.hash_fields);\n \t\tif (rss->level > 1) {\n", "prefixes": [ "v3", "02/17" ] }