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GET /api/patches/117052/?format=api
{ "id": 117052, "url": "http://patches.dpdk.org/api/patches/117052/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220928124516.93050-2-gakhil@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220928124516.93050-2-gakhil@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220928124516.93050-2-gakhil@marvell.com", "date": "2022-09-28T12:45:12", "name": "[1/5] common/cnxk: add ROC APIs for MACsec", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "fc2946e5f6a89d31b29bac1d43dcce831fcf9f5c", "submitter": { "id": 2094, "url": "http://patches.dpdk.org/api/people/2094/?format=api", "name": "Akhil Goyal", "email": "gakhil@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220928124516.93050-2-gakhil@marvell.com/mbox/", "series": [ { "id": 24879, "url": "http://patches.dpdk.org/api/series/24879/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24879", "date": "2022-09-28T12:45:11", "name": "Support and test inline MACsec for cnxk", "version": 1, "mbox": "http://patches.dpdk.org/series/24879/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/117052/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/117052/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A20DCA00C4;\n\tWed, 28 Sep 2022 14:45:55 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 95CB1427F3;\n\tWed, 28 Sep 2022 14:45:55 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 35F884113C\n for <dev@dpdk.org>; Wed, 28 Sep 2022 14:45:52 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 28SA4cpX003076;\n Wed, 28 Sep 2022 05:45:51 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3jvjkk8skd-3\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Wed, 28 Sep 2022 05:45:42 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Wed, 28 Sep 2022 05:45:29 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Wed, 28 Sep 2022 05:45:29 -0700", "from localhost.localdomain (unknown [10.28.36.102])\n by maili.marvell.com (Postfix) with ESMTP id DBAF53F7068;\n Wed, 28 Sep 2022 05:45:24 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=ovZ6oE3Ll0O9gVynE8ttD0B+KuSjIn+MH0g4TFkqp9s=;\n b=StJAorTF9JcCd8LihH/UEWNHK5cxr6cH7+aDc/O0a6RyK/BrUrqPRLkho9b3P4IgmChG\n /Ml/y6ffZhYoao9k+gaNFdEGrH2aywJzKQJQzEHVKb/m5BlPvPh0P7d9J+aFCDBnoNXb\n 8K+RjY0pihE3CzWSBTmG7hJvgCli0TjvT3sswrWgtTauH5V33MY7NEoqz2GsrQUTO9Bn\n OHmjNhmQZD/5Hh+FqHol2aVgVrpH51MaAM3i0mxpAtqsC8aDBm+axKBQ1o8Ew8KVvmuK\n J2AQ7bZ04AVuC1IoPLMfUsnDtsULNfTg2GvoS5WNXbcc/p2zAUXNXccEuhi1pTc1i6qs /g==", "From": "Akhil Goyal <gakhil@marvell.com>", "To": "<dev@dpdk.org>", "CC": "<thomas@monjalon.net>, <olivier.matz@6wind.com>, <orika@nvidia.com>,\n <david.marchand@redhat.com>, <hemant.agrawal@nxp.com>,\n <vattunuru@marvell.com>, <ferruh.yigit@xilinx.com>,\n <andrew.rybchenko@oktetlabs.ru>, <konstantin.v.ananyev@yandex.ru>,\n <jiawenwu@trustnetic.com>, <yisen.zhuang@huawei.com>,\n <irusskikh@marvell.com>, <qiming.yang@intel.com>, <jerinj@marvell.com>,\n <adwivedi@marvell.com>, Akhil Goyal <gakhil@marvell.com>", "Subject": "[PATCH 1/5] common/cnxk: add ROC APIs for MACsec", "Date": "Wed, 28 Sep 2022 18:15:12 +0530", "Message-ID": "<20220928124516.93050-2-gakhil@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220928124516.93050-1-gakhil@marvell.com>", "References": "<20220928122253.23108-4-gakhil@marvell.com>\n <20220928124516.93050-1-gakhil@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "B1Kw_whNCTCgfiyu39uPtNrPWYZdDKTn", "X-Proofpoint-ORIG-GUID": "B1Kw_whNCTCgfiyu39uPtNrPWYZdDKTn", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1\n definitions=2022-09-28_05,2022-09-28_01,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Added mbox related to configuration of MACsec.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Vamsi Attunuru <vattunuru@marvell.com>\nSigned-off-by: Akhil Goyal <gakhil@marvell.com>\n---\n drivers/common/cnxk/meson.build | 3 +\n drivers/common/cnxk/roc_api.h | 3 +\n drivers/common/cnxk/roc_dev.c | 86 +++++\n drivers/common/cnxk/roc_mbox.h | 361 ++++++++++++++++++++-\n drivers/common/cnxk/roc_mcs.c | 347 +++++++++++++++++++++\n drivers/common/cnxk/roc_mcs.h | 431 ++++++++++++++++++++++++++\n drivers/common/cnxk/roc_mcs_priv.h | 52 ++++\n drivers/common/cnxk/roc_mcs_sec_cfg.c | 425 +++++++++++++++++++++++++\n drivers/common/cnxk/roc_mcs_stats.c | 230 ++++++++++++++\n drivers/common/cnxk/roc_priv.h | 3 +\n drivers/common/cnxk/version.map | 33 ++\n 11 files changed, 1971 insertions(+), 3 deletions(-)\n create mode 100644 drivers/common/cnxk/roc_mcs.c\n create mode 100644 drivers/common/cnxk/roc_mcs.h\n create mode 100644 drivers/common/cnxk/roc_mcs_priv.h\n create mode 100644 drivers/common/cnxk/roc_mcs_sec_cfg.c\n create mode 100644 drivers/common/cnxk/roc_mcs_stats.c", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 127fcbcdc5..02264016e3 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -26,6 +26,9 @@ sources = files(\n 'roc_irq.c',\n 'roc_ie_ot.c',\n 'roc_mbox.c',\n+ 'roc_mcs.c',\n+\t'roc_mcs_sec_cfg.c',\n+ 'roc_mcs_stats.c',\n 'roc_model.c',\n 'roc_nix.c',\n 'roc_nix_bpf.c',\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 072f16d77d..bcc8746927 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -106,4 +106,7 @@\n /* NIX Inline dev */\n #include \"roc_nix_inl.h\"\n \n+/* MACsec */\n+#include \"roc_mcs.h\"\n+\n #endif /* _ROC_API_H_ */\ndiff --git a/drivers/common/cnxk/roc_dev.c b/drivers/common/cnxk/roc_dev.c\nindex 59128a3552..b4d492ed08 100644\n--- a/drivers/common/cnxk/roc_dev.c\n+++ b/drivers/common/cnxk/roc_dev.c\n@@ -501,6 +501,91 @@ pf_vf_mbox_send_up_msg(struct dev *dev, void *rec_msg)\n \t}\n }\n \n+static int\n+mbox_up_handler_mcs_intr_notify(struct dev *dev, struct mcs_intr_info *info, struct msg_rsp *rsp)\n+{\n+\tstruct roc_mcs_event_desc desc = {0};\n+\tstruct roc_mcs *mcs;\n+\n+\tplt_base_dbg(\"pf:%d/vf:%d msg id 0x%x (%s) from: pf:%d/vf:%d\", dev_get_pf(dev->pf_func),\n+\t\t dev_get_vf(dev->pf_func), info->hdr.id, mbox_id2name(info->hdr.id),\n+\t\t dev_get_pf(info->hdr.pcifunc), dev_get_vf(info->hdr.pcifunc));\n+\n+\tmcs = roc_mcs_dev_get(info->mcs_id);\n+\tif (!mcs)\n+\t\tgoto exit;\n+\n+\tif (info->intr_mask) {\n+\t\tswitch (info->intr_mask) {\n+\t\tcase MCS_CPM_RX_SECTAG_V_EQ1_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_RX_SECTAG_V_EQ1;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_RX_SECTAG_SL_GTE48_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_RX_SECTAG_SL_GTE48;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_SECTAG_VAL_ERR;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_RX_PACKET_XPN_EQ0_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_RX_SA_PN_HARD_EXP;\n+\t\t\tdesc.metadata.sa_idx = info->sa_id;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_RX_PN_THRESH_REACHED_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP;\n+\t\t\tdesc.metadata.sa_idx = info->sa_id;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_TX_PACKET_XPN_EQ0_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_TX_SA_PN_HARD_EXP;\n+\t\t\tdesc.metadata.sa_idx = info->sa_id;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_TX_PN_THRESH_REACHED_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP;\n+\t\t\tdesc.metadata.sa_idx = info->sa_id;\n+\t\t\tbreak;\n+\t\tcase MCS_CPM_TX_SA_NOT_VALID_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_SA_NOT_VALID;\n+\t\t\tbreak;\n+\t\tcase MCS_BBE_RX_DFIFO_OVERFLOW_INT:\n+\t\tcase MCS_BBE_TX_DFIFO_OVERFLOW_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_FIFO_OVERFLOW;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_DATA_FIFO_OVERFLOW;\n+\t\t\tdesc.metadata.lmac_id = info->lmac_id;\n+\t\t\tbreak;\n+\t\tcase MCS_BBE_RX_PLFIFO_OVERFLOW_INT:\n+\t\tcase MCS_BBE_TX_PLFIFO_OVERFLOW_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_FIFO_OVERFLOW;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_POLICY_FIFO_OVERFLOW;\n+\t\t\tdesc.metadata.lmac_id = info->lmac_id;\n+\t\t\tbreak;\n+\t\tcase MCS_PAB_RX_CHAN_OVERFLOW_INT:\n+\t\tcase MCS_PAB_TX_CHAN_OVERFLOW_INT:\n+\t\t\tdesc.type = ROC_MCS_EVENT_FIFO_OVERFLOW;\n+\t\t\tdesc.subtype = ROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW;\n+\t\t\tdesc.metadata.lmac_id = info->lmac_id;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tgoto exit;\n+\t\t}\n+\n+\t\tmcs_event_cb_process(mcs, &desc);\n+\t}\n+\n+exit:\n+\trsp->hdr.rc = 0;\n+\treturn 0;\n+}\n+\n static int\n mbox_up_handler_cgx_link_event(struct dev *dev, struct cgx_link_info_msg *msg,\n \t\t\t struct msg_rsp *rsp)\n@@ -589,6 +674,7 @@ mbox_process_msgs_up(struct dev *dev, struct mbox_msghdr *req)\n \t\treturn err; \\\n \t}\n \t\tMBOX_UP_CGX_MESSAGES\n+\t\tMBOX_UP_MCS_MESSAGES\n #undef M\n \t}\n \ndiff --git a/drivers/common/cnxk/roc_mbox.h b/drivers/common/cnxk/roc_mbox.h\nindex 688c70b4ee..05f96ce192 100644\n--- a/drivers/common/cnxk/roc_mbox.h\n+++ b/drivers/common/cnxk/roc_mbox.h\n@@ -267,16 +267,56 @@ struct mbox_msghdr {\n \tM(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \\\n \t msg_req, nix_inline_ipsec_cfg)\t\t\t\t \\\n \tM(NIX_LF_INLINE_RQ_CFG, 0x8024, nix_lf_inline_rq_cfg, \\\n-\t nix_rq_cpt_field_mask_cfg_req, msg_rsp)\n-\n+\t nix_rq_cpt_field_mask_cfg_req, msg_rsp) \\\n+\tM(MCS_ALLOC_RESOURCES, 0xa000, mcs_alloc_resources, mcs_alloc_rsrc_req,\\\n+\t mcs_alloc_rsrc_rsp) \\\n+\tM(MCS_FREE_RESOURCES, 0xa001, mcs_free_resources, mcs_free_rsrc_req, \\\n+\t msg_rsp) \\\n+\tM(MCS_FLOWID_ENTRY_WRITE, 0xa002, mcs_flowid_entry_write, \\\n+\t mcs_flowid_entry_write_req, msg_rsp) \\\n+\tM(MCS_SECY_PLCY_WRITE, 0xa003, mcs_secy_plcy_write, \\\n+\t mcs_secy_plcy_write_req, msg_rsp) \\\n+\tM(MCS_RX_SC_CAM_WRITE, 0xa004, mcs_rx_sc_cam_write, \\\n+\t mcs_rx_sc_cam_write_req, msg_rsp) \\\n+\tM(MCS_SA_PLCY_WRITE, 0xa005, mcs_sa_plcy_write, \\\n+\t mcs_sa_plcy_write_req, msg_rsp) \\\n+\tM(MCS_TX_SC_SA_MAP_WRITE, 0xa006, mcs_tx_sc_sa_map_write, \\\n+\t mcs_tx_sc_sa_map, msg_rsp) \\\n+\tM(MCS_RX_SC_SA_MAP_WRITE, 0xa007, mcs_rx_sc_sa_map_write, \\\n+\t mcs_rx_sc_sa_map, msg_rsp) \\\n+\tM(MCS_FLOWID_ENA_ENTRY, 0xa008, mcs_flowid_ena_entry, \\\n+\t mcs_flowid_ena_dis_entry, msg_rsp) \\\n+\tM(MCS_PN_TABLE_WRITE, 0xa009, mcs_pn_table_write, \\\n+\t mcs_pn_table_write_req, msg_rsp) \\\n+\tM(MCS_SET_ACTIVE_LMAC, 0xa00a, mcs_set_active_lmac, \\\n+\t mcs_set_active_lmac, msg_rsp) \\\n+\tM(MCS_GET_HW_INFO, 0xa00b, mcs_get_hw_info, msg_req, mcs_hw_info) \\\n+\tM(MCS_GET_FLOWID_STATS, 0xa00c, mcs_get_flowid_stats, mcs_stats_req, \\\n+\t mcs_flowid_stats) \\\n+\tM(MCS_GET_SECY_STATS, 0xa00d, mcs_get_secy_stats, mcs_stats_req, \\\n+\t mcs_secy_stats) \\\n+\tM(MCS_GET_SC_STATS, 0xa00e, mcs_get_sc_stats, mcs_stats_req, \\\n+\t mcs_sc_stats) \\\n+\tM(MCS_GET_SA_STATS, 0xa00f, mcs_get_sa_stats, mcs_stats_req, \\\n+\t mcs_sa_stats) \\\n+\tM(MCS_GET_PORT_STATS, 0xa010, mcs_get_port_stats, mcs_stats_req, \\\n+\t mcs_port_stats) \\\n+\tM(MCS_CLEAR_STATS, 0xa011, mcs_clear_stats, mcs_clear_stats, msg_rsp) \\\n+\tM(MCS_INTR_CFG, 0xa012, mcs_intr_cfg, mcs_intr_cfg, msg_rsp) \\\n+\tM(MCS_SET_LMAC_MODE, 0xa013, mcs_set_lmac_mode, mcs_set_lmac_mode, \\\n+\t msg_rsp) \\\n+ \n /* Messages initiated by AF (range 0xC00 - 0xDFF) */\n #define MBOX_UP_CGX_MESSAGES \\\n \tM(CGX_LINK_EVENT, 0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp) \\\n \tM(CGX_PTP_RX_INFO, 0xC01, cgx_ptp_rx_info, cgx_ptp_rx_info_msg, msg_rsp)\n \n+#define MBOX_UP_MCS_MESSAGES \\\n+\tM(MCS_INTR_NOTIFY, 0xE00, mcs_intr_notify, mcs_intr_info, msg_rsp)\n+\n enum {\n #define M(_name, _id, _1, _2, _3) MBOX_MSG_##_name = _id,\n-\tMBOX_MESSAGES MBOX_UP_CGX_MESSAGES\n+\tMBOX_MESSAGES MBOX_UP_CGX_MESSAGES MBOX_UP_MCS_MESSAGES\n #undef M\n };\n \n@@ -645,6 +685,321 @@ struct cgx_set_link_mode_rsp {\n \tint __io status;\n };\n \n+/* MCS mbox structures */\n+enum mcs_direction {\n+\tMCS_RX,\n+\tMCS_TX,\n+};\n+\n+enum mcs_rsrc_type {\n+\tMCS_RSRC_TYPE_FLOWID,\n+\tMCS_RSRC_TYPE_SECY,\n+\tMCS_RSRC_TYPE_SC,\n+\tMCS_RSRC_TYPE_SA,\n+};\n+\n+struct mcs_alloc_rsrc_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io rsrc_type;\n+\tuint8_t __io rsrc_cnt; /* Resources count */\n+\tuint8_t __io mcs_id; /* MCS block ID */\n+\tuint8_t __io dir; /* Macsec ingress or egress side */\n+\tuint8_t __io all; /* Allocate all resource type one each */\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_alloc_rsrc_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io flow_ids[128]; /* Index of reserved entries */\n+\tuint8_t __io secy_ids[128];\n+\tuint8_t __io sc_ids[128];\n+\tuint8_t __io sa_ids[256];\n+\tuint8_t __io rsrc_type;\n+\tuint8_t __io rsrc_cnt; /* No of entries reserved */\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint8_t __io all;\n+\tuint8_t __io rsvd[256];\n+};\n+\n+struct mcs_free_rsrc_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io rsrc_id; /* Index of the entry to be freed */\n+\tuint8_t __io rsrc_type;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint8_t __io all; /* Free all the cam resources */\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_flowid_entry_write_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io data[4];\n+\tuint64_t __io mask[4];\n+\tuint64_t __io sci; /* CNF10K-B for tx_secy_mem_map */\n+\tuint8_t __io flow_id;\n+\tuint8_t __io secy_id; /* secyid for which flowid is mapped */\n+\t/* sc_id is Valid if dir = MCS_TX, SC_CAM id mapped to flowid */\n+\tuint8_t __io sc_id;\n+\tuint8_t __io ena; /* Enable tcam entry */\n+\tuint8_t __io ctr_pkt;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_secy_plcy_write_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io plcy;\n+\tuint8_t __io secy_id;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+/* RX SC_CAM mapping */\n+struct mcs_rx_sc_cam_write_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io sci; /* SCI */\n+\tuint64_t __io secy_id; /* secy index mapped to SC */\n+\tuint8_t __io sc_id; /* SC CAM entry index */\n+\tuint8_t __io mcs_id;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_sa_plcy_write_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io plcy[2][9]; /* Support 2 SA policy */\n+\tuint8_t __io sa_index[2];\n+\tuint8_t __io sa_cnt;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_tx_sc_sa_map {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io sa_index0;\n+\tuint8_t __io sa_index1;\n+\tuint8_t __io rekey_ena;\n+\tuint8_t __io sa_index0_vld;\n+\tuint8_t __io sa_index1_vld;\n+\tuint8_t __io tx_sa_active;\n+\tuint64_t __io sectag_sci;\n+\tuint8_t __io sc_id; /* used as index for SA_MEM_MAP */\n+\tuint8_t __io mcs_id;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_rx_sc_sa_map {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io sa_index;\n+\tuint8_t __io sa_in_use;\n+\tuint8_t __io sc_id;\n+\t/* an range is 0-3, sc_id + an used as index SA_MEM_MAP */\n+\tuint8_t __io an;\n+\tuint8_t __io mcs_id;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_flowid_ena_dis_entry {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io flow_id;\n+\tuint8_t __io ena;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_pn_table_write_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io next_pn;\n+\tuint8_t __io pn_id;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_cam_entry_read_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io rsrc_type; /* TCAM/SECY/SC/SA/PN */\n+\tuint8_t __io rsrc_id;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_cam_entry_read_rsp {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io reg_val[10];\n+\tuint8_t __io rsrc_type;\n+\tuint8_t __io rsrc_id;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_hw_info {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io num_mcs_blks; /* Number of MCS blocks */\n+\tuint8_t __io tcam_entries; /* RX/TX Tcam entries per mcs block */\n+\tuint8_t __io secy_entries; /* RX/TX SECY entries per mcs block */\n+\tuint8_t __io sc_entries; /* RX/TX SC CAM entries per mcs block */\n+\tuint8_t __io sa_entries; /* PN table entries = SA entries */\n+\tuint64_t __io rsvd[16];\n+};\n+\n+struct mcs_set_active_lmac {\n+\tstruct mbox_msghdr hdr;\n+\tuint32_t __io lmac_bmap; /* bitmap of active lmac per mcs block */\n+\tuint8_t __io mcs_id;\n+\tuint16_t channel_base; /* MCS channel base */\n+\tuint64_t __io rsvd;\n+};\n+\n+#define MCS_CPM_RX_SECTAG_V_EQ1_INT\t\t BIT_ULL(0)\n+#define MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT\t BIT_ULL(1)\n+#define MCS_CPM_RX_SECTAG_SL_GTE48_INT\t\t BIT_ULL(2)\n+#define MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT\t BIT_ULL(3)\n+#define MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT\t BIT_ULL(4)\n+#define MCS_CPM_RX_PACKET_XPN_EQ0_INT\t\t BIT_ULL(5)\n+#define MCS_CPM_RX_PN_THRESH_REACHED_INT\t BIT_ULL(6)\n+#define MCS_CPM_TX_PACKET_XPN_EQ0_INT\t\t BIT_ULL(7)\n+#define MCS_CPM_TX_PN_THRESH_REACHED_INT\t BIT_ULL(8)\n+#define MCS_CPM_TX_SA_NOT_VALID_INT\t\t BIT_ULL(9)\n+#define MCS_BBE_RX_DFIFO_OVERFLOW_INT\t\t BIT_ULL(10)\n+#define MCS_BBE_RX_PLFIFO_OVERFLOW_INT\t\t BIT_ULL(11)\n+#define MCS_BBE_TX_DFIFO_OVERFLOW_INT\t\t BIT_ULL(12)\n+#define MCS_BBE_TX_PLFIFO_OVERFLOW_INT\t\t BIT_ULL(13)\n+#define MCS_PAB_RX_CHAN_OVERFLOW_INT\t\t BIT_ULL(14)\n+#define MCS_PAB_TX_CHAN_OVERFLOW_INT\t\t BIT_ULL(15)\n+\n+struct mcs_intr_cfg {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io intr_mask; /* Interrupt enable mask */\n+\tuint8_t __io mcs_id;\n+};\n+\n+struct mcs_intr_info {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io intr_mask;\n+\tint __io sa_id;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io lmac_id;\n+\tuint64_t __io rsvd[4];\n+};\n+\n+struct mcs_set_lmac_mode {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */\n+\tuint8_t __io lmac_id;\n+\tuint8_t __io mcs_id;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_stats_req {\n+\tstruct mbox_msghdr hdr;\n+\tuint8_t __io id;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_flowid_stats {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io tcam_hit_cnt;\n+\tuint64_t __io rsvd;\n+};\n+\n+struct mcs_secy_stats {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io ctl_pkt_bcast_cnt;\n+\tuint64_t __io ctl_pkt_mcast_cnt;\n+\tuint64_t __io ctl_pkt_ucast_cnt;\n+\tuint64_t __io ctl_octet_cnt;\n+\tuint64_t __io unctl_pkt_bcast_cnt;\n+\tuint64_t __io unctl_pkt_mcast_cnt;\n+\tuint64_t __io unctl_pkt_ucast_cnt;\n+\tuint64_t __io unctl_octet_cnt;\n+\t/* Valid only for RX */\n+\tuint64_t __io octet_decrypted_cnt;\n+\tuint64_t __io octet_validated_cnt;\n+\tuint64_t __io pkt_port_disabled_cnt;\n+\tuint64_t __io pkt_badtag_cnt;\n+\tuint64_t __io pkt_nosa_cnt;\n+\tuint64_t __io pkt_nosaerror_cnt;\n+\tuint64_t __io pkt_tagged_ctl_cnt;\n+\tuint64_t __io pkt_untaged_cnt;\n+\tuint64_t __io pkt_ctl_cnt; /* CN10K-B */\n+\tuint64_t __io pkt_notag_cnt; /* CNF10K-B */\n+\t/* Valid only for TX */\n+\tuint64_t __io octet_encrypted_cnt;\n+\tuint64_t __io octet_protected_cnt;\n+\tuint64_t __io pkt_noactivesa_cnt;\n+\tuint64_t __io pkt_toolong_cnt;\n+\tuint64_t __io pkt_untagged_cnt;\n+\tuint64_t __io rsvd[4];\n+};\n+\n+struct mcs_port_stats {\n+\tstruct mbox_msghdr hdr;\n+\tuint64_t __io tcam_miss_cnt;\n+\tuint64_t __io parser_err_cnt;\n+\tuint64_t __io preempt_err_cnt; /* CNF10K-B */\n+\tuint64_t __io sectag_insert_err_cnt;\n+\tuint64_t __io rsvd[4];\n+};\n+\n+/* Only for CN10K-B */\n+struct mcs_sa_stats {\n+\tstruct mbox_msghdr hdr;\n+\t/* RX */\n+\tuint64_t __io pkt_invalid_cnt;\n+\tuint64_t __io pkt_nosaerror_cnt;\n+\tuint64_t __io pkt_notvalid_cnt;\n+\tuint64_t __io pkt_ok_cnt;\n+\tuint64_t __io pkt_nosa_cnt;\n+\t/* TX */\n+\tuint64_t __io pkt_encrypt_cnt;\n+\tuint64_t __io pkt_protected_cnt;\n+\tuint64_t __io rsvd[4];\n+};\n+\n+struct mcs_sc_stats {\n+\tstruct mbox_msghdr hdr;\n+\t/* RX */\n+\tuint64_t __io hit_cnt;\n+\tuint64_t __io pkt_invalid_cnt;\n+\tuint64_t __io pkt_late_cnt;\n+\tuint64_t __io pkt_notvalid_cnt;\n+\tuint64_t __io pkt_unchecked_cnt;\n+\tuint64_t __io pkt_delay_cnt;\t /* CNF10K-B */\n+\tuint64_t __io pkt_ok_cnt;\t /* CNF10K-B */\n+\tuint64_t __io octet_decrypt_cnt; /* CN10K-B */\n+\tuint64_t __io octet_validate_cnt; /* CN10K-B */\n+\t/* TX */\n+\tuint64_t __io pkt_encrypt_cnt;\n+\tuint64_t __io pkt_protected_cnt;\n+\tuint64_t __io octet_encrypt_cnt; /* CN10K-B */\n+\tuint64_t __io octet_protected_cnt; /* CN10K-B */\n+\tuint64_t __io rsvd[4];\n+};\n+\n+struct mcs_clear_stats {\n+\tstruct mbox_msghdr hdr;\n+#define MCS_FLOWID_STATS 0\n+#define MCS_SECY_STATS\t1\n+#define MCS_SC_STATS\t2\n+#define MCS_SA_STATS\t3\n+#define MCS_PORT_STATS\t4\n+\tuint8_t __io type; /* FLOWID, SECY, SC, SA, PORT */\n+\t/* type = PORT, If id = FF(invalid) port no is derived from pcifunc */\n+\tuint8_t __io id;\n+\tuint8_t __io mcs_id;\n+\tuint8_t __io dir;\n+\tuint8_t __io all; /* All resources stats mapped to PF are cleared */\n+};\n+\n /* NPA mbox message formats */\n \n /* NPA mailbox error codes\ndiff --git a/drivers/common/cnxk/roc_mcs.c b/drivers/common/cnxk/roc_mcs.c\nnew file mode 100644\nindex 0000000000..769f74a512\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_mcs.c\n@@ -0,0 +1,347 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2022 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+struct mcs_event_cb {\n+\tTAILQ_ENTRY(mcs_event_cb) next;\n+\tenum roc_mcs_event_type event;\n+\troc_mcs_dev_cb_fn cb_fn;\n+\tvoid *cb_arg;\n+\tvoid *ret_param;\n+\tuint32_t active;\n+};\n+TAILQ_HEAD(mcs_event_cb_list, mcs_event_cb);\n+\n+PLT_STATIC_ASSERT(ROC_MCS_MEM_SZ >= (sizeof(struct mcs_priv) + sizeof(struct mcs_event_cb_list)));\n+\n+TAILQ_HEAD(roc_mcs_head, roc_mcs);\n+/* Local mcs tailq list */\n+static struct roc_mcs_head roc_mcs_head = TAILQ_HEAD_INITIALIZER(roc_mcs_head);\n+\n+int\n+roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info)\n+{\n+\tstruct mcs_hw_info *hw;\n+\tstruct npa_lf *npa;\n+\tint rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (hw_info == NULL)\n+\t\treturn -EINVAL;\n+\n+\t/* Use mbox handler of first probed pci_func for\n+\t * initial mcs mbox communication.\n+\t */\n+\tnpa = idev_npa_obj_get();\n+\tif (!npa)\n+\t\treturn MCS_ERR_DEVICE_NOT_FOUND;\n+\n+\tmbox_alloc_msg_mcs_get_hw_info(npa->mbox);\n+\trc = mbox_process_msg(npa->mbox, (void *)&hw);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\thw_info->num_mcs_blks = hw->num_mcs_blks;\n+\thw_info->tcam_entries = hw->tcam_entries;\n+\thw_info->secy_entries = hw->secy_entries;\n+\thw_info->sc_entries = hw->sc_entries;\n+\thw_info->sa_entries = hw->sa_entries;\n+\n+\treturn rc;\n+}\n+\n+int\n+roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_active_lmac *lmac)\n+{\n+\tstruct mcs_set_active_lmac *req;\n+\tstruct msg_rsp *rsp;\n+\n+\t/* Only needed for 105N */\n+\tif (!roc_model_is_cnf10kb())\n+\t\treturn 0;\n+\n+\tif (lmac == NULL)\n+\t\treturn -EINVAL;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\treq = mbox_alloc_msg_mcs_set_active_lmac(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\treq->lmac_bmap = lmac->lmac_bmap;\n+\treq->channel_base = lmac->channel_base;\n+\treq->mcs_id = mcs->idx;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port)\n+{\n+\tstruct mcs_set_lmac_mode *req;\n+\tstruct msg_rsp *rsp;\n+\n+\tif (port == NULL)\n+\t\treturn -EINVAL;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\treq = mbox_alloc_msg_mcs_set_lmac_mode(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\treq->lmac_id = port->lmac_id;\n+\treq->mcs_id = mcs->idx;\n+\treq->mode = port->mode;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config)\n+{\n+\tstruct mcs_intr_cfg *req;\n+\tstruct msg_rsp *rsp;\n+\n+\tif (config == NULL)\n+\t\treturn -EINVAL;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\treq = mbox_alloc_msg_mcs_intr_cfg(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\treq->intr_mask = config->intr_mask;\n+\treq->mcs_id = mcs->idx;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_event_cb_register(struct roc_mcs *mcs, enum roc_mcs_event_type event,\n+\t\t\t roc_mcs_dev_cb_fn cb_fn, void *cb_arg, void *userdata)\n+{\n+\tstruct mcs_event_cb_list *cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs);\n+\tstruct mcs_event_cb *cb;\n+\n+\tif (cb_fn == NULL || cb_arg == NULL || userdata == NULL)\n+\t\treturn -EINVAL;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tTAILQ_FOREACH(cb, cb_list, next) {\n+\t\tif (cb->cb_fn == cb_fn && cb->cb_arg == cb_arg && cb->event == event)\n+\t\t\tbreak;\n+\t}\n+\n+\tif (cb == NULL) {\n+\t\tcb = plt_zmalloc(sizeof(struct mcs_event_cb), 0);\n+\t\tif (!cb)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tcb->cb_fn = cb_fn;\n+\t\tcb->cb_arg = cb_arg;\n+\t\tcb->event = event;\n+\t\tmcs->userdata = userdata;\n+\t\tTAILQ_INSERT_TAIL(cb_list, cb, next);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_mcs_event_cb_unregister(struct roc_mcs *mcs, enum roc_mcs_event_type event)\n+{\n+\tstruct mcs_event_cb_list *cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs);\n+\tstruct mcs_event_cb *cb, *next;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tfor (cb = TAILQ_FIRST(cb_list); cb != NULL; cb = next) {\n+\t\tnext = TAILQ_NEXT(cb, next);\n+\n+\t\tif (cb->event != event)\n+\t\t\tcontinue;\n+\n+\t\tif (cb->active == 0) {\n+\t\t\tTAILQ_REMOVE(cb_list, cb, next);\n+\t\t\tplt_free(cb);\n+\t\t} else {\n+\t\t\treturn -EAGAIN;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+mcs_event_cb_process(struct roc_mcs *mcs, struct roc_mcs_event_desc *desc)\n+{\n+\tstruct mcs_event_cb_list *cb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs);\n+\tstruct mcs_event_cb mcs_cb;\n+\tstruct mcs_event_cb *cb;\n+\tint rc = 0;\n+\n+\tTAILQ_FOREACH(cb, cb_list, next) {\n+\t\tif (cb->cb_fn == NULL || cb->event != desc->type)\n+\t\t\tcontinue;\n+\n+\t\tmcs_cb = *cb;\n+\t\tcb->active = 1;\n+\t\tmcs_cb.ret_param = desc;\n+\n+\t\trc = mcs_cb.cb_fn(mcs->userdata, mcs_cb.ret_param, mcs_cb.cb_arg);\n+\t\tcb->active = 0;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static int\n+mcs_alloc_bmap(uint16_t entries, void **mem, struct plt_bitmap **bmap)\n+{\n+\tsize_t bmap_sz;\n+\tint rc = 0;\n+\n+\tbmap_sz = plt_bitmap_get_memory_footprint(entries);\n+\t*mem = plt_zmalloc(bmap_sz, PLT_CACHE_LINE_SIZE);\n+\tif (*mem == NULL)\n+\t\trc = -ENOMEM;\n+\n+\t*bmap = plt_bitmap_init(entries, *mem, bmap_sz);\n+\tif (!*bmap) {\n+\t\tplt_free(*mem);\n+\t\t*mem = NULL;\n+\t\trc = -ENOMEM;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+static int\n+mcs_alloc_rsrc_bmap(struct roc_mcs *mcs)\n+{\n+\tstruct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);\n+\tstruct mcs_hw_info *hw;\n+\tint rc;\n+\n+\tmbox_alloc_msg_mcs_get_hw_info(mcs->mbox);\n+\trc = mbox_process_msg(mcs->mbox, (void *)&hw);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tpriv->num_mcs_blks = hw->num_mcs_blks;\n+\tpriv->tcam_entries = hw->tcam_entries;\n+\tpriv->secy_entries = hw->secy_entries;\n+\tpriv->sc_entries = hw->sc_entries;\n+\tpriv->sa_entries = hw->sa_entries;\n+\n+\t/* Allocate double the resources to accommodate both Tx & Rx */\n+\trc = mcs_alloc_bmap(priv->tcam_entries << 1, &priv->tcam_bmap_mem, &priv->tcam_bmap);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\trc = mcs_alloc_bmap(priv->secy_entries << 1, &priv->secy_bmap_mem, &priv->secy_bmap);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\trc = mcs_alloc_bmap(priv->sc_entries << 1, &priv->sc_bmap_mem, &priv->sc_bmap);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\trc = mcs_alloc_bmap(priv->sa_entries << 1, &priv->sa_bmap_mem, &priv->sa_bmap);\n+\tif (rc)\n+\t\tgoto exit;\n+\n+\treturn rc;\n+\n+exit:\n+\tplt_bitmap_free(priv->tcam_bmap);\n+\tplt_free(priv->tcam_bmap_mem);\n+\tplt_bitmap_free(priv->secy_bmap);\n+\tplt_free(priv->secy_bmap_mem);\n+\tplt_bitmap_free(priv->sc_bmap);\n+\tplt_free(priv->sc_bmap_mem);\n+\tplt_bitmap_free(priv->sa_bmap);\n+\tplt_free(priv->sa_bmap_mem);\n+\n+\treturn rc;\n+}\n+\n+struct roc_mcs *\n+roc_mcs_dev_get(uint8_t mcs_idx)\n+{\n+\tstruct roc_mcs *mcs = NULL;\n+\n+\tTAILQ_FOREACH (mcs, &roc_mcs_head, next) {\n+\t\tif (mcs->idx == mcs_idx)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn mcs;\n+}\n+\n+struct roc_mcs *\n+roc_mcs_dev_init(uint8_t mcs_idx)\n+{\n+\tstruct mcs_event_cb_list *cb_list;\n+\tstruct roc_mcs *mcs;\n+\tstruct npa_lf *npa;\n+\n+\tmcs = plt_zmalloc(sizeof(struct roc_mcs), PLT_CACHE_LINE_SIZE);\n+\tif (!mcs)\n+\t\treturn NULL;\n+\n+\tif (roc_model_is_cnf10kb()) {\n+\t\tnpa = idev_npa_obj_get();\n+\t\tif (!npa)\n+\t\t\tgoto exit;\n+\n+\t\tmcs->mbox = npa->mbox;\n+\t} else {\n+\t\t/* Retrieve mbox handler for other roc models */\n+\t\t;\n+\t}\n+\n+\tmcs->idx = mcs_idx;\n+\n+\t/* Add any per mcsv initialization */\n+\tif (mcs_alloc_rsrc_bmap(mcs))\n+\t\tgoto exit;\n+\n+\tTAILQ_INSERT_TAIL(&roc_mcs_head, mcs, next);\n+\n+\tcb_list = (struct mcs_event_cb_list *)roc_mcs_to_mcs_cb_list(mcs);\n+\tTAILQ_INIT(cb_list);\n+\n+\treturn mcs;\n+\n+exit:\n+\tplt_free(mcs);\n+\treturn NULL;\n+}\n+\n+void\n+roc_mcs_dev_fini(struct roc_mcs *mcs)\n+{\n+\tstruct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);\n+\n+\tTAILQ_REMOVE(&roc_mcs_head, mcs, next);\n+\n+\tplt_bitmap_free(priv->tcam_bmap);\n+\tplt_free(priv->tcam_bmap_mem);\n+\tplt_bitmap_free(priv->secy_bmap);\n+\tplt_free(priv->secy_bmap_mem);\n+\tplt_bitmap_free(priv->sc_bmap);\n+\tplt_free(priv->sc_bmap_mem);\n+\tplt_bitmap_free(priv->sa_bmap);\n+\tplt_free(priv->sa_bmap_mem);\n+\n+\tplt_free(mcs);\n+}\ndiff --git a/drivers/common/cnxk/roc_mcs.h b/drivers/common/cnxk/roc_mcs.h\nnew file mode 100644\nindex 0000000000..f2c8b3ae06\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_mcs.h\n@@ -0,0 +1,431 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2022 Marvell.\n+ */\n+\n+#ifndef _ROC_MCS_H_\n+#define _ROC_MCS_H_\n+\n+struct roc_mcs_alloc_rsrc_req {\n+\tuint8_t rsrc_type;\n+\tuint8_t rsrc_cnt; /* Resources count */\n+\tuint8_t mcs_id;\t /* MCS block ID */\n+\tuint8_t dir;\t /* Macsec ingress or egress side */\n+\tuint8_t all;\t /* Allocate all resource type one each */\n+};\n+\n+struct roc_mcs_alloc_rsrc_rsp {\n+\tuint8_t flow_ids[128]; /* Index of reserved entries */\n+\tuint8_t secy_ids[128];\n+\tuint8_t sc_ids[128];\n+\tuint8_t sa_ids[256];\n+\tuint8_t rsrc_type;\n+\tuint8_t rsrc_cnt; /* No of entries reserved */\n+\tuint8_t mcs_id;\n+\tuint8_t dir;\n+\tuint8_t all;\n+};\n+\n+struct roc_mcs_free_rsrc_req {\n+\tuint8_t rsrc_id; /* Index of the entry to be freed */\n+\tuint8_t rsrc_type;\n+\tuint8_t mcs_id;\n+\tuint8_t dir;\n+\tuint8_t all; /* Free all the cam resources */\n+};\n+\n+struct roc_mcs_flowid_entry_write_req {\n+\tuint64_t data[4];\n+\tuint64_t mask[4];\n+\tuint64_t sci; /* 105N for tx_secy_mem_map */\n+\tuint8_t flow_id;\n+\tuint8_t secy_id; /* secyid for which flowid is mapped */\n+\tuint8_t sc_id;\t /* Valid if dir = MCS_TX, SC_CAM id mapped to flowid */\n+\tuint8_t ena;\t /* Enable tcam entry */\n+\tuint8_t ctr_pkt;\n+\tuint8_t mcs_id;\n+\tuint8_t dir;\n+};\n+\n+struct roc_mcs_secy_plcy_write_req {\n+\tuint64_t plcy;\n+\tuint8_t secy_id;\n+\tuint8_t mcs_id;\n+\tuint8_t dir;\n+};\n+\n+/* RX SC_CAM mapping */\n+struct roc_mcs_rx_sc_cam_write_req {\n+\tuint64_t sci;\t /* SCI */\n+\tuint64_t secy_id; /* secy index mapped to SC */\n+\tuint8_t sc_id;\t /* SC CAM entry index */\n+\tuint8_t mcs_id;\n+};\n+\n+struct roc_mcs_sa_plcy_write_req {\n+\tuint64_t plcy[2][9];\n+\tuint8_t sa_index[2];\n+\tuint8_t sa_cnt;\n+\tuint8_t mcs_id;\n+\tuint8_t dir;\n+};\n+\n+struct roc_mcs_tx_sc_sa_map {\n+\tuint8_t sa_index0;\n+\tuint8_t sa_index1;\n+\tuint8_t rekey_ena;\n+\tuint8_t sa_index0_vld;\n+\tuint8_t sa_index1_vld;\n+\tuint8_t tx_sa_active;\n+\tuint64_t sectag_sci;\n+\tuint8_t sc_id; /* used as index for SA_MEM_MAP */\n+\tuint8_t mcs_id;\n+};\n+\n+struct roc_mcs_rx_sc_sa_map {\n+\tuint8_t sa_index;\n+\tuint8_t sa_in_use;\n+\tuint8_t sc_id;\n+\tuint8_t an; /* value range 0-3, sc_id + an used as index SA_MEM_MAP */\n+\tuint8_t mcs_id;\n+};\n+\n+struct roc_mcs_flowid_ena_dis_entry {\n+\tuint8_t flow_id;\n+\tuint8_t ena;\n+\tuint8_t mcs_id;\n+\tuint8_t dir;\n+};\n+\n+struct roc_mcs_pn_table_write_req {\n+\tuint64_t next_pn;\n+\tuint8_t pn_id;\n+\tuint8_t mcs_id;\n+\tuint8_t dir;\n+};\n+\n+struct roc_mcs_cam_entry_read_req {\n+\tuint8_t rsrc_type; /* TCAM/SECY/SC/SA/PN */\n+\tuint8_t rsrc_id;\n+\tuint8_t mcs_id;\n+\tuint8_t dir;\n+};\n+\n+struct roc_mcs_cam_entry_read_rsp {\n+\tuint64_t reg_val[10];\n+\tuint8_t rsrc_type;\n+\tuint8_t rsrc_id;\n+\tuint8_t mcs_id;\n+\tuint8_t dir;\n+};\n+\n+struct roc_mcs_hw_info {\n+\tuint8_t num_mcs_blks; /* Number of MCS blocks */\n+\tuint8_t tcam_entries; /* RX/TX Tcam entries per mcs block */\n+\tuint8_t secy_entries; /* RX/TX SECY entries per mcs block */\n+\tuint8_t sc_entries; /* RX/TX SC CAM entries per mcs block */\n+\tuint8_t sa_entries; /* PN table entries = SA entries */\n+\tuint64_t rsvd[16];\n+};\n+\n+#define ROC_MCS_CPM_RX_SECTAG_V_EQ1_INT\t\t BIT_ULL(0)\n+#define ROC_MCS_CPM_RX_SECTAG_E_EQ0_C_EQ1_INT\t BIT_ULL(1)\n+#define ROC_MCS_CPM_RX_SECTAG_SL_GTE48_INT\t BIT_ULL(2)\n+#define ROC_MCS_CPM_RX_SECTAG_ES_EQ1_SC_EQ1_INT\t BIT_ULL(3)\n+#define ROC_MCS_CPM_RX_SECTAG_SC_EQ1_SCB_EQ1_INT BIT_ULL(4)\n+#define ROC_MCS_CPM_RX_PACKET_XPN_EQ0_INT\t BIT_ULL(5)\n+#define ROC_MCS_CPM_RX_PN_THRESH_REACHED_INT\t BIT_ULL(6)\n+#define ROC_MCS_CPM_TX_PACKET_XPN_EQ0_INT\t BIT_ULL(7)\n+#define ROC_MCS_CPM_TX_PN_THRESH_REACHED_INT\t BIT_ULL(8)\n+#define ROC_MCS_CPM_TX_SA_NOT_VALID_INT\t\t BIT_ULL(9)\n+#define ROC_MCS_BBE_RX_DFIFO_OVERFLOW_INT\t BIT_ULL(10)\n+#define ROC_MCS_BBE_RX_PLFIFO_OVERFLOW_INT\t BIT_ULL(11)\n+#define ROC_MCS_BBE_TX_DFIFO_OVERFLOW_INT\t BIT_ULL(12)\n+#define ROC_MCS_BBE_TX_PLFIFO_OVERFLOW_INT\t BIT_ULL(13)\n+#define ROC_MCS_PAB_RX_CHAN_OVERFLOW_INT\t BIT_ULL(14)\n+#define ROC_MCS_PAB_TX_CHAN_OVERFLOW_INT\t BIT_ULL(15)\n+\n+struct roc_mcs_intr_cfg {\n+\tuint64_t intr_mask; /* Interrupt enable mask */\n+\tuint8_t mcs_id;\n+};\n+\n+struct roc_mcs_intr_info {\n+\tuint64_t intr_mask;\n+\tint sa_id;\n+\tuint8_t mcs_id;\n+\tuint8_t lmac_id;\n+\tuint64_t rsvd[4];\n+};\n+\n+struct roc_mcs_set_lmac_mode {\n+\tuint8_t mode; /* '1' for internal bypass mode (passthrough), '0' for MCS processing */\n+\tuint8_t lmac_id;\n+\tuint8_t mcs_id;\n+\tuint64_t rsvd;\n+};\n+\n+struct roc_mcs_set_active_lmac {\n+\tuint32_t lmac_bmap; /* bitmap of active lmac per mcs block */\n+\tuint8_t mcs_id;\n+\tuint16_t channel_base; /* MCS channel base */\n+\tuint64_t rsvd;\n+};\n+\n+struct roc_mcs_stats_req {\n+\tuint8_t id;\n+\tuint8_t mcs_id;\n+\tuint8_t dir;\n+};\n+\n+struct roc_mcs_flowid_stats {\n+\tuint64_t tcam_hit_cnt;\n+};\n+\n+struct roc_mcs_secy_stats {\n+\tuint64_t ctl_pkt_bcast_cnt;\n+\tuint64_t ctl_pkt_mcast_cnt;\n+\tuint64_t ctl_pkt_ucast_cnt;\n+\tuint64_t ctl_octet_cnt;\n+\tuint64_t unctl_pkt_bcast_cnt;\n+\tuint64_t unctl_pkt_mcast_cnt;\n+\tuint64_t unctl_pkt_ucast_cnt;\n+\tuint64_t unctl_octet_cnt;\n+\t/* Valid only for RX */\n+\tuint64_t octet_decrypted_cnt;\n+\tuint64_t octet_validated_cnt;\n+\tuint64_t pkt_port_disabled_cnt;\n+\tuint64_t pkt_badtag_cnt;\n+\tuint64_t pkt_nosa_cnt;\n+\tuint64_t pkt_nosaerror_cnt;\n+\tuint64_t pkt_tagged_ctl_cnt;\n+\tuint64_t pkt_untaged_cnt;\n+\tuint64_t pkt_ctl_cnt;\t/* CN10K-B */\n+\tuint64_t pkt_notag_cnt; /* CNF10K-B */\n+\t/* Valid only for TX */\n+\tuint64_t octet_encrypted_cnt;\n+\tuint64_t octet_protected_cnt;\n+\tuint64_t pkt_noactivesa_cnt;\n+\tuint64_t pkt_toolong_cnt;\n+\tuint64_t pkt_untagged_cnt;\n+};\n+\n+struct roc_mcs_sc_stats {\n+\t/* RX */\n+\tuint64_t hit_cnt;\n+\tuint64_t pkt_invalid_cnt;\n+\tuint64_t pkt_late_cnt;\n+\tuint64_t pkt_notvalid_cnt;\n+\tuint64_t pkt_unchecked_cnt;\n+\tuint64_t pkt_delay_cnt;\t /* CNF10K-B */\n+\tuint64_t pkt_ok_cnt;\t /* CNF10K-B */\n+\tuint64_t octet_decrypt_cnt; /* CN10K-B */\n+\tuint64_t octet_validate_cnt; /* CN10K-B */\n+\t/* TX */\n+\tuint64_t pkt_encrypt_cnt;\n+\tuint64_t pkt_protected_cnt;\n+\tuint64_t octet_encrypt_cnt; /* CN10K-B */\n+\tuint64_t octet_protected_cnt; /* CN10K-B */\n+};\n+\n+/* Only for CN10K-B */\n+struct roc_mcs_sa_stats {\n+\t/* RX */\n+\tuint64_t pkt_invalid_cnt;\n+\tuint64_t pkt_nosaerror_cnt;\n+\tuint64_t pkt_notvalid_cnt;\n+\tuint64_t pkt_ok_cnt;\n+\tuint64_t pkt_nosa_cnt;\n+\t/* TX */\n+\tuint64_t pkt_encrypt_cnt;\n+\tuint64_t pkt_protected_cnt;\n+};\n+\n+struct roc_mcs_port_stats {\n+\tuint64_t tcam_miss_cnt;\n+\tuint64_t parser_err_cnt;\n+\tuint64_t preempt_err_cnt; /* CNF10K-B */\n+\tuint64_t sectag_insert_err_cnt;\n+};\n+\n+struct roc_mcs_clear_stats {\n+\tuint8_t type; /* FLOWID, SECY, SC, SA, PORT */\n+\t/* type = PORT, If id = FF(invalid) port no is derived from pcifunc */\n+\tuint8_t id;\n+\tuint8_t mcs_id;\n+\tuint8_t dir;\n+\tuint8_t all; /* All resources stats mapped to PF are cleared */\n+};\n+\n+enum roc_mcs_event_subtype {\n+\tROC_MCS_SUBEVENT_UNKNOWN,\n+\n+\t/* subevents of ROC_MCS_EVENT_SECTAG_VAL_ERR sectag validation events\n+\t * ROC_MCS_EVENT_RX_SECTAG_V_EQ1\n+\t *\tValidation check: SecTag.TCI.V = 1\n+\t * ROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1\n+\t *\tValidation check: SecTag.TCI.E = 0 && SecTag.TCI.C = 1\n+\t * ROC_MCS_EVENT_RX_SECTAG_SL_GTE48\n+\t *\tValidation check: SecTag.SL >= 'd48\n+\t * ROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1\n+\t *\tValidation check: SecTag.TCI.ES = 1 && SecTag.TCI.SC = 1\n+\t * ROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1\n+\t *\tValidation check: SecTag.TCI.SC = 1 && SecTag.TCI.SCB = 1\n+\t */\n+\tROC_MCS_EVENT_RX_SECTAG_V_EQ1,\n+\tROC_MCS_EVENT_RX_SECTAG_E_EQ0_C_EQ1,\n+\tROC_MCS_EVENT_RX_SECTAG_SL_GTE48,\n+\tROC_MCS_EVENT_RX_SECTAG_ES_EQ1_SC_EQ1,\n+\tROC_MCS_EVENT_RX_SECTAG_SC_EQ1_SCB_EQ1,\n+\n+\t/* subevents of ROC_MCS_EVENT_FIFO_OVERFLOW error event\n+\t * ROC_MCS_EVENT_DATA_FIFO_OVERFLOW:\n+\t *\tNotifies data FIFO overflow fatal error in BBE unit.\n+\t * ROC_MCS_EVENT_POLICY_FIFO_OVERFLOW\n+\t *\tNotifies policy FIFO overflow fatal error in BBE unit.\n+\t * ROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW,\n+\t *\tNotifies output FIFO overflow fatal error in PAB unit.\n+\t */\n+\tROC_MCS_EVENT_DATA_FIFO_OVERFLOW,\n+\tROC_MCS_EVENT_POLICY_FIFO_OVERFLOW,\n+\tROC_MCS_EVENT_PKT_ASSM_FIFO_OVERFLOW,\n+};\n+\n+enum roc_mcs_event_type {\n+\tROC_MCS_EVENT_UNKNOWN,\n+\n+\t/* Notifies BBE_INT_DFIFO/PLFIFO_OVERFLOW or PAB_INT_OVERFLOW\n+\t * interrupts, it's a fatal error that causes packet corruption.\n+\t */\n+\tROC_MCS_EVENT_FIFO_OVERFLOW,\n+\n+\t/* Notifies CPM_RX_SECTAG_X validation error interrupt */\n+\tROC_MCS_EVENT_SECTAG_VAL_ERR,\n+\t/* Notifies CPM_RX_PACKET_XPN_EQ0 (SecTag.PN == 0 in ingress) interrupt */\n+\tROC_MCS_EVENT_RX_SA_PN_HARD_EXP,\n+\t/* Notifies CPM_RX_PN_THRESH_REACHED interrupt */\n+\tROC_MCS_EVENT_RX_SA_PN_SOFT_EXP,\n+\t/* Notifies CPM_TX_PACKET_XPN_EQ0 (PN wrapped in egress) interrupt */\n+\tROC_MCS_EVENT_TX_SA_PN_HARD_EXP,\n+\t/* Notifies CPM_TX_PN_THRESH_REACHED interrupt */\n+\tROC_MCS_EVENT_TX_SA_PN_SOFT_EXP,\n+\t/* Notifies CPM_TX_SA_NOT_VALID interrupt */\n+\tROC_MCS_EVENT_SA_NOT_VALID,\n+};\n+\n+union roc_mcs_event_data {\n+\t/* Valid for below events\n+\t * - ROC_MCS_EVENT_RX_SA_PN_SOFT_EXP\n+\t * - ROC_MCS_EVENT_TX_SA_PN_SOFT_EXP\n+\t */\n+\tstruct {\n+\t\tuint8_t secy_idx;\n+\t\tuint8_t sc_idx;\n+\t\tuint8_t sa_idx;\n+\t\tuint8_t lmac_id;\n+\t};\n+};\n+\n+struct roc_mcs_event_desc {\n+\tenum roc_mcs_event_type type;\n+\tenum roc_mcs_event_subtype subtype;\n+\tunion roc_mcs_event_data metadata;\n+};\n+\n+/** User application callback to be registered for any notifications from\n+ * driver. */\n+typedef int (*roc_mcs_dev_cb_fn)(void *userdata, struct roc_mcs_event_desc *desc, void *cb_arg);\n+\n+struct roc_mcs {\n+\tTAILQ_ENTRY(roc_mcs) next;\n+\tstruct plt_pci_device *pci_dev;\n+\tstruct mbox *mbox;\n+\tvoid *userdata;\n+\tuint8_t idx;\n+\n+#define ROC_MCS_MEM_SZ (1 * 1024)\n+\tuint8_t reserved[ROC_MCS_MEM_SZ] __plt_cache_aligned;\n+} __plt_cache_aligned;\n+\n+/* Initialization */\n+__roc_api struct roc_mcs *roc_mcs_dev_init(uint8_t mcs_idx);\n+__roc_api void roc_mcs_dev_fini(struct roc_mcs *mcs);\n+/* Get roc mcs dev structure */\n+__roc_api struct roc_mcs *roc_mcs_dev_get(uint8_t mcs_idx);\n+/* HW info get */\n+__roc_api int roc_mcs_hw_info_get(struct roc_mcs_hw_info *hw_info);\n+/* Active lmac bmap set */\n+__roc_api int roc_mcs_active_lmac_set(struct roc_mcs *mcs, struct roc_mcs_set_active_lmac *lmac);\n+/* Port bypass mode set */\n+__roc_api int roc_mcs_lmac_mode_set(struct roc_mcs *mcs, struct roc_mcs_set_lmac_mode *port);\n+\n+/* Resource allocation and free */\n+__roc_api int roc_mcs_alloc_rsrc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req,\n+\t\t\t\t struct roc_mcs_alloc_rsrc_rsp *rsp);\n+__roc_api int roc_mcs_free_rsrc(struct roc_mcs *mcs, struct roc_mcs_free_rsrc_req *req);\n+/* SA policy read and write */\n+__roc_api int roc_mcs_sa_policy_write(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_sa_plcy_write_req *sa_plcy);\n+__roc_api int roc_mcs_sa_policy_read(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_sa_plcy_write_req *sa_plcy);\n+/* PN Table read and write */\n+__roc_api int roc_mcs_pn_table_write(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_pn_table_write_req *pn_table);\n+__roc_api int roc_mcs_pn_table_read(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_pn_table_write_req *pn_table);\n+/* RX SC read, write and enable */\n+__roc_api int roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);\n+__roc_api int roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);\n+__roc_api int roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);\n+/* SECY policy read and write */\n+__roc_api int roc_mcs_secy_policy_write(struct roc_mcs *mcs,\n+\t\t\t\t\tstruct roc_mcs_secy_plcy_write_req *secy_plcy);\n+__roc_api int roc_mcs_secy_policy_read(struct roc_mcs *mcs,\n+\t\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam);\n+/* RX SC-SA MAP read and write */\n+__roc_api int roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs,\n+\t\t\t\t\t struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map);\n+__roc_api int roc_mcs_rx_sc_sa_map_read(struct roc_mcs *mcs,\n+\t\t\t\t\tstruct roc_mcs_rx_sc_sa_map *rx_sc_sa_map);\n+/* TX SC-SA MAP read and write */\n+__roc_api int roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs,\n+\t\t\t\t\t struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map);\n+__roc_api int roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs,\n+\t\t\t\t\tstruct roc_mcs_tx_sc_sa_map *tx_sc_sa_map);\n+/* Flow entry read, write and enable */\n+__roc_api int roc_mcs_flowid_entry_write(struct roc_mcs *mcs,\n+\t\t\t\t\t struct roc_mcs_flowid_entry_write_req *flowid_req);\n+__roc_api int roc_mcs_flowid_entry_read(struct roc_mcs *mcs,\n+\t\t\t\t\tstruct roc_mcs_flowid_entry_write_req *flowid_rsp);\n+__roc_api int roc_mcs_flowid_entry_enable(struct roc_mcs *mcs,\n+\t\t\t\t\t struct roc_mcs_flowid_ena_dis_entry *entry);\n+\n+/* Flow id stats get */\n+__roc_api int roc_mcs_flowid_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,\n+\t\t\t\t struct roc_mcs_flowid_stats *stats);\n+/* Secy stats get */\n+__roc_api int roc_mcs_secy_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,\n+\t\t\t\t struct roc_mcs_secy_stats *stats);\n+/* SC stats get */\n+__roc_api int roc_mcs_sc_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,\n+\t\t\t\t struct roc_mcs_sc_stats *stats);\n+/* SA stats get */\n+__roc_api int roc_mcs_sa_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,\n+\t\t\t\t struct roc_mcs_sa_stats *stats);\n+/* Port stats get */\n+__roc_api int roc_mcs_port_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,\n+\t\t\t\t struct roc_mcs_port_stats *stats);\n+/* Clear stats */\n+__roc_api int roc_mcs_stats_clear(struct roc_mcs *mcs, struct roc_mcs_clear_stats *mcs_req);\n+\n+/* Register user callback routines */\n+__roc_api int roc_mcs_event_cb_register(struct roc_mcs *mcs, enum roc_mcs_event_type event,\n+\t\t\t\t\troc_mcs_dev_cb_fn cb_fn, void *cb_arg, void *userdata);\n+/* Unregister user callback routines */\n+__roc_api int roc_mcs_event_cb_unregister(struct roc_mcs *mcs, enum roc_mcs_event_type event);\n+\n+/* Configure interrupts */\n+__roc_api int roc_mcs_intr_configure(struct roc_mcs *mcs, struct roc_mcs_intr_cfg *config);\n+#endif /* _ROC_MCS_H_ */\ndiff --git a/drivers/common/cnxk/roc_mcs_priv.h b/drivers/common/cnxk/roc_mcs_priv.h\nnew file mode 100644\nindex 0000000000..c5199d3722\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_mcs_priv.h\n@@ -0,0 +1,52 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2022 Marvell.\n+ */\n+\n+#ifndef _ROC_MCS_PRIV_H_\n+#define _ROC_MCS_PRIV_H_\n+\n+enum mcs_error_status {\n+\tMCS_ERR_PARAM = -900,\n+\tMCS_ERR_HW_NOTSUP = -901,\n+\tMCS_ERR_DEVICE_NOT_FOUND = -902,\n+};\n+\n+#define MCS_SUPPORT_CHECK \\\n+\tdo { \\\n+\t\tif (!(roc_model_is_cnf10kb() || roc_model_is_cn10kb_a0())) \\\n+\t\t\treturn MCS_ERR_HW_NOTSUP; \\\n+\t} while (0)\n+\n+struct mcs_priv {\n+\tstruct plt_bitmap *tcam_bmap;\n+\tvoid *tcam_bmap_mem;\n+\tstruct plt_bitmap *secy_bmap;\n+\tvoid *secy_bmap_mem;\n+\tstruct plt_bitmap *sc_bmap;\n+\tvoid *sc_bmap_mem;\n+\tstruct plt_bitmap *sa_bmap;\n+\tvoid *sa_bmap_mem;\n+\tuint64_t default_sci;\n+\tuint32_t lmac_bmap;\n+\tuint8_t num_mcs_blks;\n+\tuint8_t tcam_entries;\n+\tuint8_t secy_entries;\n+\tuint8_t sc_entries;\n+\tuint8_t sa_entries;\n+};\n+\n+static inline struct mcs_priv *\n+roc_mcs_to_mcs_priv(struct roc_mcs *roc_mcs)\n+{\n+\treturn (struct mcs_priv *)&roc_mcs->reserved[0];\n+}\n+\n+static inline void *\n+roc_mcs_to_mcs_cb_list(struct roc_mcs *roc_mcs)\n+{\n+\treturn (void *)((uintptr_t)roc_mcs->reserved + sizeof(struct mcs_priv));\n+}\n+\n+int mcs_event_cb_process(struct roc_mcs *mcs, struct roc_mcs_event_desc *desc);\n+\n+#endif /* _ROC_MCS_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_mcs_sec_cfg.c b/drivers/common/cnxk/roc_mcs_sec_cfg.c\nnew file mode 100644\nindex 0000000000..fabc174308\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_mcs_sec_cfg.c\n@@ -0,0 +1,425 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2022 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+int\n+roc_mcs_alloc_rsrc(struct roc_mcs *mcs, struct roc_mcs_alloc_rsrc_req *req,\n+\t\t struct roc_mcs_alloc_rsrc_rsp *rsp)\n+{\n+\tstruct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);\n+\tstruct mcs_alloc_rsrc_req *rsrc_req;\n+\tstruct mcs_alloc_rsrc_rsp *rsrc_rsp;\n+\tint rc, i;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (req == NULL || rsp == NULL)\n+\t\treturn -EINVAL;\n+\n+\trsrc_req = mbox_alloc_msg_mcs_alloc_resources(mcs->mbox);\n+\tif (rsrc_req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\trsrc_req->rsrc_type = req->rsrc_type;\n+\trsrc_req->rsrc_cnt = req->rsrc_cnt;\n+\trsrc_req->mcs_id = req->mcs_id;\n+\trsrc_req->dir = req->dir;\n+\trsrc_req->all = req->all;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rsrc_rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (rsrc_rsp->all) {\n+\t\trsrc_rsp->rsrc_cnt = 1;\n+\t\trsrc_rsp->rsrc_type = 0xFF;\n+\t}\n+\n+\tfor (i = 0; i < rsrc_rsp->rsrc_cnt; i++) {\n+\t\tswitch (rsrc_rsp->rsrc_type) {\n+\t\tcase MCS_RSRC_TYPE_FLOWID:\n+\t\t\trsp->flow_ids[i] = rsrc_rsp->flow_ids[i];\n+\t\t\tplt_bitmap_set(priv->tcam_bmap,\n+\t\t\t\t rsp->flow_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->tcam_entries : 0));\n+\t\t\tbreak;\n+\t\tcase MCS_RSRC_TYPE_SECY:\n+\t\t\trsp->secy_ids[i] = rsrc_rsp->secy_ids[i];\n+\t\t\tplt_bitmap_set(priv->secy_bmap,\n+\t\t\t\t rsp->secy_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->secy_entries : 0));\n+\t\t\tbreak;\n+\t\tcase MCS_RSRC_TYPE_SC:\n+\t\t\trsp->sc_ids[i] = rsrc_rsp->sc_ids[i];\n+\t\t\tplt_bitmap_set(priv->sc_bmap,\n+\t\t\t\t rsp->sc_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->sc_entries : 0));\n+\t\t\tbreak;\n+\t\tcase MCS_RSRC_TYPE_SA:\n+\t\t\trsp->sa_ids[2 * i] = rsrc_rsp->sa_ids[2 * i];\n+\t\t\trsp->sa_ids[2 * i + 1] = rsrc_rsp->sa_ids[2 * i + 1];\n+\t\t\tplt_bitmap_set(priv->sa_bmap,\n+\t\t\t\t rsp->sa_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->sa_entries : 0));\n+\t\t\tplt_bitmap_set(priv->sa_bmap,\n+\t\t\t\t rsp->sa_ids[2 * i + 1] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->sa_entries : 0));\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\trsp->flow_ids[i] = rsrc_rsp->flow_ids[i];\n+\t\t\trsp->secy_ids[i] = rsrc_rsp->secy_ids[i];\n+\t\t\trsp->sc_ids[i] = rsrc_rsp->sc_ids[i];\n+\t\t\trsp->sa_ids[2 * i] = rsrc_rsp->sa_ids[2 * i];\n+\t\t\trsp->sa_ids[2 * i + 1] = rsrc_rsp->sa_ids[2 * i + 1];\n+\t\t\tplt_bitmap_set(priv->tcam_bmap,\n+\t\t\t\t rsp->flow_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->tcam_entries : 0));\n+\t\t\tplt_bitmap_set(priv->secy_bmap,\n+\t\t\t\t rsp->secy_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->secy_entries : 0));\n+\t\t\tplt_bitmap_set(priv->sc_bmap,\n+\t\t\t\t rsp->sc_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->sc_entries : 0));\n+\t\t\tplt_bitmap_set(priv->sa_bmap,\n+\t\t\t\t rsp->sa_ids[i] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->sa_entries : 0));\n+\t\t\tplt_bitmap_set(priv->sa_bmap,\n+\t\t\t\t rsp->sa_ids[2 * i + 1] +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->sa_entries : 0));\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\trsp->rsrc_type = rsrc_rsp->rsrc_type;\n+\trsp->rsrc_cnt = rsrc_rsp->rsrc_cnt;\n+\trsp->mcs_id = rsrc_rsp->mcs_id;\n+\trsp->dir = rsrc_rsp->dir;\n+\trsp->all = rsrc_rsp->all;\n+\n+\treturn 0;\n+}\n+\n+int\n+roc_mcs_free_rsrc(struct roc_mcs *mcs, struct roc_mcs_free_rsrc_req *free_req)\n+{\n+\tstruct mcs_priv *priv = roc_mcs_to_mcs_priv(mcs);\n+\tstruct mcs_free_rsrc_req *req;\n+\tstruct msg_rsp *rsp;\n+\tint rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (free_req == NULL)\n+\t\treturn -EINVAL;\n+\n+\treq = mbox_alloc_msg_mcs_free_resources(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\treq->rsrc_id = free_req->rsrc_id;\n+\treq->rsrc_type = free_req->rsrc_type;\n+\treq->mcs_id = free_req->mcs_id;\n+\treq->dir = free_req->dir;\n+\treq->all = free_req->all;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tswitch (free_req->rsrc_type) {\n+\tcase MCS_RSRC_TYPE_FLOWID:\n+\t\tplt_bitmap_clear(priv->tcam_bmap,\n+\t\t\t\t free_req->rsrc_id +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->tcam_entries : 0));\n+\t\tbreak;\n+\tcase MCS_RSRC_TYPE_SECY:\n+\t\tplt_bitmap_clear(priv->secy_bmap,\n+\t\t\t\t free_req->rsrc_id +\n+\t\t\t\t\t ((req->dir == MCS_TX) ? priv->secy_entries : 0));\n+\t\tbreak;\n+\tcase MCS_RSRC_TYPE_SC:\n+\t\tplt_bitmap_clear(priv->sc_bmap,\n+\t\t\t\t free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->sc_entries : 0));\n+\t\tbreak;\n+\tcase MCS_RSRC_TYPE_SA:\n+\t\tplt_bitmap_clear(priv->sa_bmap,\n+\t\t\t\t free_req->rsrc_id + ((req->dir == MCS_TX) ? priv->sa_entries : 0));\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+int\n+roc_mcs_sa_policy_write(struct roc_mcs *mcs, struct roc_mcs_sa_plcy_write_req *sa_plcy)\n+{\n+\tstruct mcs_sa_plcy_write_req *sa;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (sa_plcy == NULL)\n+\t\treturn -EINVAL;\n+\n+\tsa = mbox_alloc_msg_mcs_sa_plcy_write(mcs->mbox);\n+\tif (sa == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tmbox_memcpy(sa->plcy, sa_plcy->plcy, sizeof(uint64_t) * 2 * 9);\n+\tsa->sa_index[0] = sa_plcy->sa_index[0];\n+\tsa->sa_index[1] = sa_plcy->sa_index[1];\n+\tsa->sa_cnt = sa_plcy->sa_cnt;\n+\tsa->mcs_id = sa_plcy->mcs_id;\n+\tsa->dir = sa_plcy->dir;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_sa_policy_read(struct roc_mcs *mcs __plt_unused,\n+\t\t struct roc_mcs_sa_plcy_write_req *sa __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+roc_mcs_pn_table_write(struct roc_mcs *mcs, struct roc_mcs_pn_table_write_req *pn_table)\n+{\n+\tstruct mcs_pn_table_write_req *pn;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (pn_table == NULL)\n+\t\treturn -EINVAL;\n+\n+\tpn = mbox_alloc_msg_mcs_pn_table_write(mcs->mbox);\n+\tif (pn == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tpn->next_pn = pn_table->next_pn;\n+\tpn->pn_id = pn_table->pn_id;\n+\tpn->mcs_id = pn_table->mcs_id;\n+\tpn->dir = pn_table->dir;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_pn_table_read(struct roc_mcs *mcs __plt_unused,\n+\t\t struct roc_mcs_pn_table_write_req *sa __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+roc_mcs_rx_sc_cam_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam)\n+{\n+\tstruct mcs_rx_sc_cam_write_req *rx_sc;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (rx_sc_cam == NULL)\n+\t\treturn -EINVAL;\n+\n+\trx_sc = mbox_alloc_msg_mcs_rx_sc_cam_write(mcs->mbox);\n+\tif (rx_sc == NULL)\n+\t\treturn -ENOMEM;\n+\n+\trx_sc->sci = rx_sc_cam->sci;\n+\trx_sc->secy_id = rx_sc_cam->secy_id;\n+\trx_sc->sc_id = rx_sc_cam->sc_id;\n+\trx_sc->mcs_id = rx_sc_cam->mcs_id;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_rx_sc_cam_read(struct roc_mcs *mcs __plt_unused,\n+\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+roc_mcs_rx_sc_cam_enable(struct roc_mcs *mcs __plt_unused,\n+\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+roc_mcs_secy_policy_write(struct roc_mcs *mcs, struct roc_mcs_secy_plcy_write_req *secy_plcy)\n+{\n+\tstruct mcs_secy_plcy_write_req *secy;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (secy_plcy == NULL)\n+\t\treturn -EINVAL;\n+\n+\tsecy = mbox_alloc_msg_mcs_secy_plcy_write(mcs->mbox);\n+\tif (secy == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tsecy->plcy = secy_plcy->plcy;\n+\tsecy->secy_id = secy_plcy->secy_id;\n+\tsecy->mcs_id = secy_plcy->mcs_id;\n+\tsecy->dir = secy_plcy->dir;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_secy_policy_read(struct roc_mcs *mcs __plt_unused,\n+\t\t\t struct roc_mcs_rx_sc_cam_write_req *rx_sc_cam __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+roc_mcs_rx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map)\n+{\n+\tstruct mcs_rx_sc_sa_map *sa_map;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (rx_sc_sa_map == NULL)\n+\t\treturn -EINVAL;\n+\n+\tsa_map = mbox_alloc_msg_mcs_rx_sc_sa_map_write(mcs->mbox);\n+\tif (sa_map == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tsa_map->sa_index = rx_sc_sa_map->sa_index;\n+\tsa_map->sa_in_use = rx_sc_sa_map->sa_in_use;\n+\tsa_map->sc_id = rx_sc_sa_map->sc_id;\n+\tsa_map->an = rx_sc_sa_map->an;\n+\tsa_map->mcs_id = rx_sc_sa_map->mcs_id;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_rx_sc_sa_map_read(struct roc_mcs *mcs __plt_unused,\n+\t\t\t struct roc_mcs_rx_sc_sa_map *rx_sc_sa_map __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+roc_mcs_tx_sc_sa_map_write(struct roc_mcs *mcs, struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map)\n+{\n+\tstruct mcs_tx_sc_sa_map *sa_map;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (tx_sc_sa_map == NULL)\n+\t\treturn -EINVAL;\n+\n+\tsa_map = mbox_alloc_msg_mcs_tx_sc_sa_map_write(mcs->mbox);\n+\tif (sa_map == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tsa_map->sa_index0 = tx_sc_sa_map->sa_index0;\n+\tsa_map->sa_index1 = tx_sc_sa_map->sa_index1;\n+\tsa_map->rekey_ena = tx_sc_sa_map->rekey_ena;\n+\tsa_map->sa_index0_vld = tx_sc_sa_map->sa_index0_vld;\n+\tsa_map->sa_index1_vld = tx_sc_sa_map->sa_index1_vld;\n+\tsa_map->tx_sa_active = tx_sc_sa_map->tx_sa_active;\n+\tsa_map->sectag_sci = tx_sc_sa_map->sectag_sci;\n+\tsa_map->sc_id = tx_sc_sa_map->sc_id;\n+\tsa_map->mcs_id = tx_sc_sa_map->mcs_id;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_tx_sc_sa_map_read(struct roc_mcs *mcs __plt_unused,\n+\t\t\t struct roc_mcs_tx_sc_sa_map *tx_sc_sa_map __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+roc_mcs_flowid_entry_write(struct roc_mcs *mcs, struct roc_mcs_flowid_entry_write_req *flowid_req)\n+{\n+\tstruct mcs_flowid_entry_write_req *flow_req;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (flowid_req == NULL)\n+\t\treturn -EINVAL;\n+\n+\tflow_req = mbox_alloc_msg_mcs_flowid_entry_write(mcs->mbox);\n+\tif (flow_req == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tmbox_memcpy(flow_req->data, flowid_req->data, sizeof(uint64_t) * 4);\n+\tmbox_memcpy(flow_req->mask, flowid_req->mask, sizeof(uint64_t) * 4);\n+\tflow_req->sci = flowid_req->sci;\n+\tflow_req->flow_id = flowid_req->flow_id;\n+\tflow_req->secy_id = flowid_req->secy_id;\n+\tflow_req->sc_id = flowid_req->sc_id;\n+\tflow_req->ena = flowid_req->ena;\n+\tflow_req->ctr_pkt = flowid_req->ctr_pkt;\n+\tflow_req->mcs_id = flowid_req->mcs_id;\n+\tflow_req->dir = flowid_req->dir;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\n+\n+int\n+roc_mcs_flowid_entry_read(struct roc_mcs *mcs __plt_unused,\n+\t\t\t struct roc_mcs_flowid_entry_write_req *flowid_rsp __plt_unused)\n+{\n+\tMCS_SUPPORT_CHECK;\n+\n+\treturn -ENOTSUP;\n+}\n+\n+int\n+roc_mcs_flowid_entry_enable(struct roc_mcs *mcs, struct roc_mcs_flowid_ena_dis_entry *entry)\n+{\n+\tstruct mcs_flowid_ena_dis_entry *flow_entry;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (entry == NULL)\n+\t\treturn -EINVAL;\n+\n+\tflow_entry = mbox_alloc_msg_mcs_flowid_ena_entry(mcs->mbox);\n+\tif (flow_entry == NULL)\n+\t\treturn -ENOMEM;\n+\n+\tflow_entry->flow_id = entry->flow_id;\n+\tflow_entry->ena = entry->ena;\n+\tflow_entry->mcs_id = entry->mcs_id;\n+\tflow_entry->dir = entry->dir;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\ndiff --git a/drivers/common/cnxk/roc_mcs_stats.c b/drivers/common/cnxk/roc_mcs_stats.c\nnew file mode 100644\nindex 0000000000..bd65826611\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_mcs_stats.c\n@@ -0,0 +1,230 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2022 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+int\n+roc_mcs_flowid_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,\n+\t\t\t struct roc_mcs_flowid_stats *stats)\n+{\n+\tstruct mcs_flowid_stats *rsp;\n+\tstruct mcs_stats_req *req;\n+\tint rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\treq = mbox_alloc_msg_mcs_get_flowid_stats(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\n+\treq->id = mcs_req->id;\n+\treq->mcs_id = mcs_req->mcs_id;\n+\treq->dir = mcs_req->dir;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tstats->tcam_hit_cnt = rsp->tcam_hit_cnt;\n+\n+\treturn rc;\n+}\n+\n+int\n+roc_mcs_secy_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,\n+\t\t struct roc_mcs_secy_stats *stats)\n+{\n+\tstruct mcs_secy_stats *rsp;\n+\tstruct mcs_stats_req *req;\n+\tint rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\treq = mbox_alloc_msg_mcs_get_secy_stats(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\n+\treq->id = mcs_req->id;\n+\treq->mcs_id = mcs_req->mcs_id;\n+\treq->dir = mcs_req->dir;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tstats->ctl_pkt_bcast_cnt = rsp->ctl_pkt_bcast_cnt;\n+\tstats->ctl_pkt_mcast_cnt = rsp->ctl_pkt_mcast_cnt;\n+\tstats->ctl_pkt_ucast_cnt = rsp->ctl_pkt_ucast_cnt;\n+\tstats->ctl_octet_cnt = rsp->ctl_octet_cnt;\n+\tstats->unctl_pkt_bcast_cnt = rsp->unctl_pkt_bcast_cnt;\n+\tstats->unctl_pkt_mcast_cnt = rsp->unctl_pkt_mcast_cnt;\n+\tstats->unctl_pkt_ucast_cnt = rsp->unctl_pkt_ucast_cnt;\n+\tstats->unctl_octet_cnt = rsp->unctl_octet_cnt;\n+\n+\tif (mcs_req->dir == MCS_RX) {\n+\t\tstats->octet_decrypted_cnt = rsp->octet_decrypted_cnt;\n+\t\tstats->octet_validated_cnt = rsp->octet_validated_cnt;\n+\t\tstats->pkt_port_disabled_cnt = rsp->pkt_port_disabled_cnt;\n+\t\tstats->pkt_badtag_cnt = rsp->pkt_badtag_cnt;\n+\t\tstats->pkt_nosa_cnt = rsp->pkt_nosa_cnt;\n+\t\tstats->pkt_nosaerror_cnt = rsp->pkt_nosaerror_cnt;\n+\t\tstats->pkt_tagged_ctl_cnt = rsp->pkt_tagged_ctl_cnt;\n+\t\tstats->pkt_untaged_cnt = rsp->pkt_untaged_cnt;\n+\t\tif (roc_model_is_cn10kb_a0())\n+\t\t\t/* CN10K-B */\n+\t\t\tstats->pkt_ctl_cnt = rsp->pkt_ctl_cnt;\n+\t\telse\n+\t\t\t/* CNF10K-B */\n+\t\t\tstats->pkt_notag_cnt = rsp->pkt_notag_cnt;\n+\t} else {\n+\t\tstats->octet_encrypted_cnt = rsp->octet_encrypted_cnt;\n+\t\tstats->octet_protected_cnt = rsp->octet_protected_cnt;\n+\t\tstats->pkt_noactivesa_cnt = rsp->pkt_noactivesa_cnt;\n+\t\tstats->pkt_toolong_cnt = rsp->pkt_toolong_cnt;\n+\t\tstats->pkt_untagged_cnt = rsp->pkt_untagged_cnt;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+int\n+roc_mcs_sc_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,\n+\t\t struct roc_mcs_sc_stats *stats)\n+{\n+\tstruct mcs_stats_req *req;\n+\tstruct mcs_sc_stats *rsp;\n+\tint rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\treq = mbox_alloc_msg_mcs_get_sc_stats(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\n+\treq->id = mcs_req->id;\n+\treq->mcs_id = mcs_req->mcs_id;\n+\treq->dir = mcs_req->dir;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (mcs_req->dir == MCS_RX) {\n+\t\tstats->hit_cnt = rsp->hit_cnt;\n+\t\tstats->pkt_invalid_cnt = rsp->pkt_invalid_cnt;\n+\t\tstats->pkt_late_cnt = rsp->pkt_late_cnt;\n+\t\tstats->pkt_notvalid_cnt = rsp->pkt_notvalid_cnt;\n+\t\tstats->pkt_unchecked_cnt = rsp->pkt_unchecked_cnt;\n+\t\tif (roc_model_is_cn10kb_a0()) {\n+\t\t\tstats->octet_decrypt_cnt = rsp->octet_decrypt_cnt;\n+\t\t\tstats->octet_validate_cnt = rsp->octet_validate_cnt;\n+\t\t} else {\n+\t\t\tstats->pkt_delay_cnt = rsp->pkt_delay_cnt;\n+\t\t\tstats->pkt_ok_cnt = rsp->pkt_ok_cnt;\n+\t\t}\n+\t} else {\n+\t\tstats->pkt_encrypt_cnt = rsp->pkt_encrypt_cnt;\n+\t\tstats->pkt_protected_cnt = rsp->pkt_protected_cnt;\n+\t\tif (roc_model_is_cn10kb_a0()) {\n+\t\t\tstats->octet_encrypt_cnt = rsp->octet_encrypt_cnt;\n+\t\t\tstats->octet_protected_cnt = rsp->octet_protected_cnt;\n+\t\t}\n+\t}\n+\n+\treturn rc;\n+}\n+\n+int\n+roc_mcs_sa_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,\n+\t\t struct roc_mcs_sa_stats *stats)\n+{\n+\tstruct mcs_stats_req *req;\n+\tstruct mcs_sa_stats *rsp;\n+\tint rc;\n+\n+\tif (!roc_model_is_cn10kb_a0())\n+\t\treturn MCS_ERR_HW_NOTSUP;\n+\n+\treq = mbox_alloc_msg_mcs_get_sa_stats(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\n+\treq->id = mcs_req->id;\n+\treq->mcs_id = mcs_req->mcs_id;\n+\treq->dir = mcs_req->dir;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (mcs_req->dir == MCS_RX) {\n+\t\tstats->pkt_invalid_cnt = rsp->pkt_invalid_cnt;\n+\t\tstats->pkt_nosaerror_cnt = rsp->pkt_nosaerror_cnt;\n+\t\tstats->pkt_notvalid_cnt = rsp->pkt_notvalid_cnt;\n+\t\tstats->pkt_ok_cnt = rsp->pkt_ok_cnt;\n+\t\tstats->pkt_nosa_cnt = rsp->pkt_nosa_cnt;\n+\t} else {\n+\t\tstats->pkt_encrypt_cnt = rsp->pkt_encrypt_cnt;\n+\t\tstats->pkt_protected_cnt = rsp->pkt_protected_cnt;\n+\t}\n+\n+\treturn rc;\n+}\n+\n+int\n+roc_mcs_port_stats_get(struct roc_mcs *mcs, struct roc_mcs_stats_req *mcs_req,\n+\t\t struct roc_mcs_port_stats *stats)\n+{\n+\tstruct mcs_port_stats *rsp;\n+\tstruct mcs_stats_req *req;\n+\tint rc;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\treq = mbox_alloc_msg_mcs_get_port_stats(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\n+\treq->id = mcs_req->id;\n+\treq->mcs_id = mcs_req->mcs_id;\n+\treq->dir = mcs_req->dir;\n+\n+\trc = mbox_process_msg(mcs->mbox, (void *)&rsp);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tstats->tcam_miss_cnt = rsp->tcam_miss_cnt;\n+\tstats->parser_err_cnt = rsp->parser_err_cnt;\n+\tif (roc_model_is_cnf10kb())\n+\t\tstats->preempt_err_cnt = rsp->preempt_err_cnt;\n+\n+\tstats->sectag_insert_err_cnt = rsp->sectag_insert_err_cnt;\n+\n+\treturn rc;\n+}\n+\n+int\n+roc_mcs_stats_clear(struct roc_mcs *mcs, struct roc_mcs_clear_stats *mcs_req)\n+{\n+\tstruct mcs_clear_stats *req;\n+\tstruct msg_rsp *rsp;\n+\n+\tMCS_SUPPORT_CHECK;\n+\n+\tif (!roc_model_is_cn10kb_a0() && mcs_req->type == MCS_SA_STATS)\n+\t\treturn MCS_ERR_HW_NOTSUP;\n+\n+\treq = mbox_alloc_msg_mcs_clear_stats(mcs->mbox);\n+\tif (req == NULL)\n+\t\treturn -ENOSPC;\n+\n+\treq->type = mcs_req->type;\n+\treq->id = mcs_req->id;\n+\treq->mcs_id = mcs_req->mcs_id;\n+\treq->dir = mcs_req->dir;\n+\treq->all = mcs_req->all;\n+\n+\treturn mbox_process_msg(mcs->mbox, (void *)&rsp);\n+}\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex 122d411fe7..b2b4aecedc 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -44,6 +44,9 @@\n /* DPI */\n #include \"roc_dpi_priv.h\"\n \n+/* MCS */\n+#include \"roc_mcs_priv.h\"\n+\n /* REE */\n #include \"roc_ree_priv.h\"\n \ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 276fec3660..5cdc70e0e0 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -99,6 +99,39 @@ INTERNAL {\n \troc_model;\n \troc_se_auth_key_set;\n \troc_se_ciph_key_set;\n+\troc_mcs_active_lmac_set;\n+\troc_mcs_alloc_rsrc;\n+\troc_mcs_dev_init;\n+\troc_mcs_dev_fini;\n+\troc_mcs_dev_get;\n+\troc_mcs_event_cb_register;\n+\troc_mcs_event_cb_unregister;\n+\troc_mcs_flowid_entry_enable;\n+\troc_mcs_flowid_entry_read;\n+\troc_mcs_flowid_entry_write;\n+\troc_mcs_flowid_stats_get;\n+\troc_mcs_free_rsrc;\n+\troc_mcs_hw_info_get;\n+\troc_mcs_intr_configure;\n+\troc_mcs_lmac_mode_set;\n+\troc_mcs_pn_table_write;\n+\troc_mcs_pn_table_read;\n+\troc_mcs_port_stats_get;\n+\troc_mcs_rx_sc_cam_enable;\n+\troc_mcs_rx_sc_cam_read;\n+\troc_mcs_rx_sc_cam_write;\n+\troc_mcs_rx_sc_sa_map_read;\n+\troc_mcs_rx_sc_sa_map_write;\n+\troc_mcs_sa_policy_read;\n+\troc_mcs_sa_policy_write;\n+\troc_mcs_sa_stats_get;\n+\troc_mcs_sc_stats_get;\n+\troc_mcs_secy_policy_read;\n+\troc_mcs_secy_policy_write;\n+\troc_mcs_secy_stats_get;\n+\troc_mcs_stats_clear;\n+\troc_mcs_tx_sc_sa_map_read;\n+\troc_mcs_tx_sc_sa_map_write;\n \troc_nix_bpf_alloc;\n \troc_nix_bpf_config;\n \troc_nix_bpf_connect;\n", "prefixes": [ "1/5" ] }