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GET /api/patches/117016/?format=api
{ "id": 117016, "url": "http://patches.dpdk.org/api/patches/117016/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220928033130.9106-17-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220928033130.9106-17-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220928033130.9106-17-suanmingm@nvidia.com", "date": "2022-09-28T03:31:29", "name": "[v2,16/17] net/mlx5: support device control for E-Switch default rule", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0a6d31ef3de0f729acb10658f78f1c5eac4798e9", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220928033130.9106-17-suanmingm@nvidia.com/mbox/", "series": [ { "id": 24870, "url": "http://patches.dpdk.org/api/series/24870/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24870", "date": "2022-09-28T03:31:15", "name": "net/mlx5: HW steering PMD update", "version": 2, "mbox": "http://patches.dpdk.org/series/24870/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/117016/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/117016/checks/", "tags": {}, "related": [], "headers": { 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b=boN6S5ltZTAEaFKECSDIKe0bgFaUxrfMPFZZi2JboX6i6QDOVQEkKHet3bCiWyjXOLL9gvMU0/OwhMAFxZ3el1odUBnkSG0AP2n9VbD3M1+zx7UZcGKn9PEi6iDEoMb6jhu0CVCyMwTdQkb69Hv/2qkANDg4MXhcPYZW+vWrKWvvk1knx9cc7AdbXsXZskXQtGfjZ7wN9SnlyFt2uBuhYoq2ISGZAdCN3bravRhQSQ+JSYDc459ZZxtN+7ooc8fia6D563gGj3lVGn4olPL7k5bLXjAlpAcENP27hbAzL56MDHkLBluFU6/+XTzlP5GMQw1+Y61EVp4P3xAFwz0nRw==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>, <orika@nvidia.com>, \"Dariusz\n Sosnowski\" <dsosnowski@nvidia.com>, Xueming Li <xuemingl@nvidia.com>", "Subject": "[PATCH v2 16/17] net/mlx5: support device control for E-Switch\n default rule", "Date": "Wed, 28 Sep 2022 06:31:29 +0300", "Message-ID": "<20220928033130.9106-17-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220928033130.9106-1-suanmingm@nvidia.com>", "References": "<20220923144334.27736-1-suanmingm@nvidia.com>\n <20220928033130.9106-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0000C409:EE_|BL1PR12MB5972:EE_", "X-MS-Office365-Filtering-Correlation-Id": "087c3d51-dd48-47a1-e901-08daa1022002", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", 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PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(346002)(39860400002)(396003)(376002)(136003)(451199015)(46966006)(36840700001)(40470700004)(2616005)(26005)(41300700001)(7636003)(86362001)(478600001)(55016003)(30864003)(5660300002)(82740400003)(40460700003)(7696005)(82310400005)(2906002)(36756003)(356005)(40480700001)(47076005)(1076003)(16526019)(336012)(186003)(36860700001)(107886003)(426003)(8676002)(83380400001)(70586007)(70206006)(4326008)(8936002)(6286002)(316002)(54906003)(110136005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Sep 2022 03:32:52.3227 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 087c3d51-dd48-47a1-e901-08daa1022002", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0000C409.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL1PR12MB5972", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Dariusz Sosnowski <dsosnowski@nvidia.com>\n\nThis patch introduces\nThis patch adds support for fdb_def_rule_en device argument to HW\nSteering, which controls:\n\n- creation of default FDB jump flow rule,\n- ability of the user to create transfer flow rules in root table.\n\nA new PMD API to allow user application to enable traffic with port\nID and SQ number is also added to direct packet to wire.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 14 ++\n drivers/net/mlx5/mlx5.h | 4 +-\n drivers/net/mlx5/mlx5_flow.c | 28 ++--\n drivers/net/mlx5/mlx5_flow.h | 11 +-\n drivers/net/mlx5/mlx5_flow_dv.c | 46 ++---\n drivers/net/mlx5/mlx5_flow_hw.c | 279 +++++++++++++++----------------\n drivers/net/mlx5/mlx5_trigger.c | 31 ++--\n drivers/net/mlx5/mlx5_tx.h | 1 +\n drivers/net/mlx5/mlx5_txq.c | 47 ++++++\n drivers/net/mlx5/rte_pmd_mlx5.h | 17 ++\n drivers/net/mlx5/version.map | 1 +\n 11 files changed, 274 insertions(+), 205 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 60a1a391fb..de8c003d02 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1554,6 +1554,20 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \trte_rwlock_init(&priv->ind_tbls_lock);\n \tif (priv->sh->config.dv_flow_en == 2) {\n #ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\t\tif (priv->sh->config.dv_esw_en) {\n+\t\t\tif (priv->sh->dv_regc0_mask == UINT32_MAX) {\n+\t\t\t\tDRV_LOG(ERR, \"E-Switch port metadata is required when using HWS \"\n+\t\t\t\t\t \"but it is disabled (configure it through devlink)\");\n+\t\t\t\terr = ENOTSUP;\n+\t\t\t\tgoto error;\n+\t\t\t}\n+\t\t\tif (priv->sh->dv_regc0_mask == 0) {\n+\t\t\t\tDRV_LOG(ERR, \"E-Switch with HWS is not supported \"\n+\t\t\t\t\t \"(no available bits in reg_c[0])\");\n+\t\t\t\terr = ENOTSUP;\n+\t\t\t\tgoto error;\n+\t\t\t}\n+\t\t}\n \t\tif (priv->vport_meta_mask)\n \t\t\tflow_hw_set_port_info(eth_dev);\n \t\tif (priv->sh->config.dv_esw_en &&\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 5d92df8965..9299ffe9f9 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -2015,7 +2015,7 @@ int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops);\n int mlx5_flow_start_default(struct rte_eth_dev *dev);\n void mlx5_flow_stop_default(struct rte_eth_dev *dev);\n int mlx5_flow_verify(struct rte_eth_dev *dev);\n-int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue);\n+int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t sq_num);\n int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev,\n \t\t\tstruct rte_flow_item_eth *eth_spec,\n \t\t\tstruct rte_flow_item_eth *eth_mask,\n@@ -2027,7 +2027,7 @@ int mlx5_ctrl_flow(struct rte_eth_dev *dev,\n int mlx5_flow_lacp_miss(struct rte_eth_dev *dev);\n struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev);\n uint32_t mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev,\n-\t\t\t\t\t uint32_t txq);\n+\t\t\t\t\t uint32_t sq_num);\n void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh,\n \t\t\t\t uint64_t async_id, int status);\n void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh);\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex bc2ccb4d3c..2142cd828a 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -7155,14 +7155,14 @@ mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev)\n *\n * @param dev\n * Pointer to Ethernet device.\n- * @param txq\n- * Txq index.\n+ * @param sq_num\n+ * SQ number.\n *\n * @return\n * Flow ID on success, 0 otherwise and rte_errno is set.\n */\n uint32_t\n-mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t txq)\n+mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sq_num)\n {\n \tstruct rte_flow_attr attr = {\n \t\t.group = 0,\n@@ -7174,8 +7174,8 @@ mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t txq)\n \tstruct rte_flow_item_port_id port_spec = {\n \t\t.id = MLX5_PORT_ESW_MGR,\n \t};\n-\tstruct mlx5_rte_flow_item_tx_queue txq_spec = {\n-\t\t.queue = txq,\n+\tstruct mlx5_rte_flow_item_sq sq_spec = {\n+\t\t.queue = sq_num,\n \t};\n \tstruct rte_flow_item pattern[] = {\n \t\t{\n@@ -7184,8 +7184,8 @@ mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t txq)\n \t\t},\n \t\t{\n \t\t\t.type = (enum rte_flow_item_type)\n-\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,\n-\t\t\t.spec = &txq_spec,\n+\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_SQ,\n+\t\t\t.spec = &sq_spec,\n \t\t},\n \t\t{\n \t\t\t.type = RTE_FLOW_ITEM_TYPE_END,\n@@ -7556,30 +7556,30 @@ mlx5_flow_verify(struct rte_eth_dev *dev __rte_unused)\n *\n * @param dev\n * Pointer to Ethernet device.\n- * @param queue\n- * The queue index.\n+ * @param sq_num\n+ * The SQ hw number.\n *\n * @return\n * 0 on success, a negative errno value otherwise and rte_errno is set.\n */\n int\n mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev,\n-\t\t\t uint32_t queue)\n+\t\t\t uint32_t sq_num)\n {\n \tconst struct rte_flow_attr attr = {\n \t\t.egress = 1,\n \t\t.priority = 0,\n \t};\n-\tstruct mlx5_rte_flow_item_tx_queue queue_spec = {\n-\t\t.queue = queue,\n+\tstruct mlx5_rte_flow_item_sq queue_spec = {\n+\t\t.queue = sq_num,\n \t};\n-\tstruct mlx5_rte_flow_item_tx_queue queue_mask = {\n+\tstruct mlx5_rte_flow_item_sq queue_mask = {\n \t\t.queue = UINT32_MAX,\n \t};\n \tstruct rte_flow_item items[] = {\n \t\t{\n \t\t\t.type = (enum rte_flow_item_type)\n-\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,\n+\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_SQ,\n \t\t\t.spec = &queue_spec,\n \t\t\t.last = NULL,\n \t\t\t.mask = &queue_mask,\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 3f4aa080bb..63f946473d 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -29,7 +29,7 @@\n enum mlx5_rte_flow_item_type {\n \tMLX5_RTE_FLOW_ITEM_TYPE_END = INT_MIN,\n \tMLX5_RTE_FLOW_ITEM_TYPE_TAG,\n-\tMLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,\n+\tMLX5_RTE_FLOW_ITEM_TYPE_SQ,\n \tMLX5_RTE_FLOW_ITEM_TYPE_VLAN,\n \tMLX5_RTE_FLOW_ITEM_TYPE_TUNNEL,\n };\n@@ -115,8 +115,8 @@ struct mlx5_flow_action_copy_mreg {\n };\n \n /* Matches on source queue. */\n-struct mlx5_rte_flow_item_tx_queue {\n-\tuint32_t queue;\n+struct mlx5_rte_flow_item_sq {\n+\tuint32_t queue; /* DevX SQ number */\n };\n \n /* Feature name to allocate metadata register. */\n@@ -179,7 +179,7 @@ enum mlx5_feature_name {\n #define MLX5_FLOW_LAYER_GENEVE (1u << 26)\n \n /* Queue items. */\n-#define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)\n+#define MLX5_FLOW_ITEM_SQ (1u << 27)\n \n /* Pattern tunnel Layer bits (continued). */\n #define MLX5_FLOW_LAYER_GTP (1u << 28)\n@@ -2475,9 +2475,8 @@ int mlx5_flow_pick_transfer_proxy(struct rte_eth_dev *dev,\n \n int mlx5_flow_hw_flush_ctrl_flows(struct rte_eth_dev *dev);\n \n-int mlx5_flow_hw_esw_create_mgr_sq_miss_flow(struct rte_eth_dev *dev);\n int mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev,\n-\t\t\t\t\t uint32_t txq);\n+\t\t\t\t\t uint32_t sqn);\n int mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev);\n int mlx5_flow_hw_create_tx_default_mreg_copy_flow(struct rte_eth_dev *dev);\n int mlx5_flow_actions_validate(struct rte_eth_dev *dev,\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 758672568c..e5c09c27eb 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -7453,8 +7453,8 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t\t\t\treturn ret;\n \t\t\tlast_item = MLX5_FLOW_ITEM_TAG;\n \t\t\tbreak;\n-\t\tcase MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:\n-\t\t\tlast_item = MLX5_FLOW_ITEM_TX_QUEUE;\n+\t\tcase MLX5_RTE_FLOW_ITEM_TYPE_SQ:\n+\t\t\tlast_item = MLX5_FLOW_ITEM_SQ;\n \t\t\tbreak;\n \t\tcase MLX5_RTE_FLOW_ITEM_TYPE_TAG:\n \t\t\tbreak;\n@@ -8343,7 +8343,7 @@ flow_dv_validate(struct rte_eth_dev *dev, const struct rte_flow_attr *attr,\n \t * work due to metadata regC0 mismatch.\n \t */\n \tif ((!attr->transfer && attr->egress) && priv->representor &&\n-\t !(item_flags & MLX5_FLOW_ITEM_TX_QUEUE))\n+\t !(item_flags & MLX5_FLOW_ITEM_SQ))\n \t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM,\n \t\t\t\t\t NULL,\n@@ -11390,10 +11390,10 @@ flow_dv_translate_create_counter(struct rte_eth_dev *dev,\n }\n \n /**\n- * Add Tx queue matcher\n+ * Add SQ matcher\n *\n- * @param[in] dev\n- * Pointer to the dev struct.\n+ * @param[in, out] matcher\n+ * Flow matcher.\n * @param[in, out] key\n * Flow matcher value.\n * @param[in] item\n@@ -11402,40 +11402,29 @@ flow_dv_translate_create_counter(struct rte_eth_dev *dev,\n * Set flow matcher mask or value.\n */\n static void\n-flow_dv_translate_item_tx_queue(struct rte_eth_dev *dev,\n-\t\t\t\tvoid *key,\n-\t\t\t\tconst struct rte_flow_item *item,\n-\t\t\t\tuint32_t key_type)\n+flow_dv_translate_item_sq(void *key,\n+\t\t\t const struct rte_flow_item *item,\n+\t\t\t uint32_t key_type)\n {\n-\tconst struct mlx5_rte_flow_item_tx_queue *queue_m;\n-\tconst struct mlx5_rte_flow_item_tx_queue *queue_v;\n-\tconst struct mlx5_rte_flow_item_tx_queue queue_mask = {\n+\tconst struct mlx5_rte_flow_item_sq *queue_m;\n+\tconst struct mlx5_rte_flow_item_sq *queue_v;\n+\tconst struct mlx5_rte_flow_item_sq queue_mask = {\n \t\t.queue = UINT32_MAX,\n \t};\n-\tvoid *misc_v =\n-\t\tMLX5_ADDR_OF(fte_match_param, key, misc_parameters);\n-\tstruct mlx5_txq_ctrl *txq = NULL;\n+\tvoid *misc_v = MLX5_ADDR_OF(fte_match_param, key, misc_parameters);\n \tuint32_t queue;\n \n \tMLX5_ITEM_UPDATE(item, key_type, queue_v, queue_m, &queue_mask);\n \tif (!queue_m || !queue_v)\n \t\treturn;\n \tif (key_type & MLX5_SET_MATCHER_V) {\n-\t\ttxq = mlx5_txq_get(dev, queue_v->queue);\n-\t\tif (!txq)\n-\t\t\treturn;\n-\t\tif (txq->is_hairpin)\n-\t\t\tqueue = txq->obj->sq->id;\n-\t\telse\n-\t\t\tqueue = txq->obj->sq_obj.sq->id;\n+\t\tqueue = queue_v->queue;\n \t\tif (key_type == MLX5_SET_MATCHER_SW_V)\n \t\t\tqueue &= queue_m->queue;\n \t} else {\n \t\tqueue = queue_m->queue;\n \t}\n \tMLX5_SET(fte_match_set_misc, misc_v, source_sqn, queue);\n-\tif (txq)\n-\t\tmlx5_txq_release(dev, queue_v->queue);\n }\n \n /**\n@@ -13341,9 +13330,9 @@ flow_dv_translate_items(struct rte_eth_dev *dev,\n \t\tflow_dv_translate_mlx5_item_tag(dev, key, items, key_type);\n \t\tlast_item = MLX5_FLOW_ITEM_TAG;\n \t\tbreak;\n-\tcase MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:\n-\t\tflow_dv_translate_item_tx_queue(dev, key, items, key_type);\n-\t\tlast_item = MLX5_FLOW_ITEM_TX_QUEUE;\n+\tcase MLX5_RTE_FLOW_ITEM_TYPE_SQ:\n+\t\tflow_dv_translate_item_sq(key, items, key_type);\n+\t\tlast_item = MLX5_FLOW_ITEM_SQ;\n \t\tbreak;\n \tcase RTE_FLOW_ITEM_TYPE_GTP:\n \t\tflow_dv_translate_item_gtp(key, items, tunnel, key_type);\n@@ -13552,7 +13541,6 @@ flow_dv_translate_items_sws(struct rte_eth_dev *dev,\n \t\t\twks.last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX :\n \t\t\t\t\t\t MLX5_FLOW_ITEM_OUTER_FLEX;\n \t\t\tbreak;\n-\n \t\tdefault:\n \t\t\tret = flow_dv_translate_items(dev, items, &wks_m,\n \t\t\t\tmatch_mask, MLX5_SET_MATCHER_SW_M, error);\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 31f98a2636..6a7f1376f7 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -3154,7 +3154,10 @@ flow_hw_translate_group(struct rte_eth_dev *dev,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tconst struct rte_flow_attr *flow_attr = &cfg->attr.flow_attr;\n \n-\tif (priv->sh->config.dv_esw_en && cfg->external && flow_attr->transfer) {\n+\tif (priv->sh->config.dv_esw_en &&\n+\t priv->fdb_def_rule &&\n+\t cfg->external &&\n+\t flow_attr->transfer) {\n \t\tif (group > MLX5_HW_MAX_TRANSFER_GROUP)\n \t\t\treturn rte_flow_error_set(error, EINVAL,\n \t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ATTR_GROUP,\n@@ -4610,7 +4613,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_GTP:\n \t\tcase RTE_FLOW_ITEM_TYPE_GTP_PSC:\n \t\tcase RTE_FLOW_ITEM_TYPE_VXLAN:\n-\t\tcase MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:\n+\t\tcase MLX5_RTE_FLOW_ITEM_TYPE_SQ:\n \t\tcase RTE_FLOW_ITEM_TYPE_GRE:\n \t\tcase RTE_FLOW_ITEM_TYPE_GRE_KEY:\n \t\tcase RTE_FLOW_ITEM_TYPE_GRE_OPTION:\n@@ -5103,14 +5106,23 @@ flow_hw_free_vport_actions(struct mlx5_priv *priv)\n }\n \n static uint32_t\n-flow_hw_usable_lsb_vport_mask(struct mlx5_priv *priv)\n+flow_hw_esw_mgr_regc_marker_mask(struct rte_eth_dev *dev)\n {\n-\tuint32_t usable_mask = ~priv->vport_meta_mask;\n+\tuint32_t mask = MLX5_SH(dev)->dv_regc0_mask;\n \n-\tif (usable_mask)\n-\t\treturn (1 << rte_bsf32(usable_mask));\n-\telse\n-\t\treturn 0;\n+\t/* Mask is verified during device initialization. */\n+\tMLX5_ASSERT(mask != 0);\n+\treturn mask;\n+}\n+\n+static uint32_t\n+flow_hw_esw_mgr_regc_marker(struct rte_eth_dev *dev)\n+{\n+\tuint32_t mask = MLX5_SH(dev)->dv_regc0_mask;\n+\n+\t/* Mask is verified during device initialization. */\n+\tMLX5_ASSERT(mask != 0);\n+\treturn RTE_BIT32(rte_bsf32(mask));\n }\n \n /**\n@@ -5136,12 +5148,19 @@ flow_hw_create_ctrl_esw_mgr_pattern_template(struct rte_eth_dev *dev)\n \tstruct rte_flow_item_ethdev port_mask = {\n \t\t.port_id = UINT16_MAX,\n \t};\n+\tstruct mlx5_rte_flow_item_sq sq_mask = {\n+\t\t.queue = UINT32_MAX,\n+\t};\n \tstruct rte_flow_item items[] = {\n \t\t{\n \t\t\t.type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,\n \t\t\t.spec = &port_spec,\n \t\t\t.mask = &port_mask,\n \t\t},\n+\t\t{\n+\t\t\t.type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,\n+\t\t\t.mask = &sq_mask,\n+\t\t},\n \t\t{\n \t\t\t.type = RTE_FLOW_ITEM_TYPE_END,\n \t\t},\n@@ -5151,9 +5170,10 @@ flow_hw_create_ctrl_esw_mgr_pattern_template(struct rte_eth_dev *dev)\n }\n \n /**\n- * Creates a flow pattern template used to match REG_C_0 and a TX queue.\n- * Matching on REG_C_0 is set up to match on least significant bit usable\n- * by user-space, which is set when packet was originated from E-Switch Manager.\n+ * Creates a flow pattern template used to match REG_C_0 and a SQ.\n+ * Matching on REG_C_0 is set up to match on all bits usable by user-space.\n+ * If traffic was sent from E-Switch Manager, then all usable bits will be set to 0,\n+ * except the least significant bit, which will be set to 1.\n *\n * This template is used to set up a table for SQ miss default flow.\n *\n@@ -5166,8 +5186,6 @@ flow_hw_create_ctrl_esw_mgr_pattern_template(struct rte_eth_dev *dev)\n static struct rte_flow_pattern_template *\n flow_hw_create_ctrl_regc_sq_pattern_template(struct rte_eth_dev *dev)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tuint32_t marker_bit = flow_hw_usable_lsb_vport_mask(priv);\n \tstruct rte_flow_pattern_template_attr attr = {\n \t\t.relaxed_matching = 0,\n \t\t.transfer = 1,\n@@ -5177,8 +5195,9 @@ flow_hw_create_ctrl_regc_sq_pattern_template(struct rte_eth_dev *dev)\n \t};\n \tstruct rte_flow_item_tag reg_c0_mask = {\n \t\t.index = 0xff,\n+\t\t.data = flow_hw_esw_mgr_regc_marker_mask(dev),\n \t};\n-\tstruct mlx5_rte_flow_item_tx_queue queue_mask = {\n+\tstruct mlx5_rte_flow_item_sq queue_mask = {\n \t\t.queue = UINT32_MAX,\n \t};\n \tstruct rte_flow_item items[] = {\n@@ -5190,7 +5209,7 @@ flow_hw_create_ctrl_regc_sq_pattern_template(struct rte_eth_dev *dev)\n \t\t},\n \t\t{\n \t\t\t.type = (enum rte_flow_item_type)\n-\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,\n+\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_SQ,\n \t\t\t.mask = &queue_mask,\n \t\t},\n \t\t{\n@@ -5198,12 +5217,6 @@ flow_hw_create_ctrl_regc_sq_pattern_template(struct rte_eth_dev *dev)\n \t\t},\n \t};\n \n-\tif (!marker_bit) {\n-\t\tDRV_LOG(ERR, \"Unable to set up pattern template for SQ miss table\");\n-\t\treturn NULL;\n-\t}\n-\treg_c0_spec.data = marker_bit;\n-\treg_c0_mask.data = marker_bit;\n \treturn flow_hw_pattern_template_create(dev, &attr, items, NULL);\n }\n \n@@ -5295,9 +5308,8 @@ flow_hw_create_tx_default_mreg_copy_pattern_template(struct rte_eth_dev *dev)\n static struct rte_flow_actions_template *\n flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tuint32_t marker_bit = flow_hw_usable_lsb_vport_mask(priv);\n-\tuint32_t marker_bit_mask = UINT32_MAX;\n+\tuint32_t marker_mask = flow_hw_esw_mgr_regc_marker_mask(dev);\n+\tuint32_t marker_bits = flow_hw_esw_mgr_regc_marker(dev);\n \tstruct rte_flow_actions_template_attr attr = {\n \t\t.transfer = 1,\n \t};\n@@ -5310,7 +5322,7 @@ flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev)\n \t\t.src = {\n \t\t\t.field = RTE_FLOW_FIELD_VALUE,\n \t\t},\n-\t\t.width = 1,\n+\t\t.width = __builtin_popcount(marker_mask),\n \t};\n \tstruct rte_flow_action_modify_field set_reg_m = {\n \t\t.operation = RTE_FLOW_MODIFY_SET,\n@@ -5357,13 +5369,9 @@ flow_hw_create_ctrl_regc_jump_actions_template(struct rte_eth_dev *dev)\n \t\t}\n \t};\n \n-\tif (!marker_bit) {\n-\t\tDRV_LOG(ERR, \"Unable to set up actions template for SQ miss table\");\n-\t\treturn NULL;\n-\t}\n-\tset_reg_v.dst.offset = rte_bsf32(marker_bit);\n-\trte_memcpy(set_reg_v.src.value, &marker_bit, sizeof(marker_bit));\n-\trte_memcpy(set_reg_m.src.value, &marker_bit_mask, sizeof(marker_bit_mask));\n+\tset_reg_v.dst.offset = rte_bsf32(marker_mask);\n+\trte_memcpy(set_reg_v.src.value, &marker_bits, sizeof(marker_bits));\n+\trte_memcpy(set_reg_m.src.value, &marker_mask, sizeof(marker_mask));\n \treturn flow_hw_actions_template_create(dev, &attr, actions_v, actions_m, NULL);\n }\n \n@@ -5550,7 +5558,7 @@ flow_hw_create_ctrl_sq_miss_root_table(struct rte_eth_dev *dev,\n \tstruct rte_flow_template_table_attr attr = {\n \t\t.flow_attr = {\n \t\t\t.group = 0,\n-\t\t\t.priority = 0,\n+\t\t\t.priority = MLX5_HW_LOWEST_PRIO_ROOT,\n \t\t\t.ingress = 0,\n \t\t\t.egress = 0,\n \t\t\t.transfer = 1,\n@@ -5665,7 +5673,7 @@ flow_hw_create_ctrl_jump_table(struct rte_eth_dev *dev,\n \tstruct rte_flow_template_table_attr attr = {\n \t\t.flow_attr = {\n \t\t\t.group = 0,\n-\t\t\t.priority = MLX5_HW_LOWEST_PRIO_ROOT,\n+\t\t\t.priority = 0,\n \t\t\t.ingress = 0,\n \t\t\t.egress = 0,\n \t\t\t.transfer = 1,\n@@ -7727,141 +7735,123 @@ flow_hw_flush_all_ctrl_flows(struct rte_eth_dev *dev)\n }\n \n int\n-mlx5_flow_hw_esw_create_mgr_sq_miss_flow(struct rte_eth_dev *dev)\n+mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn)\n {\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct rte_flow_item_ethdev port_spec = {\n+\tuint16_t port_id = dev->data->port_id;\n+\tstruct rte_flow_item_ethdev esw_mgr_spec = {\n \t\t.port_id = MLX5_REPRESENTED_PORT_ESW_MGR,\n \t};\n-\tstruct rte_flow_item_ethdev port_mask = {\n+\tstruct rte_flow_item_ethdev esw_mgr_mask = {\n \t\t.port_id = MLX5_REPRESENTED_PORT_ESW_MGR,\n \t};\n-\tstruct rte_flow_item items[] = {\n-\t\t{\n-\t\t\t.type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,\n-\t\t\t.spec = &port_spec,\n-\t\t\t.mask = &port_mask,\n-\t\t},\n-\t\t{\n-\t\t\t.type = RTE_FLOW_ITEM_TYPE_END,\n-\t\t},\n-\t};\n-\tstruct rte_flow_action_modify_field modify_field = {\n-\t\t.operation = RTE_FLOW_MODIFY_SET,\n-\t\t.dst = {\n-\t\t\t.field = (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG,\n-\t\t},\n-\t\t.src = {\n-\t\t\t.field = RTE_FLOW_FIELD_VALUE,\n-\t\t},\n-\t\t.width = 1,\n-\t};\n-\tstruct rte_flow_action_jump jump = {\n-\t\t.group = 1,\n-\t};\n-\tstruct rte_flow_action actions[] = {\n-\t\t{\n-\t\t\t.type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,\n-\t\t\t.conf = &modify_field,\n-\t\t},\n-\t\t{\n-\t\t\t.type = RTE_FLOW_ACTION_TYPE_JUMP,\n-\t\t\t.conf = &jump,\n-\t\t},\n-\t\t{\n-\t\t\t.type = RTE_FLOW_ACTION_TYPE_END,\n-\t\t},\n-\t};\n-\n-\tMLX5_ASSERT(priv->master);\n-\tif (!priv->dr_ctx ||\n-\t !priv->hw_esw_sq_miss_root_tbl)\n-\t\treturn 0;\n-\treturn flow_hw_create_ctrl_flow(dev, dev,\n-\t\t\t\t\tpriv->hw_esw_sq_miss_root_tbl,\n-\t\t\t\t\titems, 0, actions, 0);\n-}\n-\n-int\n-mlx5_flow_hw_esw_create_sq_miss_flow(struct rte_eth_dev *dev, uint32_t txq)\n-{\n-\tuint16_t port_id = dev->data->port_id;\n \tstruct rte_flow_item_tag reg_c0_spec = {\n \t\t.index = (uint8_t)REG_C_0,\n+\t\t.data = flow_hw_esw_mgr_regc_marker(dev),\n \t};\n \tstruct rte_flow_item_tag reg_c0_mask = {\n \t\t.index = 0xff,\n+\t\t.data = flow_hw_esw_mgr_regc_marker_mask(dev),\n \t};\n-\tstruct mlx5_rte_flow_item_tx_queue queue_spec = {\n-\t\t.queue = txq,\n-\t};\n-\tstruct mlx5_rte_flow_item_tx_queue queue_mask = {\n-\t\t.queue = UINT32_MAX,\n-\t};\n-\tstruct rte_flow_item items[] = {\n-\t\t{\n-\t\t\t.type = (enum rte_flow_item_type)\n-\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_TAG,\n-\t\t\t.spec = ®_c0_spec,\n-\t\t\t.mask = ®_c0_mask,\n-\t\t},\n-\t\t{\n-\t\t\t.type = (enum rte_flow_item_type)\n-\t\t\t\tMLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE,\n-\t\t\t.spec = &queue_spec,\n-\t\t\t.mask = &queue_mask,\n-\t\t},\n-\t\t{\n-\t\t\t.type = RTE_FLOW_ITEM_TYPE_END,\n-\t\t},\n+\tstruct mlx5_rte_flow_item_sq sq_spec = {\n+\t\t.queue = sqn,\n \t};\n \tstruct rte_flow_action_ethdev port = {\n \t\t.port_id = port_id,\n \t};\n-\tstruct rte_flow_action actions[] = {\n-\t\t{\n-\t\t\t.type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,\n-\t\t\t.conf = &port,\n-\t\t},\n-\t\t{\n-\t\t\t.type = RTE_FLOW_ACTION_TYPE_END,\n-\t\t},\n-\t};\n+\tstruct rte_flow_item items[3] = { { 0 } };\n+\tstruct rte_flow_action actions[3] = { { 0 } };\n \tstruct rte_eth_dev *proxy_dev;\n \tstruct mlx5_priv *proxy_priv;\n \tuint16_t proxy_port_id = dev->data->port_id;\n-\tuint32_t marker_bit;\n \tint ret;\n \n-\tRTE_SET_USED(txq);\n \tret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);\n \tif (ret) {\n-\t\tDRV_LOG(ERR, \"Unable to pick proxy port for port %u\", port_id);\n+\t\tDRV_LOG(ERR, \"Unable to pick transfer proxy port for port %u. Transfer proxy \"\n+\t\t\t \"port must be present to create default SQ miss flows.\",\n+\t\t\t port_id);\n \t\treturn ret;\n \t}\n \tproxy_dev = &rte_eth_devices[proxy_port_id];\n \tproxy_priv = proxy_dev->data->dev_private;\n-\tif (!proxy_priv->dr_ctx)\n+\tif (!proxy_priv->dr_ctx) {\n+\t\tDRV_LOG(DEBUG, \"Transfer proxy port (port %u) of port %u must be configured \"\n+\t\t\t \"for HWS to create default SQ miss flows. Default flows will \"\n+\t\t\t \"not be created.\",\n+\t\t\t proxy_port_id, port_id);\n \t\treturn 0;\n+\t}\n \tif (!proxy_priv->hw_esw_sq_miss_root_tbl ||\n \t !proxy_priv->hw_esw_sq_miss_tbl) {\n-\t\tDRV_LOG(ERR, \"port %u proxy port %u was configured but default\"\n-\t\t\t\" flow tables are not created\",\n-\t\t\tport_id, proxy_port_id);\n+\t\tDRV_LOG(ERR, \"Transfer proxy port (port %u) of port %u was configured, but \"\n+\t\t\t \"default flow tables were not created.\",\n+\t\t\t proxy_port_id, port_id);\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n \t}\n-\tmarker_bit = flow_hw_usable_lsb_vport_mask(proxy_priv);\n-\tif (!marker_bit) {\n-\t\tDRV_LOG(ERR, \"Unable to set up control flow in SQ miss table\");\n-\t\trte_errno = EINVAL;\n-\t\treturn -rte_errno;\n+\t/*\n+\t * Create a root SQ miss flow rule - match E-Switch Manager and SQ,\n+\t * and jump to group 1.\n+\t */\n+\titems[0] = (struct rte_flow_item){\n+\t\t.type = RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT,\n+\t\t.spec = &esw_mgr_spec,\n+\t\t.mask = &esw_mgr_mask,\n+\t};\n+\titems[1] = (struct rte_flow_item){\n+\t\t.type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,\n+\t\t.spec = &sq_spec,\n+\t};\n+\titems[2] = (struct rte_flow_item){\n+\t\t.type = RTE_FLOW_ITEM_TYPE_END,\n+\t};\n+\tactions[0] = (struct rte_flow_action){\n+\t\t.type = RTE_FLOW_ACTION_TYPE_MODIFY_FIELD,\n+\t};\n+\tactions[1] = (struct rte_flow_action){\n+\t\t.type = RTE_FLOW_ACTION_TYPE_JUMP,\n+\t};\n+\tactions[2] = (struct rte_flow_action) {\n+\t\t.type = RTE_FLOW_ACTION_TYPE_END,\n+\t};\n+\tret = flow_hw_create_ctrl_flow(dev, proxy_dev, proxy_priv->hw_esw_sq_miss_root_tbl,\n+\t\t\t\t items, 0, actions, 0);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Port %u failed to create root SQ miss flow rule for SQ %u, ret %d\",\n+\t\t\tport_id, sqn, ret);\n+\t\treturn ret;\n \t}\n-\treg_c0_spec.data = marker_bit;\n-\treg_c0_mask.data = marker_bit;\n-\treturn flow_hw_create_ctrl_flow(dev, proxy_dev,\n-\t\t\t\t\tproxy_priv->hw_esw_sq_miss_tbl,\n-\t\t\t\t\titems, 0, actions, 0);\n+\t/*\n+\t * Create a non-root SQ miss flow rule - match REG_C_0 marker and SQ,\n+\t * and forward to port.\n+\t */\n+\titems[0] = (struct rte_flow_item){\n+\t\t.type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_TAG,\n+\t\t.spec = ®_c0_spec,\n+\t\t.mask = ®_c0_mask,\n+\t};\n+\titems[1] = (struct rte_flow_item){\n+\t\t.type = (enum rte_flow_item_type)MLX5_RTE_FLOW_ITEM_TYPE_SQ,\n+\t\t.spec = &sq_spec,\n+\t};\n+\titems[2] = (struct rte_flow_item){\n+\t\t.type = RTE_FLOW_ITEM_TYPE_END,\n+\t};\n+\tactions[0] = (struct rte_flow_action){\n+\t\t.type = RTE_FLOW_ACTION_TYPE_REPRESENTED_PORT,\n+\t\t.conf = &port,\n+\t};\n+\tactions[1] = (struct rte_flow_action){\n+\t\t.type = RTE_FLOW_ACTION_TYPE_END,\n+\t};\n+\tret = flow_hw_create_ctrl_flow(dev, proxy_dev, proxy_priv->hw_esw_sq_miss_tbl,\n+\t\t\t\t items, 0, actions, 0);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Port %u failed to create HWS SQ miss flow rule for SQ %u, ret %d\",\n+\t\t\tport_id, sqn, ret);\n+\t\treturn ret;\n+\t}\n+\treturn 0;\n }\n \n int\n@@ -7899,17 +7889,24 @@ mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev)\n \n \tret = rte_flow_pick_transfer_proxy(port_id, &proxy_port_id, NULL);\n \tif (ret) {\n-\t\tDRV_LOG(ERR, \"Unable to pick proxy port for port %u\", port_id);\n+\t\tDRV_LOG(ERR, \"Unable to pick transfer proxy port for port %u. Transfer proxy \"\n+\t\t\t \"port must be present to create default FDB jump rule.\",\n+\t\t\t port_id);\n \t\treturn ret;\n \t}\n \tproxy_dev = &rte_eth_devices[proxy_port_id];\n \tproxy_priv = proxy_dev->data->dev_private;\n-\tif (!proxy_priv->dr_ctx)\n+\tif (!proxy_priv->dr_ctx) {\n+\t\tDRV_LOG(DEBUG, \"Transfer proxy port (port %u) of port %u must be configured \"\n+\t\t\t \"for HWS to create default FDB jump rule. Default rule will \"\n+\t\t\t \"not be created.\",\n+\t\t\t proxy_port_id, port_id);\n \t\treturn 0;\n+\t}\n \tif (!proxy_priv->hw_esw_zero_tbl) {\n-\t\tDRV_LOG(ERR, \"port %u proxy port %u was configured but default\"\n-\t\t\t\" flow tables are not created\",\n-\t\t\tport_id, proxy_port_id);\n+\t\tDRV_LOG(ERR, \"Transfer proxy port (port %u) of port %u was configured, but \"\n+\t\t\t \"default flow tables were not created.\",\n+\t\t\t proxy_port_id, port_id);\n \t\trte_errno = EINVAL;\n \t\treturn -rte_errno;\n \t}\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 2603196933..a973cbc5e3 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -426,7 +426,7 @@ mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,\n \t\t\tmlx5_txq_release(dev, peer_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n-\t\tpeer_info->qp_id = txq_ctrl->obj->sq->id;\n+\t\tpeer_info->qp_id = mlx5_txq_get_sqn(txq_ctrl);\n \t\tpeer_info->vhca_id = priv->sh->cdev->config.hca_attr.vhca_id;\n \t\t/* 1-to-1 mapping, only the first one is used. */\n \t\tpeer_info->peer_q = txq_ctrl->hairpin_conf.peers[0].queue;\n@@ -818,7 +818,7 @@ mlx5_hairpin_bind_single_port(struct rte_eth_dev *dev, uint16_t rx_port)\n \t\t}\n \t\t/* Pass TxQ's information to peer RxQ and try binding. */\n \t\tcur.peer_q = rx_queue;\n-\t\tcur.qp_id = txq_ctrl->obj->sq->id;\n+\t\tcur.qp_id = mlx5_txq_get_sqn(txq_ctrl);\n \t\tcur.vhca_id = priv->sh->cdev->config.hca_attr.vhca_id;\n \t\tcur.tx_explicit = txq_ctrl->hairpin_conf.tx_explicit;\n \t\tcur.manual_bind = txq_ctrl->hairpin_conf.manual_bind;\n@@ -1300,8 +1300,6 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev)\n \tint ret;\n \n \tif (priv->sh->config.dv_esw_en && priv->master) {\n-\t\tif (mlx5_flow_hw_esw_create_mgr_sq_miss_flow(dev))\n-\t\t\tgoto error;\n \t\tif (priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS)\n \t\t\tif (mlx5_flow_hw_create_tx_default_mreg_copy_flow(dev))\n \t\t\t\tgoto error;\n@@ -1312,10 +1310,7 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev)\n \n \t\tif (!txq)\n \t\t\tcontinue;\n-\t\tif (txq->is_hairpin)\n-\t\t\tqueue = txq->obj->sq->id;\n-\t\telse\n-\t\t\tqueue = txq->obj->sq_obj.sq->id;\n+\t\tqueue = mlx5_txq_get_sqn(txq);\n \t\tif ((priv->representor || priv->master) &&\n \t\t priv->sh->config.dv_esw_en) {\n \t\t\tif (mlx5_flow_hw_esw_create_sq_miss_flow(dev, queue)) {\n@@ -1325,9 +1320,15 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev)\n \t\t}\n \t\tmlx5_txq_release(dev, i);\n \t}\n-\tif ((priv->master || priv->representor) && priv->sh->config.dv_esw_en) {\n-\t\tif (mlx5_flow_hw_esw_create_default_jump_flow(dev))\n-\t\t\tgoto error;\n+\tif (priv->sh->config.fdb_def_rule) {\n+\t\tif ((priv->master || priv->representor) && priv->sh->config.dv_esw_en) {\n+\t\t\tif (!mlx5_flow_hw_esw_create_default_jump_flow(dev))\n+\t\t\t\tpriv->fdb_def_rule = 1;\n+\t\t\telse\n+\t\t\t\tgoto error;\n+\t\t}\n+\t} else {\n+\t\tDRV_LOG(INFO, \"port %u FDB default rule is disabled\", dev->data->port_id);\n \t}\n \treturn 0;\n error:\n@@ -1393,14 +1394,18 @@ mlx5_traffic_enable(struct rte_eth_dev *dev)\n \t\t txq_ctrl->hairpin_conf.tx_explicit == 0 &&\n \t\t txq_ctrl->hairpin_conf.peers[0].port ==\n \t\t priv->dev_data->port_id) {\n-\t\t\tret = mlx5_ctrl_flow_source_queue(dev, i);\n+\t\t\tret = mlx5_ctrl_flow_source_queue(dev,\n+\t\t\t\t\tmlx5_txq_get_sqn(txq_ctrl));\n \t\t\tif (ret) {\n \t\t\t\tmlx5_txq_release(dev, i);\n \t\t\t\tgoto error;\n \t\t\t}\n \t\t}\n \t\tif (priv->sh->config.dv_esw_en) {\n-\t\t\tif (mlx5_flow_create_devx_sq_miss_flow(dev, i) == 0) {\n+\t\t\tuint32_t q = mlx5_txq_get_sqn(txq_ctrl);\n+\n+\t\t\tif (mlx5_flow_create_devx_sq_miss_flow(dev, q) == 0) {\n+\t\t\t\tmlx5_txq_release(dev, i);\n \t\t\t\tDRV_LOG(ERR,\n \t\t\t\t\t\"Port %u Tx queue %u SQ create representor devx default miss rule failed.\",\n \t\t\t\t\tdev->data->port_id, i);\ndiff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h\nindex e0fc1872fe..6471ebf59f 100644\n--- a/drivers/net/mlx5/mlx5_tx.h\n+++ b/drivers/net/mlx5/mlx5_tx.h\n@@ -213,6 +213,7 @@ struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);\n int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);\n int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);\n int mlx5_txq_verify(struct rte_eth_dev *dev);\n+int mlx5_txq_get_sqn(struct mlx5_txq_ctrl *txq);\n void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);\n void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl);\n uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);\ndiff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c\nindex 9150ced72d..7a0f1d61a5 100644\n--- a/drivers/net/mlx5/mlx5_txq.c\n+++ b/drivers/net/mlx5/mlx5_txq.c\n@@ -27,6 +27,8 @@\n #include \"mlx5_tx.h\"\n #include \"mlx5_rxtx.h\"\n #include \"mlx5_autoconf.h\"\n+#include \"rte_pmd_mlx5.h\"\n+#include \"mlx5_flow.h\"\n \n /**\n * Allocate TX queue elements.\n@@ -1274,6 +1276,51 @@ mlx5_txq_verify(struct rte_eth_dev *dev)\n \treturn ret;\n }\n \n+int\n+mlx5_txq_get_sqn(struct mlx5_txq_ctrl *txq)\n+{\n+\treturn txq->is_hairpin ? txq->obj->sq->id : txq->obj->sq_obj.sq->id;\n+}\n+\n+int\n+rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num)\n+{\n+\tstruct rte_eth_dev *dev;\n+\tstruct mlx5_priv *priv;\n+\tuint32_t flow;\n+\n+\tif (rte_eth_dev_is_valid_port(port_id) < 0) {\n+\t\tDRV_LOG(ERR, \"There is no Ethernet device for port %u.\",\n+\t\t\tport_id);\n+\t\trte_errno = ENODEV;\n+\t\treturn -rte_errno;\n+\t}\n+\tdev = &rte_eth_devices[port_id];\n+\tpriv = dev->data->dev_private;\n+\tif ((!priv->representor && !priv->master) ||\n+\t !priv->sh->config.dv_esw_en) {\n+\t\tDRV_LOG(ERR, \"Port %u must be represetnor or master port in E-Switch mode.\",\n+\t\t\tport_id);\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\tif (sq_num == 0) {\n+\t\tDRV_LOG(ERR, \"Invalid SQ number.\");\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n+\tif (priv->sh->config.dv_flow_en == 2)\n+\t\treturn mlx5_flow_hw_esw_create_sq_miss_flow(dev, sq_num);\n+#endif\n+\tflow = mlx5_flow_create_devx_sq_miss_flow(dev, sq_num);\n+\tif (flow > 0)\n+\t\treturn 0;\n+\tDRV_LOG(ERR, \"Port %u failed to create default miss flow for SQ %u.\",\n+\t\tport_id, sq_num);\n+\treturn -rte_errno;\n+}\n+\n /**\n * Set the Tx queue dynamic timestamp (mask and offset)\n *\ndiff --git a/drivers/net/mlx5/rte_pmd_mlx5.h b/drivers/net/mlx5/rte_pmd_mlx5.h\nindex fbfdd9737b..d4caea5b20 100644\n--- a/drivers/net/mlx5/rte_pmd_mlx5.h\n+++ b/drivers/net/mlx5/rte_pmd_mlx5.h\n@@ -139,6 +139,23 @@ int rte_pmd_mlx5_external_rx_queue_id_unmap(uint16_t port_id,\n __rte_experimental\n int rte_pmd_mlx5_host_shaper_config(int port_id, uint8_t rate, uint32_t flags);\n \n+/**\n+ * Enable traffic for external SQ.\n+ *\n+ * @param[in] port_id\n+ * The port identifier of the Ethernet device.\n+ * @param[in] sq_num\n+ * SQ HW number.\n+ *\n+ * @return\n+ * 0 on success, a negative errno value otherwise and rte_errno is set.\n+ * Possible values for rte_errno:\n+ * - EINVAL - invalid sq_number or port type.\n+ * - ENODEV - there is no Ethernet device for this port id.\n+ */\n+__rte_experimental\n+int rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num);\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/drivers/net/mlx5/version.map b/drivers/net/mlx5/version.map\nindex 9942de5079..848270da13 100644\n--- a/drivers/net/mlx5/version.map\n+++ b/drivers/net/mlx5/version.map\n@@ -14,4 +14,5 @@ EXPERIMENTAL {\n \trte_pmd_mlx5_external_rx_queue_id_unmap;\n \t# added in 22.07\n \trte_pmd_mlx5_host_shaper_config;\n+\trte_pmd_mlx5_external_sq_enable;\n };\n", "prefixes": [ "v2", "16/17" ] }