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GET /api/patches/117012/?format=api
{ "id": 117012, "url": "http://patches.dpdk.org/api/patches/117012/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220928033130.9106-16-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220928033130.9106-16-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220928033130.9106-16-suanmingm@nvidia.com", "date": "2022-09-28T03:31:28", "name": "[v2,15/17] net/mlx5: support flow integrity in HWS group 0", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0ab997f11a5fb892897a861a7117c96cf60eedd0", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220928033130.9106-16-suanmingm@nvidia.com/mbox/", "series": [ { "id": 24870, "url": "http://patches.dpdk.org/api/series/24870/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24870", "date": "2022-09-28T03:31:15", "name": "net/mlx5: HW steering PMD update", "version": 2, "mbox": "http://patches.dpdk.org/series/24870/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/117012/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/117012/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 90C80A00C2;\n\tWed, 28 Sep 2022 05:34:14 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 6E3E542BC6;\n\tWed, 28 Sep 2022 05:32:39 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2063.outbound.protection.outlook.com [40.107.244.63])\n by mails.dpdk.org (Postfix) with ESMTP id CF8F242BB5\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>, <rasland@nvidia.com>, <orika@nvidia.com>, Gregory Etelson\n <getelson@nvidia.com>", "Subject": "[PATCH v2 15/17] net/mlx5: support flow integrity in HWS group 0", "Date": "Wed, 28 Sep 2022 06:31:28 +0300", "Message-ID": "<20220928033130.9106-16-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220928033130.9106-1-suanmingm@nvidia.com>", "References": "<20220923144334.27736-1-suanmingm@nvidia.com>\n <20220928033130.9106-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT063:EE_|BL3PR12MB6473:EE_", "X-MS-Office365-Filtering-Correlation-Id": "9714ea45-161d-48ba-c9a8-08daa1021573", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n JFhhIpIAIgZBAIUt/c7+KDJNEXY41gr0QLVJGGqS4PL2ku/lCel0IjK4zNB63o+RkSFRSN0V/qmerlozDVdmY9Hiqzx6iK6j0Y7oFHKD9nH4o9ez2Xd8A0AsBQlqS371gR7FreLbUX8t90AjgXkJQCW7w7jln+d/UR0Frc/Y1D5wuEbQaGwVWs+A2RMW+w4WQ1NNI1z1FwsWHT/ejJaPoINNR7K1sS8yRgss/BzuTOipqpd2hmb/9q1FPdV8xI7ua9wMs+p0rrbeZhZDU4pT1BS4yMXb95E2TIenBBgJQ9nxHWPGBWcHlBKlQCclaQyO3ggzeTyTUbw/Oe5f5CNUgddbkrqRSnoVxzy1sMLJSVKEt3koDZpCHUZH78CMjJwZAPEGb+qMMggZo9o3fdmf0mENyIF33T+7EuDBeuWfZqgzkk24uM2C8M5V/LgnY3UFLsi9E8WPl/9cea5/ZqVRwnzAhWwv2KCC412ngNMuPHYlhvHmQTbQS8pKpNxgB48fPKy+gJTxHJDVxi3ehC1EhtHPu26TMQ6BZjo9jQe/WHcrHnPfaHpMpz5YDTzjOihpByLcBk7AV1KubNHSRlohFxei58ITAl0a/DG63+eT/2FPNidfDPQl48W4nmkXzOFdBNcvVB9OyzYNlnLm8WJfoLrbqrUPWcfWFFx+7p8F+LaVO09ZPDXiSQ0sUs4+NVVdcrddPuWo8ocI0EkFaoDb+pIqj2gegV2qv39mBblOh6niXF73CXDexUHG1umrJVHGjPIVtLhqAHKrA8ZZpdk4piYUMQMJINLoUhf1Slk/yIA=", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; 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Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT063.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL3PR12MB6473", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Gregory Etelson <getelson@nvidia.com>\n\n- Reformat flow integrity item translation for HWS code.\n- Support flow integrity bits in HWS group 0.\n- Update integrity item translation to match positive semantics only.\nPositive flow semantics was described in patch [ae37c0f60c].\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 1 +\n drivers/net/mlx5/mlx5_flow_dv.c | 163 ++++++++++++++++----------------\n drivers/net/mlx5/mlx5_flow_hw.c | 8 ++\n 3 files changed, 90 insertions(+), 82 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex e45869a890..3f4aa080bb 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1462,6 +1462,7 @@ struct mlx5_dv_matcher_workspace {\n \tstruct mlx5_flow_rss_desc *rss_desc; /* RSS descriptor. */\n \tconst struct rte_flow_item *tunnel_item; /* Flow tunnel item. */\n \tconst struct rte_flow_item *gre_item; /* Flow GRE item. */\n+\tconst struct rte_flow_item *integrity_items[2];\n };\n \n struct mlx5_flow_split_info {\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 085cb23c78..758672568c 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -12636,132 +12636,121 @@ flow_dv_aso_age_params_init(struct rte_eth_dev *dev,\n \n static void\n flow_dv_translate_integrity_l4(const struct rte_flow_item_integrity *mask,\n-\t\t\t const struct rte_flow_item_integrity *value,\n-\t\t\t void *headers_m, void *headers_v)\n+\t\t\t void *headers)\n {\n+\t/*\n+\t * In HWS mode MLX5_ITEM_UPDATE() macro assigns the same pointer to\n+\t * both mask and value, therefore ether can be used.\n+\t * In SWS SW_V mode mask points to item mask and value points to item\n+\t * spec. Integrity item value is used only if matching mask is set.\n+\t * Use mask reference here to keep SWS functionality.\n+\t */\n \tif (mask->l4_ok) {\n \t\t/* RTE l4_ok filter aggregates hardware l4_ok and\n \t\t * l4_checksum_ok filters.\n \t\t * Positive RTE l4_ok match requires hardware match on both L4\n \t\t * hardware integrity bits.\n-\t\t * For negative match, check hardware l4_checksum_ok bit only,\n-\t\t * because hardware sets that bit to 0 for all packets\n-\t\t * with bad L4.\n+\t\t * PMD supports positive integrity item semantics only.\n \t\t */\n-\t\tif (value->l4_ok) {\n-\t\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_ok, 1);\n-\t\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_ok, 1);\n-\t\t}\n-\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);\n-\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,\n-\t\t\t !!value->l4_ok);\n-\t}\n-\tif (mask->l4_csum_ok) {\n-\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_m, l4_checksum_ok, 1);\n-\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_v, l4_checksum_ok,\n-\t\t\t value->l4_csum_ok);\n+\t\tMLX5_SET(fte_match_set_lyr_2_4, headers, l4_ok, 1);\n+\t\tMLX5_SET(fte_match_set_lyr_2_4, headers, l4_checksum_ok, 1);\n+\t} else if (mask->l4_csum_ok) {\n+\t\tMLX5_SET(fte_match_set_lyr_2_4, headers, l4_checksum_ok, 1);\n \t}\n }\n \n static void\n flow_dv_translate_integrity_l3(const struct rte_flow_item_integrity *mask,\n-\t\t\t const struct rte_flow_item_integrity *value,\n-\t\t\t void *headers_m, void *headers_v, bool is_ipv4)\n+\t\t\t void *headers, bool is_ipv4)\n {\n+\t/*\n+\t * In HWS mode MLX5_ITEM_UPDATE() macro assigns the same pointer to\n+\t * both mask and value, therefore ether can be used.\n+\t * In SWS SW_V mode mask points to item mask and value points to item\n+\t * spec. Integrity item value used only if matching mask is set.\n+\t * Use mask reference here to keep SWS functionality.\n+\t */\n \tif (mask->l3_ok) {\n \t\t/* RTE l3_ok filter aggregates for IPv4 hardware l3_ok and\n \t\t * ipv4_csum_ok filters.\n \t\t * Positive RTE l3_ok match requires hardware match on both L3\n \t\t * hardware integrity bits.\n-\t\t * For negative match, check hardware l3_csum_ok bit only,\n-\t\t * because hardware sets that bit to 0 for all packets\n-\t\t * with bad L3.\n+\t\t * PMD supports positive integrity item semantics only.\n \t\t */\n+\t\tMLX5_SET(fte_match_set_lyr_2_4, headers, l3_ok, 1);\n \t\tif (is_ipv4) {\n-\t\t\tif (value->l3_ok) {\n-\t\t\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_m,\n-\t\t\t\t\t l3_ok, 1);\n-\t\t\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_v,\n-\t\t\t\t\t l3_ok, 1);\n-\t\t\t}\n-\t\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_m,\n+\t\t\tMLX5_SET(fte_match_set_lyr_2_4, headers,\n \t\t\t\t ipv4_checksum_ok, 1);\n-\t\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_v,\n-\t\t\t\t ipv4_checksum_ok, !!value->l3_ok);\n-\t\t} else {\n-\t\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_m, l3_ok, 1);\n-\t\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_v, l3_ok,\n-\t\t\t\t value->l3_ok);\n \t\t}\n-\t}\n-\tif (mask->ipv4_csum_ok) {\n-\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_m, ipv4_checksum_ok, 1);\n-\t\tMLX5_SET(fte_match_set_lyr_2_4, headers_v, ipv4_checksum_ok,\n-\t\t\t value->ipv4_csum_ok);\n+\t} else if (is_ipv4 && mask->ipv4_csum_ok) {\n+\t\tMLX5_SET(fte_match_set_lyr_2_4, headers, ipv4_checksum_ok, 1);\n \t}\n }\n \n static void\n-set_integrity_bits(void *headers_m, void *headers_v,\n-\t\t const struct rte_flow_item *integrity_item, bool is_l3_ip4)\n+set_integrity_bits(void *headers, const struct rte_flow_item *integrity_item,\n+\t\t bool is_l3_ip4, uint32_t key_type)\n {\n-\tconst struct rte_flow_item_integrity *spec = integrity_item->spec;\n-\tconst struct rte_flow_item_integrity *mask = integrity_item->mask;\n+\tconst struct rte_flow_item_integrity *spec;\n+\tconst struct rte_flow_item_integrity *mask;\n \n \t/* Integrity bits validation cleared spec pointer */\n-\tMLX5_ASSERT(spec != NULL);\n-\tif (!mask)\n-\t\tmask = &rte_flow_item_integrity_mask;\n-\tflow_dv_translate_integrity_l3(mask, spec, headers_m, headers_v,\n-\t\t\t\t is_l3_ip4);\n-\tflow_dv_translate_integrity_l4(mask, spec, headers_m, headers_v);\n+\tif (MLX5_ITEM_VALID(integrity_item, key_type))\n+\t\treturn;\n+\tMLX5_ITEM_UPDATE(integrity_item, key_type, spec, mask,\n+\t\t\t &rte_flow_item_integrity_mask);\n+\tflow_dv_translate_integrity_l3(mask, headers, is_l3_ip4);\n+\tflow_dv_translate_integrity_l4(mask, headers);\n }\n \n static void\n-flow_dv_translate_item_integrity_post(void *matcher, void *key,\n+flow_dv_translate_item_integrity_post(void *key,\n \t\t\t\t const\n \t\t\t\t struct rte_flow_item *integrity_items[2],\n-\t\t\t\t uint64_t pattern_flags)\n+\t\t\t\t uint64_t pattern_flags, uint32_t key_type)\n {\n-\tvoid *headers_m, *headers_v;\n+\tvoid *headers;\n \tbool is_l3_ip4;\n \n \tif (pattern_flags & MLX5_FLOW_ITEM_INNER_INTEGRITY) {\n-\t\theaders_m = MLX5_ADDR_OF(fte_match_param, matcher,\n-\t\t\t\t\t inner_headers);\n-\t\theaders_v = MLX5_ADDR_OF(fte_match_param, key, inner_headers);\n+\t\theaders = MLX5_ADDR_OF(fte_match_param, key, inner_headers);\n \t\tis_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_INNER_L3_IPV4) !=\n \t\t\t 0;\n-\t\tset_integrity_bits(headers_m, headers_v,\n-\t\t\t\t integrity_items[1], is_l3_ip4);\n+\t\tset_integrity_bits(headers, integrity_items[1], is_l3_ip4,\n+\t\t\t\t key_type);\n \t}\n \tif (pattern_flags & MLX5_FLOW_ITEM_OUTER_INTEGRITY) {\n-\t\theaders_m = MLX5_ADDR_OF(fte_match_param, matcher,\n-\t\t\t\t\t outer_headers);\n-\t\theaders_v = MLX5_ADDR_OF(fte_match_param, key, outer_headers);\n+\t\theaders = MLX5_ADDR_OF(fte_match_param, key, outer_headers);\n \t\tis_l3_ip4 = (pattern_flags & MLX5_FLOW_LAYER_OUTER_L3_IPV4) !=\n \t\t\t 0;\n-\t\tset_integrity_bits(headers_m, headers_v,\n-\t\t\t\t integrity_items[0], is_l3_ip4);\n+\t\tset_integrity_bits(headers, integrity_items[0], is_l3_ip4,\n+\t\t\t\t key_type);\n \t}\n }\n \n-static void\n+static uint64_t\n flow_dv_translate_item_integrity(const struct rte_flow_item *item,\n-\t\t\t\t const struct rte_flow_item *integrity_items[2],\n-\t\t\t\t uint64_t *last_item)\n+\t\t\t\t struct mlx5_dv_matcher_workspace *wks,\n+\t\t\t\t uint64_t key_type)\n {\n-\tconst struct rte_flow_item_integrity *spec = (typeof(spec))item->spec;\n+\tif ((key_type & MLX5_SET_MATCHER_SW) != 0) {\n+\t\tconst struct rte_flow_item_integrity\n+\t\t\t*spec = (typeof(spec))item->spec;\n \n-\t/* integrity bits validation cleared spec pointer */\n-\tMLX5_ASSERT(spec != NULL);\n-\tif (spec->level > 1) {\n-\t\tintegrity_items[1] = item;\n-\t\t*last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;\n+\t\t/* SWS integrity bits validation cleared spec pointer */\n+\t\tif (spec->level > 1) {\n+\t\t\twks->integrity_items[1] = item;\n+\t\t\twks->last_item |= MLX5_FLOW_ITEM_INNER_INTEGRITY;\n+\t\t} else {\n+\t\t\twks->integrity_items[0] = item;\n+\t\t\twks->last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;\n+\t\t}\n \t} else {\n-\t\tintegrity_items[0] = item;\n-\t\t*last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;\n+\t\t/* HWS supports outer integrity only */\n+\t\twks->integrity_items[0] = item;\n+\t\twks->last_item |= MLX5_FLOW_ITEM_OUTER_INTEGRITY;\n \t}\n+\treturn wks->last_item;\n }\n \n /**\n@@ -13389,6 +13378,10 @@ flow_dv_translate_items(struct rte_eth_dev *dev,\n \t\tflow_dv_translate_item_meter_color(dev, key, items, key_type);\n \t\tlast_item = MLX5_FLOW_ITEM_METER_COLOR;\n \t\tbreak;\n+\tcase RTE_FLOW_ITEM_TYPE_INTEGRITY:\n+\t\tlast_item = flow_dv_translate_item_integrity(items,\n+\t\t\t\t\t\t\t wks, key_type);\n+\t\tbreak;\n \tdefault:\n \t\tbreak;\n \t}\n@@ -13452,6 +13445,12 @@ flow_dv_translate_items_hws(const struct rte_flow_item *items,\n \t\tif (ret)\n \t\t\treturn ret;\n \t}\n+\tif (wks.item_flags & MLX5_FLOW_ITEM_INTEGRITY) {\n+\t\tflow_dv_translate_item_integrity_post(key,\n+\t\t\t\t\t\t wks.integrity_items,\n+\t\t\t\t\t\t wks.item_flags,\n+\t\t\t\t\t\t key_type);\n+\t}\n \tif (wks.item_flags & MLX5_FLOW_LAYER_VXLAN_GPE) {\n \t\tflow_dv_translate_item_vxlan_gpe(key,\n \t\t\t\t\t\t wks.tunnel_item,\n@@ -13532,7 +13531,6 @@ flow_dv_translate_items_sws(struct rte_eth_dev *dev,\n \t\t\t mlx5_flow_get_thread_workspace())->rss_desc,\n \t};\n \tstruct mlx5_dv_matcher_workspace wks_m = wks;\n-\tconst struct rte_flow_item *integrity_items[2] = {NULL, NULL};\n \tint ret = 0;\n \tint tunnel;\n \n@@ -13543,10 +13541,6 @@ flow_dv_translate_items_sws(struct rte_eth_dev *dev,\n \t\t\t\t\t\t NULL, \"item not supported\");\n \t\ttunnel = !!(wks.item_flags & MLX5_FLOW_LAYER_TUNNEL);\n \t\tswitch (items->type) {\n-\t\tcase RTE_FLOW_ITEM_TYPE_INTEGRITY:\n-\t\t\tflow_dv_translate_item_integrity(items, integrity_items,\n-\t\t\t\t\t\t\t &wks.last_item);\n-\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_CONNTRACK:\n \t\t\tflow_dv_translate_item_aso_ct(dev, match_mask,\n \t\t\t\t\t\t match_value, items);\n@@ -13588,9 +13582,14 @@ flow_dv_translate_items_sws(struct rte_eth_dev *dev,\n \t\t\treturn -rte_errno;\n \t}\n \tif (wks.item_flags & MLX5_FLOW_ITEM_INTEGRITY) {\n-\t\tflow_dv_translate_item_integrity_post(match_mask, match_value,\n-\t\t\t\t\t\t integrity_items,\n-\t\t\t\t\t\t wks.item_flags);\n+\t\tflow_dv_translate_item_integrity_post(match_mask,\n+\t\t\t\t\t\t wks_m.integrity_items,\n+\t\t\t\t\t\t wks_m.item_flags,\n+\t\t\t\t\t\t MLX5_SET_MATCHER_SW_M);\n+\t\tflow_dv_translate_item_integrity_post(match_value,\n+\t\t\t\t\t\t wks.integrity_items,\n+\t\t\t\t\t\t wks.item_flags,\n+\t\t\t\t\t\t MLX5_SET_MATCHER_SW_V);\n \t}\n \tif (wks.item_flags & MLX5_FLOW_LAYER_VXLAN_GPE) {\n \t\tflow_dv_translate_item_vxlan_gpe(match_mask,\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 1879c8e9ca..31f98a2636 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -4618,6 +4618,14 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_ICMP6:\n \t\tcase RTE_FLOW_ITEM_TYPE_CONNTRACK:\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_INTEGRITY:\n+\t\t\t/*\n+\t\t\t * Integrity flow item validation require access to\n+\t\t\t * both item mask and spec.\n+\t\t\t * Current HWS model allows item mask in pattern\n+\t\t\t * template and item spec in flow rule.\n+\t\t\t */\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_END:\n \t\t\titems_end = true;\n \t\t\tbreak;\n", "prefixes": [ "v2", "15/17" ] }