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GET /api/patches/116923/?format=api
{ "id": 116923, "url": "http://patches.dpdk.org/api/patches/116923/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220927024756.947272-3-feifei.wang2@arm.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220927024756.947272-3-feifei.wang2@arm.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220927024756.947272-3-feifei.wang2@arm.com", "date": "2022-09-27T02:47:55", "name": "[v2,2/3] net/i40e: enable direct rearm mode", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "207fb2445dfc013c7cb9c4e98cbd1d9c886aae3e", "submitter": { "id": 1771, "url": "http://patches.dpdk.org/api/people/1771/?format=api", "name": "Feifei Wang", "email": "feifei.wang2@arm.com" }, "delegate": { "id": 319, "url": "http://patches.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220927024756.947272-3-feifei.wang2@arm.com/mbox/", "series": [ { "id": 24846, "url": "http://patches.dpdk.org/api/series/24846/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24846", "date": "2022-09-27T02:47:53", "name": "Direct re-arming of buffers on receive side", "version": 2, "mbox": "http://patches.dpdk.org/series/24846/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/116923/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/116923/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8EC91A00C2;\n\tTue, 27 Sep 2022 04:48:22 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5930B427ED;\n\tTue, 27 Sep 2022 04:48:18 +0200 (CEST)", "from foss.arm.com (foss.arm.com [217.140.110.172])\n by mails.dpdk.org (Postfix) with ESMTP id B4A8C427EC\n for <dev@dpdk.org>; Tue, 27 Sep 2022 04:48:16 +0200 (CEST)", "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D5B2E165C;\n Mon, 26 Sep 2022 19:48:22 -0700 (PDT)", "from net-x86-dell-8268.shanghai.arm.com\n (net-x86-dell-8268.shanghai.arm.com [10.169.210.116])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E245E3F73D;\n Mon, 26 Sep 2022 19:48:13 -0700 (PDT)" ], "From": "Feifei Wang <feifei.wang2@arm.com>", "To": "Yuying Zhang <Yuying.Zhang@intel.com>,\n Beilei Xing <beilei.xing@intel.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>", "Cc": "dev@dpdk.org, nd@arm.com, Feifei Wang <feifei.wang2@arm.com>,\n Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>", "Subject": "[PATCH v2 2/3] net/i40e: enable direct rearm mode", "Date": "Tue, 27 Sep 2022 10:47:55 +0800", "Message-Id": "<20220927024756.947272-3-feifei.wang2@arm.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220927024756.947272-1-feifei.wang2@arm.com>", "References": "<20220927024756.947272-1-feifei.wang2@arm.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "For i40e driver, enable direct re-arm mode. This patch supports the case\nof mapping Rx/Tx queues from the same single lcore.\n\nSuggested-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\nSigned-off-by: Feifei Wang <feifei.wang2@arm.com>\nReviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>\nReviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>\n---\n drivers/net/i40e/i40e_ethdev.c | 1 +\n drivers/net/i40e/i40e_ethdev.h | 2 +\n drivers/net/i40e/i40e_rxtx.c | 19 ++++++\n drivers/net/i40e/i40e_rxtx.h | 2 +\n drivers/net/i40e/i40e_rxtx_vec_neon.c | 93 +++++++++++++++++++++++++++\n 5 files changed, 117 insertions(+)", "diff": "diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex 65e689df32..649ec06f31 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -497,6 +497,7 @@ static const struct eth_dev_ops i40e_eth_dev_ops = {\n \t.flow_ops_get = i40e_dev_flow_ops_get,\n \t.rxq_info_get = i40e_rxq_info_get,\n \t.txq_info_get = i40e_txq_info_get,\n+\t.txq_data_get = i40e_txq_data_get,\n \t.rx_burst_mode_get = i40e_rx_burst_mode_get,\n \t.tx_burst_mode_get = i40e_tx_burst_mode_get,\n \t.timesync_enable = i40e_timesync_enable,\ndiff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h\nindex fe943a45ff..ee13730917 100644\n--- a/drivers/net/i40e/i40e_ethdev.h\n+++ b/drivers/net/i40e/i40e_ethdev.h\n@@ -1352,6 +1352,8 @@ void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,\n \tstruct rte_eth_rxq_info *qinfo);\n void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,\n \tstruct rte_eth_txq_info *qinfo);\n+void i40e_txq_data_get(struct rte_eth_dev *dev, uint16_t queue_id,\n+\tstruct rte_eth_txq_data *txq_data);\n int i40e_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,\n \t\t\t struct rte_eth_burst_mode *mode);\n int i40e_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t queue_id,\ndiff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c\nindex 788ffb51c2..be92ccd38a 100644\n--- a/drivers/net/i40e/i40e_rxtx.c\n+++ b/drivers/net/i40e/i40e_rxtx.c\n@@ -3197,6 +3197,24 @@ i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,\n \tqinfo->conf.offloads = txq->offloads;\n }\n \n+void\n+i40e_txq_data_get(struct rte_eth_dev *dev, uint16_t queue_id,\n+\t\t\tstruct rte_eth_txq_data *txq_data)\n+{\n+\tstruct i40e_tx_queue *txq;\n+\n+\ttxq = dev->data->tx_queues[queue_id];\n+\n+\ttxq_data->offloads = &txq->offloads;\n+\ttxq_data->tx_sw_ring = txq->sw_ring;\n+\ttxq_data->tx_ring = txq->tx_ring;\n+\ttxq_data->tx_next_dd = &txq->tx_next_dd;\n+\ttxq_data->nb_tx_free = &txq->nb_tx_free;\n+\ttxq_data->nb_tx_desc = txq->nb_tx_desc;\n+\ttxq_data->tx_rs_thresh = txq->tx_rs_thresh;\n+\ttxq_data->tx_free_thresh = txq->tx_free_thresh;\n+}\n+\n #ifdef RTE_ARCH_X86\n static inline bool\n get_avx_supported(bool request_avx512)\n@@ -3321,6 +3339,7 @@ i40e_set_rx_function(struct rte_eth_dev *dev)\n \t\t\tPMD_INIT_LOG(DEBUG, \"Using Vector Rx (port %d).\",\n \t\t\t\t dev->data->port_id);\n \t\t\tdev->rx_pkt_burst = i40e_recv_pkts_vec;\n+\t\t\tdev->rx_direct_rearm = i40e_direct_rearm_vec;\n \t\t}\n #endif /* RTE_ARCH_X86 */\n \t} else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {\ndiff --git a/drivers/net/i40e/i40e_rxtx.h b/drivers/net/i40e/i40e_rxtx.h\nindex 5e6eecc501..7a8fa2d1e8 100644\n--- a/drivers/net/i40e/i40e_rxtx.h\n+++ b/drivers/net/i40e/i40e_rxtx.h\n@@ -216,6 +216,8 @@ uint16_t i40e_simple_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t uint16_t nb_pkts);\n uint16_t i40e_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\tuint16_t nb_pkts);\n+uint16_t i40e_direct_rearm_vec(void *rx_queue,\n+\t\t\t struct rte_eth_txq_data *txq_data);\n int i40e_tx_queue_init(struct i40e_tx_queue *txq);\n int i40e_rx_queue_init(struct i40e_rx_queue *rxq);\n void i40e_free_tx_resources(struct i40e_tx_queue *txq);\ndiff --git a/drivers/net/i40e/i40e_rxtx_vec_neon.c b/drivers/net/i40e/i40e_rxtx_vec_neon.c\nindex 12e6f1cbcb..84e0159e08 100644\n--- a/drivers/net/i40e/i40e_rxtx_vec_neon.c\n+++ b/drivers/net/i40e/i40e_rxtx_vec_neon.c\n@@ -762,3 +762,96 @@ i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)\n {\n \treturn i40e_rx_vec_dev_conf_condition_check_default(dev);\n }\n+\n+uint16_t\n+i40e_direct_rearm_vec(void *rx_queue, struct rte_eth_txq_data *txq_data)\n+{\n+\tstruct i40e_rx_queue *rxq = rx_queue;\n+\tstruct i40e_rx_entry *rxep;\n+\tstruct i40e_tx_entry *txep;\n+\tvolatile union i40e_rx_desc *rxdp;\n+\tvolatile struct i40e_tx_desc *tx_ring;\n+\tstruct rte_mbuf *m;\n+\tuint16_t rx_id;\n+\tuint64x2_t dma_addr;\n+\tuint64_t paddr;\n+\tuint16_t i, n;\n+\tuint16_t nb_rearm;\n+\n+\tif (rxq->rxrearm_nb > txq_data->tx_rs_thresh &&\n+\t\t\t*txq_data->nb_tx_free < txq_data->tx_free_thresh) {\n+\t\ttx_ring = txq_data->tx_ring;\n+\t\t/* check DD bits on threshold descriptor */\n+\t\tif ((tx_ring[*txq_data->tx_next_dd].cmd_type_offset_bsz &\n+\t\t\t\trte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=\n+\t\t\t\trte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {\n+\t\t\treturn 0;\n+\t\t}\n+\t\tn = txq_data->tx_rs_thresh;\n+\n+\t\t/* first buffer to free from S/W ring is at index\n+\t\t * tx_next_dd - (tx_rs_thresh-1)\n+\t\t */\n+\t\ttxep = txq_data->tx_sw_ring;\n+\t\ttxep += *txq_data->tx_next_dd - (txq_data->tx_rs_thresh - 1);\n+\t\trxep = &rxq->sw_ring[rxq->rxrearm_start];\n+\t\trxdp = rxq->rx_ring + rxq->rxrearm_start;\n+\n+\t\tif (*txq_data->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) {\n+\t\t\t/* directly put mbufs from Tx to Rx,\n+\t\t\t * and initialize the mbufs in vector\n+\t\t\t */\n+\t\t\tfor (i = 0; i < n; i++, rxep++, txep++) {\n+\t\t\t\trxep[0].mbuf = txep[0].mbuf;\n+\n+\t\t\t\t/* Initialize rxdp descs */\n+\t\t\t\tm = txep[0].mbuf;\n+\t\t\t\tpaddr = m->buf_iova + RTE_PKTMBUF_HEADROOM;\n+\t\t\t\tdma_addr = vdupq_n_u64(paddr);\n+\t\t\t\t/* flush desc with pa dma_addr */\n+\t\t\t\tvst1q_u64((uint64_t *)&rxdp++->read, dma_addr);\n+\t\t\t}\n+\t\t} else {\n+\t\t\tfor (i = 0, nb_rearm = 0; i < n; i++) {\n+\t\t\t\tm = rte_pktmbuf_prefree_seg(txep[i].mbuf);\n+\t\t\t\tif (m != NULL) {\n+\t\t\t\t\trxep[i].mbuf = m;\n+\n+\t\t\t\t\t/* Initialize rxdp descs */\n+\t\t\t\t\tpaddr = m->buf_iova + RTE_PKTMBUF_HEADROOM;\n+\t\t\t\t\tdma_addr = vdupq_n_u64(paddr);\n+\t\t\t\t\t/* flush desc with pa dma_addr */\n+\t\t\t\t\tvst1q_u64((uint64_t *)&rxdp++->read, dma_addr);\n+\t\t\t\t\tnb_rearm++;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tn = nb_rearm;\n+\t\t}\n+\n+\t\t/* update counters for Tx */\n+\t\t*txq_data->nb_tx_free = *txq_data->nb_tx_free + txq_data->tx_rs_thresh;\n+\t\t*txq_data->tx_next_dd = *txq_data->tx_next_dd + txq_data->tx_rs_thresh;\n+\t\tif (*txq_data->tx_next_dd >= txq_data->nb_tx_desc)\n+\t\t\t*txq_data->tx_next_dd = txq_data->tx_rs_thresh - 1;\n+\n+\t\t/* Update the descriptor initializer index */\n+\t\trxq->rxrearm_start += n;\n+\t\trx_id = rxq->rxrearm_start - 1;\n+\n+\t\tif (unlikely(rxq->rxrearm_start >= rxq->nb_rx_desc)) {\n+\t\t\trxq->rxrearm_start = rxq->rxrearm_start - rxq->nb_rx_desc;\n+\t\t\tif (!rxq->rxrearm_start)\n+\t\t\t\trx_id = rxq->nb_rx_desc - 1;\n+\t\t\telse\n+\t\t\t\trx_id = rxq->rxrearm_start - 1;\n+\t\t}\n+\t\trxq->rxrearm_nb -= n;\n+\n+\t\trte_io_wmb();\n+\t\t/* Update the tail pointer on the NIC */\n+\t\tI40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rx_id);\n+\t\treturn n;\n+\t}\n+\n+\treturn 0;\n+}\n", "prefixes": [ "v2", "2/3" ] }