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GET /api/patches/116769/?format=api
{ "id": 116769, "url": "http://patches.dpdk.org/api/patches/116769/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220924005048.20302-5-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220924005048.20302-5-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220924005048.20302-5-nicolas.chautru@intel.com", "date": "2022-09-24T00:50:38", "name": "[v6,04/14] baseband/acc: introduce PMD for ACC200", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b59ce29bab59fe1d24ad1e96be50b8c5e6ede1f1", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220924005048.20302-5-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 24806, "url": "http://patches.dpdk.org/api/series/24806/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24806", "date": "2022-09-24T00:50:35", "name": "[v6,01/14] baseband/acc100: remove unused registers", "version": 6, "mbox": "http://patches.dpdk.org/series/24806/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/116769/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/116769/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E6935A054F;\n\tSat, 24 Sep 2022 02:51:25 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8E49042BEC;\n\tSat, 24 Sep 2022 02:51:00 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n by mails.dpdk.org (Postfix) with ESMTP id D9DE3400D4\n for <dev@dpdk.org>; Sat, 24 Sep 2022 02:50:54 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 Sep 2022 17:50:52 -0700", "from unknown (HELO icx-npg-scs1-cp1.localdomain) ([10.233.180.245])\n by FMSMGA003.fm.intel.com with ESMTP; 23 Sep 2022 17:50:52 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1663980655; x=1695516655;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=RuFGL3Whnjvy0C7nbTvuvC3XLGwYvGUSHEJvQC+rPyQ=;\n b=CeL/cCs9zve805v+htB6kZuEp+vxUUod/XLIigNWKKhc4zl27IoxuMgF\n +TNbg9lSg3JYJLvWEiX+yfhdxvCt09M5IUkIHGZ7/dCE5orNi5r7EbsKK\n +uu6fOfd9jtoXAe5vZtOlzA7JhAsmlg+VvsLfGLT8RPfQCDykNwi7IVCx\n 380WRsokVk8YJ2uLyEvE0N9H8wjBpEZJP99wYDH4kIXYU73d5a47fGEdB\n a+Dp6SYfSxRPMLXvJN8tyUxz3VqIbEFKFiy9SEooiOpf42ds+cwDQ1OdF\n zluRiCNmrOhRf3f4qZge6Q2yETKssPb84jqsf36sjaSzreieLsfWaTsGL g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6500,9779,10479\"; a=\"283839115\"", "E=Sophos;i=\"5.93,340,1654585200\"; d=\"scan'208\";a=\"283839115\"", "E=Sophos;i=\"5.93,340,1654585200\"; d=\"scan'208\";a=\"709504417\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tthomas@monjalon.net", "Cc": "maxime.coquelin@redhat.com, trix@redhat.com, mdr@ashroe.eu,\n bruce.richardson@intel.com, hemant.agrawal@nxp.com,\n david.marchand@redhat.com, stephen@networkplumber.org,\n hernan.vargas@intel.com, Nicolas Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v6 04/14] baseband/acc: introduce PMD for ACC200", "Date": "Fri, 23 Sep 2022 17:50:38 -0700", "Message-Id": "<20220924005048.20302-5-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.37.1", "In-Reply-To": "<20220924005048.20302-1-nicolas.chautru@intel.com>", "References": "<20220924005048.20302-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This patch introduces stubs for device driver for the ACC200\nintegrated VRAN accelerator on SPR-EEC\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n MAINTAINERS | 3 +\n doc/guides/bbdevs/acc200.rst | 244 ++++++++++++++++++++++++++\n doc/guides/bbdevs/index.rst | 1 +\n drivers/baseband/acc/acc200_pmd.h | 32 ++++\n drivers/baseband/acc/meson.build | 2 +-\n drivers/baseband/acc/rte_acc200_pmd.c | 144 +++++++++++++++\n 6 files changed, 425 insertions(+), 1 deletion(-)\n create mode 100644 doc/guides/bbdevs/acc200.rst\n create mode 100644 drivers/baseband/acc/acc200_pmd.h\n create mode 100644 drivers/baseband/acc/rte_acc200_pmd.c", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 52afd5d2e0..909c855048 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1340,6 +1340,9 @@ F: drivers/baseband/acc/\n F: doc/guides/bbdevs/acc100.rst\n F: doc/guides/bbdevs/features/acc100.ini\n F: doc/guides/bbdevs/features/acc101.ini\n+F: drivers/baseband/acc200/\n+F: doc/guides/bbdevs/acc200.rst\n+F: doc/guides/bbdevs/features/acc200.ini\n \n Null baseband\n M: Nicolas Chautru <nicolas.chautru@intel.com>\ndiff --git a/doc/guides/bbdevs/acc200.rst b/doc/guides/bbdevs/acc200.rst\nnew file mode 100644\nindex 0000000000..c5e1bd7890\n--- /dev/null\n+++ b/doc/guides/bbdevs/acc200.rst\n@@ -0,0 +1,244 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2022 Intel Corporation\n+\n+Intel(R) ACC200 vRAN Dedicated Accelerator Poll Mode Driver\n+===========================================================\n+\n+The Intel® vRAN Dedicated Accelerator ACC200 peripheral enables cost-effective 4G\n+and 5G next-generation virtualized Radio Access Network (vRAN) solutions integrated on\n+Sapphire Rapids EEC Intel(R)7 based Xeon(R) multi-core Serverprocessor.\n+\n+Features\n+--------\n+\n+The ACC200 includes a 5G Low Density Parity Check (LDPC) encoder/decoder, rate match/dematch,\n+Hybrid Automatic Repeat Request (HARQ) with access to DDR memory for buffer management, a 4G\n+Turbo encoder/decoder, a Fast Fourier Transform (FFT) block providing DFT/iDFT processing offload\n+for the 5G Sounding Reference Signal (SRS), a Queue Manager (QMGR), and a DMA subsystem.\n+There is no dedicated on-card memory for HARQ, this is using coherent memory on the CPU side.\n+\n+These correspond to the following features exposed by the PMD:\n+\n+- LDPC Encode in the Downlink (5GNR)\n+- LDPC Decode in the Uplink (5GNR)\n+- Turbo Encode in the Downlink (4G)\n+- Turbo Decode in the Uplink (4G)\n+- FFT processing\n+- SR-IOV with 16 VFs per PF\n+- Maximum of 256 queues per VF\n+- MSI\n+\n+ACC200 PMD supports the following BBDEV capabilities:\n+\n+* For the LDPC encode operation:\n+ - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)\n+ - ``RTE_BBDEV_LDPC_RATE_MATCH`` : if set then do not do Rate Match bypass\n+ - ``RTE_BBDEV_LDPC_INTERLEAVER_BYPASS`` : if set then bypass interleaver\n+\n+* For the LDPC decode operation:\n+ - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK`` : check CRC24B from CB(s)\n+ - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP`` : drops CRC24B bits appended while decoding\n+ - ``RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK`` : check CRC24A from CB(s)\n+ - ``RTE_BBDEV_LDPC_CRC_TYPE_16_CHECK`` : check CRC16 from CB(s)\n+ - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE`` : provides an input for HARQ combining\n+ - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE`` : provides an input for HARQ combining\n+ - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE`` : disable early termination\n+ - ``RTE_BBDEV_LDPC_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data\n+ - ``RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION`` : supports compression of the HARQ input/output\n+ - ``RTE_BBDEV_LDPC_LLR_COMPRESSION`` : supports LLR input compression\n+\n+* For the turbo encode operation:\n+ - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)\n+ - ``RTE_BBDEV_TURBO_RATE_MATCH`` : if set then do not do Rate Match bypass\n+ - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS`` : set for encoder dequeue interrupts\n+ - ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS`` : set to bypass RV index\n+ - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER`` : supports scatter-gather for input/output data\n+\n+* For the turbo decode operation:\n+ - ``RTE_BBDEV_TURBO_CRC_TYPE_24B`` : check CRC24B from CB(s)\n+ - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE`` : perform subblock de-interleave\n+ - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS`` : set for decoder dequeue interrupts\n+ - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN`` : set if negative LLR input is supported\n+ - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP`` : keep CRC24B bits appended while decoding\n+ - ``RTE_BBDEV_TURBO_DEC_CRC_24B_DROP`` : option to drop the code block CRC after decoding\n+ - ``RTE_BBDEV_TURBO_EARLY_TERMINATION`` : set early termination feature\n+ - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER`` : supports scatter-gather for input/output data\n+ - ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN`` : set half iteration granularity\n+ - ``RTE_BBDEV_TURBO_SOFT_OUTPUT`` : set the APP LLR soft output\n+ - ``RTE_BBDEV_TURBO_EQUALIZER`` : set the turbo equalizer feature\n+ - ``RTE_BBDEV_TURBO_SOFT_OUT_SATURATE`` : set the soft output saturation\n+ - ``RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH`` : set to run an extra odd iteration after CRC match\n+ - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT`` : set if negative APP LLR output supported\n+ - ``RTE_BBDEV_TURBO_MAP_DEC`` : supports flexible parallel MAP engine decoding\n+\n+Installation\n+------------\n+\n+Section 3 of the DPDK manual provides instructions on installing and compiling DPDK.\n+\n+DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.\n+The bbdev test application has been tested with a configuration 40 x 1GB hugepages. The\n+hugepage configuration of a server may be examined using:\n+\n+.. code-block:: console\n+\n+ grep Huge* /proc/meminfo\n+\n+\n+Initialization\n+--------------\n+\n+When the device first powers up, its PCI Physical Functions (PF) can be listed through these\n+commands for ACC200:\n+\n+.. code-block:: console\n+\n+ sudo lspci -vd8086:57c0\n+\n+The physical and virtual functions are compatible with Linux UIO drivers:\n+``vfio`` and ``igb_uio``. However, in order to work the 5G/4G\n+FEC device first needs to be bound to one of these linux drivers through DPDK.\n+\n+\n+Bind PF UIO driver(s)\n+~~~~~~~~~~~~~~~~~~~~~\n+\n+Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use\n+``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.\n+\n+The igb_uio driver may be bound to the PF PCI device using one of two methods for ACC200:\n+\n+\n+1. PCI functions (physical or virtual, depending on the use case) can be bound to\n+the UIO driver by repeating this command for every function.\n+\n+.. code-block:: console\n+\n+ cd <dpdk-top-level-directory>\n+ insmod ./build/kmod/igb_uio.ko\n+ echo \"8086 57c0\" > /sys/bus/pci/drivers/igb_uio/new_id\n+ lspci -vd8086:57c0\n+\n+\n+2. Another way to bind PF with DPDK UIO driver is by using the ``dpdk-devbind.py`` tool\n+\n+.. code-block:: console\n+\n+ cd <dpdk-top-level-directory>\n+ ./usertools/dpdk-devbind.py -b igb_uio 0000:f7:00.0\n+\n+where the PCI device ID (example: 0000:f7:00.0) is obtained using lspci -vd8086:57c0\n+\n+\n+In a similar way the PF may be bound with vfio-pci as any PCIe device.\n+\n+\n+Enable Virtual Functions\n+~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+Now, it should be visible in the printouts that PCI PF is under igb_uio control\n+\"``Kernel driver in use: igb_uio``\"\n+\n+To show the number of available VFs on the device, read ``sriov_totalvfs`` file..\n+\n+.. code-block:: console\n+\n+ cat /sys/bus/pci/devices/0000\\:<b>\\:<d>.<f>/sriov_totalvfs\n+\n+ where 0000\\:<b>\\:<d>.<f> is the PCI device ID\n+\n+\n+To enable VFs via igb_uio, echo the number of virtual functions intended to\n+enable to ``max_vfs`` file..\n+\n+.. code-block:: console\n+\n+ echo <num-of-vfs> > /sys/bus/pci/devices/0000\\:<b>\\:<d>.<f>/max_vfs\n+\n+\n+Afterwards, all VFs must be bound to appropriate UIO drivers as required, same\n+way it was done with the physical function previously.\n+\n+Enabling SR-IOV via vfio driver is pretty much the same, except that the file\n+name is different:\n+\n+.. code-block:: console\n+\n+ echo <num-of-vfs> > /sys/bus/pci/devices/0000\\:<b>\\:<d>.<f>/sriov_numvfs\n+\n+\n+Configure the VFs through PF\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+The PCI virtual functions must be configured before working or getting assigned\n+to VMs/Containers. The configuration involves allocating the number of hardware\n+queues, priorities, load balance, bandwidth and other settings necessary for the\n+device to perform FEC functions.\n+\n+This configuration needs to be executed at least once after reboot or PCI FLR and can\n+be achieved by using the functions ``rte_acc200_configure()``,\n+which sets up the parameters defined in the compatible ``acc200_conf`` structure.\n+\n+Test Application\n+----------------\n+\n+BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing\n+the functionality of the device, depending on the device's\n+capabilities. The test application is located under app->test-bbdev folder and has the\n+following options:\n+\n+.. code-block:: console\n+\n+ \"-p\", \"--testapp-path\": specifies path to the bbdev test app.\n+ \"-e\", \"--eal-params\"\t: EAL arguments which are passed to the test app.\n+ \"-t\", \"--timeout\"\t: Timeout in seconds (default=300).\n+ \"-c\", \"--test-cases\"\t: Defines test cases to run. Run all if not specified.\n+ \"-v\", \"--test-vector\"\t: Test vector path (default=dpdk_path+/app/test-bbdev/test_vectors/bbdev_null.data).\n+ \"-n\", \"--num-ops\"\t: Number of operations to process on device (default=32).\n+ \"-b\", \"--burst-size\"\t: Operations enqueue/dequeue burst size (default=32).\n+ \"-s\", \"--snr\"\t\t: SNR in dB used when generating LLRs for bler tests.\n+ \"-s\", \"--iter_max\"\t: Number of iterations for LDPC decoder.\n+ \"-l\", \"--num-lcores\"\t: Number of lcores to run (default=16).\n+ \"-i\", \"--init-device\" : Initialise PF device with default values.\n+\n+\n+To execute the test application tool using simple decode or encode data,\n+type one of the following:\n+\n+.. code-block:: console\n+\n+ ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data\n+ ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data\n+\n+\n+The test application ``test-bbdev.py``, supports the ability to configure the PF device with\n+a default set of values, if the \"-i\" or \"- -init-device\" option is included. The default values\n+are defined in test_bbdev_perf.c.\n+\n+\n+Test Vectors\n+~~~~~~~~~~~~\n+\n+In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides\n+a range of additional tests under the test_vectors folder, which may be useful. The results\n+of these tests will depend on the device capabilities which may cause some\n+testcases to be skipped, but no failure should be reported.\n+\n+\n+Alternate Baseband Device configuration tool\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+On top of the embedded configuration feature supported in test-bbdev using \"- -init-device\"\n+option mentioned above, there is also a tool available to perform that device configuration\n+using a companion application.\n+The ``pf_bb_config`` application notably enables then to run bbdev-test from the VF\n+and not only limited to the PF as captured above.\n+\n+See for more details: https://github.com/intel/pf-bb-config\n+\n+Specifically for the BBDEV ACC200 PMD, the command below can be used:\n+\n+.. code-block:: console\n+\n+ ./pf_bb_config ACC200 -c ./acc200/acc200_config_vf_5g.cfg\n+ ./test-bbdev.py -e=\"-c 0xff0 -a${VF_PCI_ADDR}\" -c validation -n 64 -b 64 -l 1 -v ./ldpc_dec_default.data\ndiff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst\nindex cedd706fa6..4e9dea8e4c 100644\n--- a/doc/guides/bbdevs/index.rst\n+++ b/doc/guides/bbdevs/index.rst\n@@ -14,4 +14,5 @@ Baseband Device Drivers\n fpga_lte_fec\n fpga_5gnr_fec\n acc100\n+ acc200\n la12xx\ndiff --git a/drivers/baseband/acc/acc200_pmd.h b/drivers/baseband/acc/acc200_pmd.h\nnew file mode 100644\nindex 0000000000..aaa6b7753c\n--- /dev/null\n+++ b/drivers/baseband/acc/acc200_pmd.h\n@@ -0,0 +1,32 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ */\n+\n+#ifndef _RTE_ACC200_PMD_H_\n+#define _RTE_ACC200_PMD_H_\n+\n+#include \"acc_common.h\"\n+\n+/* Helper macro for logging */\n+#define rte_bbdev_log(level, fmt, ...) \\\n+\trte_log(RTE_LOG_ ## level, acc200_logtype, fmt \"\\n\", \\\n+\t\t##__VA_ARGS__)\n+\n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+#define rte_bbdev_log_debug(fmt, ...) \\\n+\t\trte_bbdev_log(DEBUG, \"acc200_pmd: \" fmt, \\\n+\t\t##__VA_ARGS__)\n+#else\n+#define rte_bbdev_log_debug(fmt, ...)\n+#endif\n+\n+/* ACC200 PF and VF driver names */\n+#define ACC200PF_DRIVER_NAME intel_acc200_pf\n+#define ACC200VF_DRIVER_NAME intel_acc200_vf\n+\n+/* ACC200 PCI vendor & device IDs */\n+#define RTE_ACC200_VENDOR_ID (0x8086)\n+#define RTE_ACC200_PF_DEVICE_ID (0x57C0)\n+#define RTE_ACC200_VF_DEVICE_ID (0x57C1)\n+\n+#endif /* _RTE_ACC200_PMD_H_ */\ndiff --git a/drivers/baseband/acc/meson.build b/drivers/baseband/acc/meson.build\nindex 9a1a3b8b07..63912f0621 100644\n--- a/drivers/baseband/acc/meson.build\n+++ b/drivers/baseband/acc/meson.build\n@@ -3,6 +3,6 @@\n \n deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci']\n \n-sources = files('rte_acc100_pmd.c')\n+sources = files('rte_acc100_pmd.c', 'rte_acc200_pmd.c')\n \n headers = files('rte_acc100_cfg.h')\ndiff --git a/drivers/baseband/acc/rte_acc200_pmd.c b/drivers/baseband/acc/rte_acc200_pmd.c\nnew file mode 100644\nindex 0000000000..5554488280\n--- /dev/null\n+++ b/drivers/baseband/acc/rte_acc200_pmd.c\n@@ -0,0 +1,144 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ */\n+\n+#include <unistd.h>\n+\n+#include <rte_common.h>\n+#include <rte_log.h>\n+#include <rte_dev.h>\n+#include <rte_malloc.h>\n+#include <rte_mempool.h>\n+#include <rte_byteorder.h>\n+#include <rte_errno.h>\n+#include <rte_branch_prediction.h>\n+#include <rte_hexdump.h>\n+#include <rte_pci.h>\n+#include <rte_bus_pci.h>\n+#ifdef RTE_BBDEV_OFFLOAD_COST\n+#include <rte_cycles.h>\n+#endif\n+\n+#include <rte_bbdev.h>\n+#include <rte_bbdev_pmd.h>\n+#include \"acc200_pmd.h\"\n+\n+#ifdef RTE_LIBRTE_BBDEV_DEBUG\n+RTE_LOG_REGISTER_DEFAULT(acc200_logtype, DEBUG);\n+#else\n+RTE_LOG_REGISTER_DEFAULT(acc200_logtype, NOTICE);\n+#endif\n+\n+/* Free memory used for software rings */\n+static int\n+acc200_dev_close(struct rte_bbdev *dev)\n+{\n+\tRTE_SET_USED(dev);\n+\t/* Ensure all in flight HW transactions are completed */\n+\tusleep(ACC_LONG_WAIT);\n+\treturn 0;\n+}\n+\n+\n+static const struct rte_bbdev_ops acc200_bbdev_ops = {\n+\t.close = acc200_dev_close,\n+};\n+\n+/* ACC200 PCI PF address map */\n+static struct rte_pci_id pci_id_acc200_pf_map[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(RTE_ACC200_VENDOR_ID, RTE_ACC200_PF_DEVICE_ID)\n+\t},\n+\t{.device_id = 0},\n+};\n+\n+/* ACC200 PCI VF address map */\n+static struct rte_pci_id pci_id_acc200_vf_map[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(RTE_ACC200_VENDOR_ID, RTE_ACC200_VF_DEVICE_ID)\n+\t},\n+\t{.device_id = 0},\n+};\n+\n+/* Initialization Function */\n+static void\n+acc200_bbdev_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)\n+{\n+\tstruct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);\n+\n+\tdev->dev_ops = &acc200_bbdev_ops;\n+\n+\t((struct acc_device *) dev->data->dev_private)->pf_device =\n+\t\t\t!strcmp(drv->driver.name,\n+\t\t\t\t\tRTE_STR(ACC200PF_DRIVER_NAME));\n+\t((struct acc_device *) dev->data->dev_private)->mmio_base =\n+\t\t\tpci_dev->mem_resource[0].addr;\n+\n+\trte_bbdev_log_debug(\"Init device %s [%s] @ vaddr %p paddr %#\"PRIx64\"\",\n+\t\t\tdrv->driver.name, dev->data->name,\n+\t\t\t(void *)pci_dev->mem_resource[0].addr,\n+\t\t\tpci_dev->mem_resource[0].phys_addr);\n+}\n+\n+static int acc200_pci_probe(struct rte_pci_driver *pci_drv,\n+\tstruct rte_pci_device *pci_dev)\n+{\n+\tstruct rte_bbdev *bbdev = NULL;\n+\tchar dev_name[RTE_BBDEV_NAME_MAX_LEN];\n+\n+\tif (pci_dev == NULL) {\n+\t\trte_bbdev_log(ERR, \"NULL PCI device\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trte_pci_device_name(&pci_dev->addr, dev_name, sizeof(dev_name));\n+\n+\t/* Allocate memory to be used privately by drivers */\n+\tbbdev = rte_bbdev_allocate(pci_dev->device.name);\n+\tif (bbdev == NULL)\n+\t\treturn -ENODEV;\n+\n+\t/* allocate device private memory */\n+\tbbdev->data->dev_private = rte_zmalloc_socket(dev_name,\n+\t\t\tsizeof(struct acc_device), RTE_CACHE_LINE_SIZE,\n+\t\t\tpci_dev->device.numa_node);\n+\n+\tif (bbdev->data->dev_private == NULL) {\n+\t\trte_bbdev_log(CRIT,\n+\t\t\t\t\"Allocate of %zu bytes for device \\\"%s\\\" failed\",\n+\t\t\t\tsizeof(struct acc_device), dev_name);\n+\t\t\t\trte_bbdev_release(bbdev);\n+\t\t\treturn -ENOMEM;\n+\t}\n+\n+\t/* Fill HW specific part of device structure */\n+\tbbdev->device = &pci_dev->device;\n+\tbbdev->intr_handle = pci_dev->intr_handle;\n+\tbbdev->data->socket_id = pci_dev->device.numa_node;\n+\n+\t/* Invoke ACC200 device initialization function */\n+\tacc200_bbdev_init(bbdev, pci_drv);\n+\n+\trte_bbdev_log_debug(\"Initialised bbdev %s (id = %u)\",\n+\t\t\tdev_name, bbdev->data->dev_id);\n+\treturn 0;\n+}\n+\n+static struct rte_pci_driver acc200_pci_pf_driver = {\n+\t\t.probe = acc200_pci_probe,\n+\t\t.remove = acc_pci_remove,\n+\t\t.id_table = pci_id_acc200_pf_map,\n+\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING\n+};\n+\n+static struct rte_pci_driver acc200_pci_vf_driver = {\n+\t\t.probe = acc200_pci_probe,\n+\t\t.remove = acc_pci_remove,\n+\t\t.id_table = pci_id_acc200_vf_map,\n+\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING\n+};\n+\n+RTE_PMD_REGISTER_PCI(ACC200PF_DRIVER_NAME, acc200_pci_pf_driver);\n+RTE_PMD_REGISTER_PCI_TABLE(ACC200PF_DRIVER_NAME, pci_id_acc200_pf_map);\n+RTE_PMD_REGISTER_PCI(ACC200VF_DRIVER_NAME, acc200_pci_vf_driver);\n+RTE_PMD_REGISTER_PCI_TABLE(ACC200VF_DRIVER_NAME, pci_id_acc200_vf_map);\n", "prefixes": [ "v6", "04/14" ] }