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GET /api/patches/116756/?format=api
{ "id": 116756, "url": "http://patches.dpdk.org/api/patches/116756/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220923144334.27736-19-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220923144334.27736-19-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220923144334.27736-19-suanmingm@nvidia.com", "date": "2022-09-23T14:43:25", "name": "[18/27] net/mlx5: add meta item support in egress", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a2f60e21cec3344714c1fcfbdef38d6ecf777b06", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220923144334.27736-19-suanmingm@nvidia.com/mbox/", "series": [ { "id": 24805, "url": "http://patches.dpdk.org/api/series/24805/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24805", "date": "2022-09-23T14:43:07", "name": "net/mlx5: HW steering PMD update", "version": 1, "mbox": "http://patches.dpdk.org/series/24805/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/116756/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/116756/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 27C6EA054A;\n\tFri, 23 Sep 2022 16:46:41 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0AFEB42C1D;\n\tFri, 23 Sep 2022 16:44:42 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2064.outbound.protection.outlook.com [40.107.92.64])\n by mails.dpdk.org (Postfix) with ESMTP id 0D6E142BB3\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>, Dariusz Sosnowski <dsosnowski@nvidia.com>", "Subject": "[PATCH 18/27] net/mlx5: add meta item support in egress", "Date": "Fri, 23 Sep 2022 17:43:25 +0300", "Message-ID": "<20220923144334.27736-19-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220923144334.27736-1-suanmingm@nvidia.com>", "References": "<20220923144334.27736-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1NAM11FT026:EE_|BY5PR12MB4968:EE_", "X-MS-Office365-Filtering-Correlation-Id": "c096da16-689d-4684-dd68-08da9d722473", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n jkItnJbsPZG1DXsSeBTacNKbXB5bVQzE8GfLXyAsAJ99F/2MU2bVByZXn9xEAsl104Dcfl5GmFKMkYmEFTaQpjNfm5bHx5gMLPQFDTk0pBDV2xwlmDmI2csI2SgpANzXMuUdl4QsloKNCuH3/mypsOSTSpXIBn15h/TkF3PIlZ9NXPNT94bqB1Imrh0qYkaLINy4OkvJadN5JWAo3SkK+F2kBFipWf4HPfUNb9IlDw9iCU7RkYuJ48sNXa46QnXU2Z2KmuR6t2Rofuie26KpK1GihbPLoFZZsFSI60S4SmRP8gdKV2ZIGUqg8p0UdNW55OJ9UJ+1dyb/J1136eILeQw+SvmeI63Df+MI96JWI/mPrKjIU81GrKMNBms0Y+8p7aKcUPzokjqEXM9crXvdEl1WOyNIzZhZUSUppGT42MYPmhl4tmpeasEMkviWmLtF3r2ppUcGfSdcglD9PoXkFPpjqOAbH1DUlU+0feC/b71++gA8Ku+EAEIq/vsm8czEDTVIIAFCVyJ7fFGRPYorKNYsP56zQWlvr4RHVAACpCejQEN9tdJiYccLdXUQB0Ru2j9DHC/Ywj5SoEMGU4vTJj+gpBw+Jg/2YPalmClk/j9VNIswrLm2twuJkoKvp3njzYbVIhNKH0S084tLJmVp7WLyt9r4n5918swIr7xGNzIz1MGBe5dqFvgwiKCE0qMoH1Uzm/ndhAiQiZIPMh62zQlGbtyg4H6mU1USZIlisqdQm8y59fEuVu/m0tBNPsP+9KStbmW+htPzSVNEvIQsWX3Bd8j+86WEPJr497vf3wI=", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(396003)(136003)(39860400002)(346002)(376002)(451199015)(40470700004)(36840700001)(46966006)(186003)(356005)(82310400005)(6636002)(336012)(16526019)(7636003)(54906003)(110136005)(1076003)(47076005)(426003)(316002)(82740400003)(5660300002)(7696005)(40460700003)(4326008)(8676002)(107886003)(6666004)(478600001)(86362001)(55016003)(8936002)(36756003)(2616005)(26005)(2906002)(70206006)(70586007)(6286002)(40480700001)(83380400001)(41300700001)(36860700001)(21314003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Sep 2022 14:44:38.8189 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n c096da16-689d-4684-dd68-08da9d722473", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT026.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BY5PR12MB4968", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Dariusz Sosnowski <dsosnowski@nvidia.com>\n\nThis patch adds support for META item in HW Steering mode, in NIC TX\ndomain.\n\nDue to API limitations, usage of META item requires that all mlx5\nports use the same configuration of dv_esw_en and dv_xmeta_en device\narguments in order to consistently translate META item to appropriate\nregister. If mlx5 ports use different configurations, then configuration\nof the first probed device is used.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 1 +\n drivers/net/mlx5/mlx5.c | 4 ++-\n drivers/net/mlx5/mlx5_flow.h | 22 +++++++++++-\n drivers/net/mlx5/mlx5_flow_hw.c | 61 ++++++++++++++++++++++++++++++--\n 4 files changed, 84 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 41940d7ce7..54e7164663 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1563,6 +1563,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t}\n \t\t/* Only HWS requires this information. */\n \t\tflow_hw_init_tags_set(eth_dev);\n+\t\tflow_hw_init_flow_metadata_config(eth_dev);\n \t\tif (priv->sh->config.dv_esw_en &&\n \t\t flow_hw_create_vport_action(eth_dev)) {\n \t\t\tDRV_LOG(ERR, \"port %u failed to create vport action\",\ndiff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex 314176022a..87cbcd473d 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1970,8 +1970,10 @@ mlx5_dev_close(struct rte_eth_dev *dev)\n \tflow_hw_resource_release(dev);\n #endif\n \tflow_hw_clear_port_info(dev);\n-\tif (priv->sh->config.dv_flow_en == 2)\n+\tif (priv->sh->config.dv_flow_en == 2) {\n+\t\tflow_hw_clear_flow_metadata_config();\n \t\tflow_hw_clear_tags_set(dev);\n+\t}\n \tif (priv->rxq_privs != NULL) {\n \t\t/* XXX race condition if mlx5_rx_burst() is still running. */\n \t\trte_delay_us_sleep(1000);\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex a39dacc60a..dae2fe6b37 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1485,6 +1485,13 @@ flow_hw_get_wire_port(struct ibv_context *ibctx)\n \treturn NULL;\n }\n \n+extern uint32_t mlx5_flow_hw_flow_metadata_config_refcnt;\n+extern uint8_t mlx5_flow_hw_flow_metadata_esw_en;\n+extern uint8_t mlx5_flow_hw_flow_metadata_xmeta_en;\n+\n+void flow_hw_init_flow_metadata_config(struct rte_eth_dev *dev);\n+void flow_hw_clear_flow_metadata_config(void);\n+\n /*\n * Convert metadata or tag to the actual register.\n * META: Can only be used to match in the FDB in this stage, fixed C_1.\n@@ -1496,7 +1503,20 @@ flow_hw_get_reg_id(enum rte_flow_item_type type, uint32_t id)\n {\n \tswitch (type) {\n \tcase RTE_FLOW_ITEM_TYPE_META:\n-\t\treturn REG_C_1;\n+\t\tif (mlx5_flow_hw_flow_metadata_esw_en &&\n+\t\t mlx5_flow_hw_flow_metadata_xmeta_en == MLX5_XMETA_MODE_META32_HWS) {\n+\t\t\treturn REG_C_1;\n+\t\t}\n+\t\t/*\n+\t\t * On root table - PMD allows only egress META matching, thus\n+\t\t * REG_A matching is sufficient.\n+\t\t *\n+\t\t * On non-root tables - REG_A corresponds to general_purpose_lookup_field,\n+\t\t * which translates to REG_A in NIC TX and to REG_B in NIC RX.\n+\t\t * However, current FW does not implement REG_B case right now, so\n+\t\t * REG_B case should be rejected on pattern template validation.\n+\t\t */\n+\t\treturn REG_A;\n \tcase RTE_FLOW_ITEM_TYPE_TAG:\n \t\tMLX5_ASSERT(id < MLX5_FLOW_HW_TAGS_MAX);\n \t\treturn mlx5_flow_hw_avl_tags[id];\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex dfbc434d54..55a14d39eb 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -3332,7 +3332,6 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\t{\n \t\t\tconst struct rte_flow_item_tag *tag =\n \t\t\t\t(const struct rte_flow_item_tag *)items[i].spec;\n-\t\t\tstruct mlx5_priv *priv = dev->data->dev_private;\n \t\t\tuint8_t regcs = (uint8_t)priv->sh->cdev->config.hca_attr.set_reg_c;\n \n \t\t\tif (!((1 << (tag->index - REG_C_0)) & regcs))\n@@ -3349,6 +3348,17 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\t\t\t\t\t \"represented port item cannot be used\"\n \t\t\t\t\t\t \" when transfer attribute is set\");\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_META:\n+\t\t\tif (!priv->sh->config.dv_esw_en ||\n+\t\t\t priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_META32_HWS) {\n+\t\t\t\tif (attr->ingress)\n+\t\t\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_ITEM, NULL,\n+\t\t\t\t\t\t\t\t \"META item is not supported\"\n+\t\t\t\t\t\t\t\t \" on current FW with ingress\"\n+\t\t\t\t\t\t\t\t \" attribute\");\n+\t\t\t}\n+\t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_VOID:\n \t\tcase RTE_FLOW_ITEM_TYPE_ETH:\n \t\tcase RTE_FLOW_ITEM_TYPE_VLAN:\n@@ -3360,7 +3370,6 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_GTP_PSC:\n \t\tcase RTE_FLOW_ITEM_TYPE_VXLAN:\n \t\tcase MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE:\n-\t\tcase RTE_FLOW_ITEM_TYPE_META:\n \t\tcase RTE_FLOW_ITEM_TYPE_GRE:\n \t\tcase RTE_FLOW_ITEM_TYPE_GRE_KEY:\n \t\tcase RTE_FLOW_ITEM_TYPE_GRE_OPTION:\n@@ -4938,6 +4947,54 @@ void flow_hw_clear_tags_set(struct rte_eth_dev *dev)\n \t\t sizeof(enum modify_reg) * MLX5_FLOW_HW_TAGS_MAX);\n }\n \n+uint32_t mlx5_flow_hw_flow_metadata_config_refcnt;\n+uint8_t mlx5_flow_hw_flow_metadata_esw_en;\n+uint8_t mlx5_flow_hw_flow_metadata_xmeta_en;\n+\n+/**\n+ * Initializes static configuration of META flow items.\n+ *\n+ * As a temporary workaround, META flow item is translated to a register,\n+ * based on statically saved dv_esw_en and dv_xmeta_en device arguments.\n+ * It is a workaround for flow_hw_get_reg_id() where port specific information\n+ * is not available at runtime.\n+ *\n+ * Values of dv_esw_en and dv_xmeta_en device arguments are taken from the first opened port.\n+ * This means that each mlx5 port will use the same configuration for translation\n+ * of META flow items.\n+ *\n+ * @param[in] dev\n+ * Pointer to Ethernet device.\n+ */\n+void\n+flow_hw_init_flow_metadata_config(struct rte_eth_dev *dev)\n+{\n+\tuint32_t refcnt;\n+\n+\trefcnt = __atomic_fetch_add(&mlx5_flow_hw_flow_metadata_config_refcnt, 1,\n+\t\t\t\t __ATOMIC_RELAXED);\n+\tif (refcnt > 0)\n+\t\treturn;\n+\tmlx5_flow_hw_flow_metadata_esw_en = MLX5_SH(dev)->config.dv_esw_en;\n+\tmlx5_flow_hw_flow_metadata_xmeta_en = MLX5_SH(dev)->config.dv_xmeta_en;\n+}\n+\n+/**\n+ * Clears statically stored configuration related to META flow items.\n+ */\n+void\n+flow_hw_clear_flow_metadata_config(void)\n+{\n+\tuint32_t refcnt;\n+\n+\trefcnt = __atomic_sub_fetch(&mlx5_flow_hw_flow_metadata_config_refcnt, 1,\n+\t\t\t\t __ATOMIC_RELAXED);\n+\tif (refcnt > 0)\n+\t\treturn;\n+\tmlx5_flow_hw_flow_metadata_esw_en = 0;\n+\tmlx5_flow_hw_flow_metadata_xmeta_en = 0;\n+}\n+\n /**\n * Create shared action.\n *\n", "prefixes": [ "18/27" ] }