Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/116749/?format=api
{ "id": 116749, "url": "http://patches.dpdk.org/api/patches/116749/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220923144334.27736-13-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220923144334.27736-13-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220923144334.27736-13-suanmingm@nvidia.com", "date": "2022-09-23T14:43:19", "name": "[12/27] net/mlx5: support caching queue action", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "65831a409fedc966cfae57f40d9cedc82af835e5", "submitter": { "id": 1887, "url": "http://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220923144334.27736-13-suanmingm@nvidia.com/mbox/", "series": [ { "id": 24805, "url": "http://patches.dpdk.org/api/series/24805/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24805", "date": "2022-09-23T14:43:07", "name": "net/mlx5: HW steering PMD update", "version": 1, "mbox": "http://patches.dpdk.org/series/24805/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/116749/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/116749/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BFCC2A054A;\n\tFri, 23 Sep 2022 16:45:42 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3D3C542BD5;\n\tFri, 23 Sep 2022 16:44:24 +0200 (CEST)", "from NAM10-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam10on2044.outbound.protection.outlook.com [40.107.93.44])\n by mails.dpdk.org (Postfix) with ESMTP id 9EFC042BA7\n for <dev@dpdk.org>; Fri, 23 Sep 2022 16:44:22 +0200 (CEST)", "from DM6PR07CA0107.namprd07.prod.outlook.com (2603:10b6:5:330::21)\n by PH7PR12MB6908.namprd12.prod.outlook.com (2603:10b6:510:1ba::11) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.20; Fri, 23 Sep\n 2022 14:44:21 +0000", "from DM6NAM11FT023.eop-nam11.prod.protection.outlook.com\n (2603:10b6:5:330:cafe::4e) by DM6PR07CA0107.outlook.office365.com\n (2603:10b6:5:330::21) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.20 via Frontend\n Transport; Fri, 23 Sep 2022 14:44:20 +0000", "from mail.nvidia.com (216.228.117.160) by\n DM6NAM11FT023.mail.protection.outlook.com (10.13.173.96) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.5654.14 via Frontend Transport; Fri, 23 Sep 2022 14:44:20 +0000", "from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.26; Fri, 23 Sep\n 2022 07:44:10 -0700", "from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com\n (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 23 Sep\n 2022 07:44:09 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=XBqZXpnebg7DQe4W/zRHqCz4Vv3x3hHduXBjOp37yKsdLspSsk4bhjqGk8FdRBjKlrsRVClUPBRJ9MHeRF0CU19MoQ+z+N8Usj9xzoH2c/yWup5gIERKMBKoQZzBi78p9clzv5nTZ0R2moRXiyW5f4yB5OUOxDqsq3xu3RcyYwKFRGO0YCT/RKvYVNinH6tLNzErLJK9gwjs2rw8/0wVgkoqUsEwLybDPKDoG8eQMRd22IzbldS14fB3vsiLJOJWOFaMVnhKOsYa9j+NT9zt9L4ceP7TaXUyE7TyiOuhKXh4fFR+MsqlC7o12P0nLvYuy62mC09Az99j2RNOtBRHgA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=gxW2BWl8L0iHSCNYymMnCQWyXhkLGJ4106Lah57kfWU=;\n b=j64UznfbNvMyF76AytIJfQRB3BLXSOb4Vrm/NQtIdrYDeH97t68ilMSP+wq3wknrtSrKauBr+AuMiOniWlVbVprQ2+SPM6L+4bBm7mPXB5x/i3rU1GqxbkE/9QHST6w9U0l2OjBKKTbRtfYZezw9KCit32ZyKOzbtGFLoFO1KxHyJNd23BrNWU5xUVY0GkDaXvRzz0bVrZ8AfgVOHBlVz83VyyTXrQT0xuYcxHnQrw8UlxVsmSBTNBnm0KwZiK4LZVfhtd0JcaQW7u9RwC8JE6NUkv7YU0iV3WjUgcD5GeRL201u+PCWjOBDUAtPzUEwht5RFSJ5T3MHMxFz7j03bQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=gxW2BWl8L0iHSCNYymMnCQWyXhkLGJ4106Lah57kfWU=;\n b=VEzyxLALajaUP9N2+/Bm+yciKKHhGstWRYdlXiw3lQhMOxrSyzbzUFcDN21HJQn8BjVEPoTmREKw/9IIcsBFLm785SG1CvTz8L8hldWQOdhspb+g0g0OqcTkrlX/UjD3LYUoSfsNyhK8dGyx4NHlKRL3PpnPk1nRKgXyL0nqpdDdXY06FuiloULpUM/wZwfoTeIVoCtr1Vs2s/1m89ppacXIr/avSEHLQKKCVECjxRkWobjZabOUN+r70TK5i+lQm0tb7aw2E2Wkds4/YkV4/mA4h8zEA8mc96dlronOIxTY0KcYKaNcwjIu3ptCSiKVWqgQpfl71CwJQVQ4e50iCg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 12/27] net/mlx5: support caching queue action", "Date": "Fri, 23 Sep 2022 17:43:19 +0300", "Message-ID": "<20220923144334.27736-13-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20220923144334.27736-1-suanmingm@nvidia.com>", "References": "<20220923144334.27736-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail201.nvidia.com (10.129.68.8) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM6NAM11FT023:EE_|PH7PR12MB6908:EE_", "X-MS-Office365-Filtering-Correlation-Id": "6da7db85-fa5a-4d29-7605-08da9d721990", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n EDrE8o6k9MryiPjjaaX9ouzmvFGSMDkHBtq2x6ZMgB9Yp7CBc5KI7JnJnl5Mfa+HjLX5CagMQn9eAx4YkKwfH8JdfcbNUl2W3Cl/BLItex+xCEQ3jcB74GVIYR4gnVBK/PDkxgDJI3E/dT1i8gALdr3wEW353NED9UrmmcWBbP+N57A1pCNg7G/JAiR8QLJIciQCA6qBe7sFWvkmYbrrGVeeyYDNH08VDJn5PYmU0W3lmmM0lErFX0meNWnN0TGEetSkga7iiT8cnmRqfoLAuwO1OGXs+YZqfkqlS2utXJrBDLtnVAqkww30P92DbCyaODwz7hC9gSKoxMMm81MlI1+SelSgwB0tsrsWq/8oMWCHwR1DeVuH3OD7weHZMcw3EVO9pVZ5vtkEj6ISD7Ru4XRD45eOUVB2m75nZVx7+RR/mt6TsS3Ymg1DEGaB7ZVtYSWf/Ok0vKFz0uluZlTKyZJ+U0NOd0JTX8e9mfBxZ/TpOW9+pH4RvYJ+kIG8w/svGZwAc1Lq62ckrEj74kL8PklDnuhsP8rZF7I06i4YNgelvogCkg6Pr1CujeGAHke4G07Z/S+41+gKhnaoLCO0OrwUTNjoX0vMNDsKAzRVgLgoHjguJLBtKVfWYFeLqpmyqjrhg7RAiOvXgvGywTCgtNZhq96NUDakFxSasfIamPw5NGKqJnTYTv1d9JguOUmFq7z26dvwO2UkRZMa18MH1kEO1d3uurWoYPaf2138lrd59vLiqLvbJX0C4zlL8abVKysBuzIJCY11Y4QHsNaJPAlzbjB2wbNfsx+Cp2R2ZzI=", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230022)(4636009)(376002)(396003)(346002)(39860400002)(136003)(451199015)(40470700004)(36840700001)(46966006)(82310400005)(478600001)(2616005)(6636002)(2906002)(5660300002)(356005)(16526019)(70586007)(336012)(70206006)(40460700003)(186003)(1076003)(8676002)(7696005)(316002)(110136005)(6666004)(26005)(426003)(47076005)(36756003)(6286002)(40480700001)(55016003)(83380400001)(4326008)(36860700001)(8936002)(7636003)(82740400003)(41300700001)(86362001)(309714004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "23 Sep 2022 14:44:20.5670 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 6da7db85-fa5a-4d29-7605-08da9d721990", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT023.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB6908", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "If the port is stopped, the Rx queue data will also be destroyed. At that\ntime, create table with RSS action would be failed due to lack of Rx queue\ndata.\n\nThis commit adds the cache of queue create operation while port stopped.\nIn case port is stopped, add tables to the ongoing list first, then do\naction translate only when port starts.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5.h | 2 +\n drivers/net/mlx5/mlx5_flow.h | 2 +\n drivers/net/mlx5/mlx5_flow_hw.c | 95 +++++++++++++++++++++++++++++----\n drivers/net/mlx5/mlx5_trigger.c | 8 +++\n 4 files changed, 97 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 8d82c68569..be60038810 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1643,6 +1643,8 @@ struct mlx5_priv {\n \tstruct mlx5dr_action *hw_drop[2];\n \t/* HW steering global tag action. */\n \tstruct mlx5dr_action *hw_tag[2];\n+\t/* HW steering create ongoing rte flow table list header. */\n+\tLIST_HEAD(flow_hw_tbl_ongo, rte_flow_template_table) flow_hw_tbl_ongo;\n \tstruct mlx5_indexed_pool *acts_ipool; /* Action data indexed pool. */\n \tstruct mlx5_hws_cnt_pool *hws_cpool; /* HW steering's counter pool. */\n #endif\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex cdea4076d8..746cf439fc 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -2398,4 +2398,6 @@ int mlx5_flow_pattern_validate(struct rte_eth_dev *dev,\n \t\tconst struct rte_flow_pattern_template_attr *attr,\n \t\tconst struct rte_flow_item items[],\n \t\tstruct rte_flow_error *error);\n+int flow_hw_table_update(struct rte_eth_dev *dev,\n+\t\t\t struct rte_flow_error *error);\n #endif /* RTE_PMD_MLX5_FLOW_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 8891f4a4e3..fe40b02c49 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -992,11 +992,11 @@ flow_hw_cnt_compile(struct rte_eth_dev *dev, uint32_t start_pos,\n * Table on success, NULL otherwise and rte_errno is set.\n */\n static int\n-flow_hw_actions_translate(struct rte_eth_dev *dev,\n-\t\t\t const struct mlx5_flow_template_table_cfg *cfg,\n-\t\t\t struct mlx5_hw_actions *acts,\n-\t\t\t struct rte_flow_actions_template *at,\n-\t\t\t struct rte_flow_error *error)\n+__flow_hw_actions_translate(struct rte_eth_dev *dev,\n+\t\t\t const struct mlx5_flow_template_table_cfg *cfg,\n+\t\t\t struct mlx5_hw_actions *acts,\n+\t\t\t struct rte_flow_actions_template *at,\n+\t\t\t struct rte_flow_error *error)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tconst struct rte_flow_template_table_attr *table_attr = &cfg->attr;\n@@ -1309,6 +1309,40 @@ flow_hw_actions_translate(struct rte_eth_dev *dev,\n \t\t\t\t \"fail to create rte table\");\n }\n \n+/**\n+ * Translate rte_flow actions to DR action.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[in] tbl\n+ * Pointer to the flow template table.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, negative value otherwise and rte_errno is set.\n+ */\n+static int\n+flow_hw_actions_translate(struct rte_eth_dev *dev,\n+\t\t\t struct rte_flow_template_table *tbl,\n+\t\t\t struct rte_flow_error *error)\n+{\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < tbl->nb_action_templates; i++) {\n+\t\tif (__flow_hw_actions_translate(dev, &tbl->cfg,\n+\t\t\t\t\t\t&tbl->ats[i].acts,\n+\t\t\t\t\t\ttbl->ats[i].action_template,\n+\t\t\t\t\t\terror))\n+\t\t\tgoto err;\n+\t}\n+\treturn 0;\n+err:\n+\twhile (i--)\n+\t\t__flow_hw_action_template_destroy(dev, &tbl->ats[i].acts);\n+\treturn -1;\n+}\n+\n /**\n * Get shared indirect action.\n *\n@@ -1837,6 +1871,10 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev,\n \tuint32_t acts_num, flow_idx;\n \tint ret;\n \n+\tif (unlikely((!dev->data->dev_started))) {\n+\t\trte_errno = EINVAL;\n+\t\tgoto error;\n+\t}\n \tif (unlikely(!priv->hw_q[queue].job_idx)) {\n \t\trte_errno = ENOMEM;\n \t\tgoto error;\n@@ -2231,6 +2269,7 @@ flow_hw_table_create(struct rte_eth_dev *dev,\n \tstruct mlx5_list_entry *ge;\n \tuint32_t i, max_tpl = MLX5_HW_TBL_MAX_ITEM_TEMPLATE;\n \tuint32_t nb_flows = rte_align32pow2(attr->nb_flows);\n+\tbool port_started = !!dev->data->dev_started;\n \tint err;\n \n \t/* HWS layer accepts only 1 item template with root table. */\n@@ -2295,21 +2334,26 @@ flow_hw_table_create(struct rte_eth_dev *dev,\n \t\t\trte_errno = EINVAL;\n \t\t\tgoto at_error;\n \t\t}\n+\t\ttbl->ats[i].action_template = action_templates[i];\n \t\tLIST_INIT(&tbl->ats[i].acts.act_list);\n-\t\terr = flow_hw_actions_translate(dev, &tbl->cfg,\n-\t\t\t\t\t\t&tbl->ats[i].acts,\n-\t\t\t\t\t\taction_templates[i], error);\n+\t\tif (!port_started)\n+\t\t\tcontinue;\n+\t\terr = __flow_hw_actions_translate(dev, &tbl->cfg,\n+\t\t\t\t\t\t &tbl->ats[i].acts,\n+\t\t\t\t\t\t action_templates[i], error);\n \t\tif (err) {\n \t\t\ti++;\n \t\t\tgoto at_error;\n \t\t}\n-\t\ttbl->ats[i].action_template = action_templates[i];\n \t}\n \ttbl->nb_action_templates = nb_action_templates;\n \ttbl->type = attr->flow_attr.transfer ? MLX5DR_TABLE_TYPE_FDB :\n \t\t (attr->flow_attr.egress ? MLX5DR_TABLE_TYPE_NIC_TX :\n \t\t MLX5DR_TABLE_TYPE_NIC_RX);\n-\tLIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);\n+\tif (port_started)\n+\t\tLIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);\n+\telse\n+\t\tLIST_INSERT_HEAD(&priv->flow_hw_tbl_ongo, tbl, next);\n \treturn tbl;\n at_error:\n \twhile (i--) {\n@@ -2339,6 +2383,33 @@ flow_hw_table_create(struct rte_eth_dev *dev,\n \treturn NULL;\n }\n \n+/**\n+ * Update flow template table.\n+ *\n+ * @param[in] dev\n+ * Pointer to the rte_eth_dev structure.\n+ * @param[out] error\n+ * Pointer to error structure.\n+ *\n+ * @return\n+ * 0 on success, negative value otherwise and rte_errno is set.\n+ */\n+int\n+flow_hw_table_update(struct rte_eth_dev *dev,\n+\t\t struct rte_flow_error *error)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct rte_flow_template_table *tbl;\n+\n+\twhile ((tbl = LIST_FIRST(&priv->flow_hw_tbl_ongo)) != NULL) {\n+\t\tif (flow_hw_actions_translate(dev, tbl, error))\n+\t\t\treturn -1;\n+\t\tLIST_REMOVE(tbl, next);\n+\t\tLIST_INSERT_HEAD(&priv->flow_hw_tbl, tbl, next);\n+\t}\n+\treturn 0;\n+}\n+\n /**\n * Translates group index specified by the user in @p attr to internal\n * group index.\n@@ -4440,6 +4511,10 @@ flow_hw_resource_release(struct rte_eth_dev *dev)\n \tif (!priv->dr_ctx)\n \t\treturn;\n \tflow_hw_flush_all_ctrl_flows(dev);\n+\twhile (!LIST_EMPTY(&priv->flow_hw_tbl_ongo)) {\n+\t\ttbl = LIST_FIRST(&priv->flow_hw_tbl_ongo);\n+\t\tflow_hw_table_destroy(dev, tbl, NULL);\n+\t}\n \twhile (!LIST_EMPTY(&priv->flow_hw_tbl)) {\n \t\ttbl = LIST_FIRST(&priv->flow_hw_tbl);\n \t\tflow_hw_table_destroy(dev, tbl, NULL);\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex 9e458356a0..ab2b83a870 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -1170,6 +1170,14 @@ mlx5_dev_start(struct rte_eth_dev *dev)\n \t\t\tdev->data->port_id, rte_strerror(rte_errno));\n \t\tgoto error;\n \t}\n+\tif (priv->sh->config.dv_flow_en == 2) {\n+\t\tret = flow_hw_table_update(dev, NULL);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(ERR, \"port %u failed to update HWS tables\",\n+\t\t\t\tdev->data->port_id);\n+\t\t\tgoto error;\n+\t\t}\n+\t}\n \tret = mlx5_traffic_enable(dev);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"port %u failed to set defaults flows\",\n", "prefixes": [ "12/27" ] }