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GET /api/patches/116101/?format=api
{ "id": 116101, "url": "http://patches.dpdk.org/api/patches/116101/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220908181503.7584-1-bhagyada.modali@amd.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220908181503.7584-1-bhagyada.modali@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220908181503.7584-1-bhagyada.modali@amd.com", "date": "2022-09-08T18:15:03", "name": "[v2] net/axgbe: support segmented Tx", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6e633e4bbaadf06814a650b1eae58a39d509a3c3", "submitter": { "id": 2826, "url": "http://patches.dpdk.org/api/people/2826/?format=api", "name": "Bhagyada Modali", "email": "bhagyada.modali@amd.com" }, "delegate": { "id": 3961, "url": "http://patches.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220908181503.7584-1-bhagyada.modali@amd.com/mbox/", "series": [ { "id": 24611, "url": "http://patches.dpdk.org/api/series/24611/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24611", "date": "2022-09-08T18:15:03", "name": "[v2] net/axgbe: support segmented Tx", "version": 2, "mbox": "http://patches.dpdk.org/series/24611/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/116101/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/116101/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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b=0hwzWC4q7o+fBNbMd7Zl4JqDjY406ztvs1uwlz5U3S/X8OPKcXjEq3pznsW1wRIvTmiUvI0eTPjaA2WbW7Nesddt19r6iRlJfxL19th/Lw9hz8feZ3kleKyS4T8tu5DA7hvZppBJvyDGQv9yV/12XRHIO4mJr4XHLyVkpyBxKbc=", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 165.204.84.17)\n smtp.mailfrom=amd.com; dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=amd.com;", "Received-SPF": "Pass (protection.outlook.com: domain of amd.com designates\n 165.204.84.17 as permitted sender) receiver=protection.outlook.com;\n client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C", "From": "Bhagyada Modali <bhagyada.modali@amd.com>", "To": "<chandu@amd.com>, <ferruh.yigit@amd.com>", "CC": "<dev@dpdk.org>, <stable@dpdk.org>, Bhagyada Modali\n <bhagyada.modali@amd.com>", "Subject": "[PATCH v2] net/axgbe: support segmented Tx", "Date": "Thu, 8 Sep 2022 14:15:03 -0400", "Message-ID": "<20220908181503.7584-1-bhagyada.modali@amd.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": 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0nz1hvhq1OKVigR+kXpAjWlWFptAuR/LW1jqDoRpB5yY6TZIQiphQ+H6SoAfLK745O3dKQIlrYljWCsd80TIHH4QHS4AoOxgZTpzziSR1+qn7kVWkpftRnLimEMoiw43+IEOnkJgHNDi6UsW7h7CCi/ZgmTMUIhe48qYQbvoFSxfhxkoPwzj0zl6HUUGNM7PkePqBwuPMecBiU+K8hxz4qmt/rp9XQfjA54OxD3sHdNLYYVZq+mF4UKZGiy66za/ot6w/0+yvD4nliyfl1HtrQ7YWRxNbycSF+x1IQiv6w8rFJiCv+8ZttpMerQHf/MdH+tfHAclQgPTQBFoGNBG/skv1QlPm+MORSpZHc4pxvjcbUuMPoilY71hCPyYPDoEaH9qUEAoOjJcZpRotOClziZz8p6ieX6xmanJeVYslshoFdwdY3ku/XWWyjlREQrJ3pyOtf/mx/ltwikD1cAgduTs2Rq08VjJBKy/yRfl9UnbN2BM83BT6p0vGz+lY/YKNATfhimKZSskDL+P3QsuV5krXWb2fnYDBKWSxlOihJxVOVEugtT/WWCTOT30Q2UT9080Tk6z9JBpGU7Wwoeoxev5PDx0TDySmdpDLE0e4b4U5Gxg2yPuMPcvqXgYCtVPc8GZBzNCy2gAjfaBZku0azh37R7YzZuCbaX2A7rQvnBSgF7DBYPOicoPax9fKsJmFRRC5jj/BMJJHpBWElUnYfWiSiOyP+A9ohfb2LO6zSkpo9vKCPPOBVM4DWvieG//xHJTE7QZi4nAoUhCv8bVq5pGKh1iGNgQ/amQdOgva4/9AU1QueALGqZSdgyKXWa7", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE;\n SFS:(13230016)(4636009)(39860400002)(346002)(136003)(396003)(376002)(40470700004)(36840700001)(46966006)(6666004)(7696005)(82740400003)(36756003)(86362001)(426003)(83380400001)(36860700001)(336012)(16526019)(26005)(1076003)(186003)(82310400005)(47076005)(316002)(5660300002)(2616005)(110136005)(478600001)(54906003)(40480700001)(8936002)(6636002)(4326008)(40460700003)(81166007)(70586007)(2906002)(70206006)(8676002)(356005)(41300700001)(450100002)(44832011)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Sep 2022 18:15:59.5761 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ca39fd90-b95b-433b-117a-08da91c62e8a", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17];\n Helo=[SATLEXMB04.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT021.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB6087", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Enable segmented tx support and add jumbo packet transmit capability\n\nSigned-off-by: Bhagyada Modali <bhagyada.modali@amd.com>\n---\n drivers/net/axgbe/axgbe_ethdev.c | 1 +\n drivers/net/axgbe/axgbe_ethdev.h | 1 +\n drivers/net/axgbe/axgbe_rxtx.c | 213 ++++++++++++++++++++++++++++++-\n drivers/net/axgbe/axgbe_rxtx.h | 4 +\n 4 files changed, 218 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c\nindex e6822fa711..b071e4e460 100644\n--- a/drivers/net/axgbe/axgbe_ethdev.c\n+++ b/drivers/net/axgbe/axgbe_ethdev.c\n@@ -1228,6 +1228,7 @@ axgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\tRTE_ETH_TX_OFFLOAD_VLAN_INSERT |\n \t\tRTE_ETH_TX_OFFLOAD_QINQ_INSERT |\n \t\tRTE_ETH_TX_OFFLOAD_IPV4_CKSUM |\n+\t\tRTE_ETH_TX_OFFLOAD_MULTI_SEGS |\n \t\tRTE_ETH_TX_OFFLOAD_UDP_CKSUM |\n \t\tRTE_ETH_TX_OFFLOAD_TCP_CKSUM;\n \ndiff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h\nindex e06d40f9eb..7f19321d88 100644\n--- a/drivers/net/axgbe/axgbe_ethdev.h\n+++ b/drivers/net/axgbe/axgbe_ethdev.h\n@@ -582,6 +582,7 @@ struct axgbe_port {\n \tunsigned int tx_pbl;\n \tunsigned int tx_osp_mode;\n \tunsigned int tx_max_fifo_size;\n+\tunsigned int multi_segs_tx;\n \n \t/* Rx settings */\n \tunsigned int rx_sf_mode;\ndiff --git a/drivers/net/axgbe/axgbe_rxtx.c b/drivers/net/axgbe/axgbe_rxtx.c\nindex 8b43e8160b..881ffa01db 100644\n--- a/drivers/net/axgbe/axgbe_rxtx.c\n+++ b/drivers/net/axgbe/axgbe_rxtx.c\n@@ -544,6 +544,7 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \tunsigned int tsize;\n \tconst struct rte_memzone *tz;\n \tuint64_t offloads;\n+\tstruct rte_eth_dev_data *dev_data = dev->data;\n \n \ttx_desc = nb_desc;\n \tpdata = dev->data->dev_private;\n@@ -611,7 +612,13 @@ int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \tif (!pdata->tx_queues)\n \t\tpdata->tx_queues = dev->data->tx_queues;\n \n-\tif (txq->vector_disable ||\n+\tif ((dev_data->dev_conf.txmode.offloads &\n+\t\t\t\tRTE_ETH_TX_OFFLOAD_MULTI_SEGS))\n+\t\tpdata->multi_segs_tx = true;\n+\n+\tif (pdata->multi_segs_tx)\n+\t\tdev->tx_pkt_burst = &axgbe_xmit_pkts_seg;\n+\telse if (txq->vector_disable ||\n \t\t\trte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128)\n \t\tdev->tx_pkt_burst = &axgbe_xmit_pkts;\n \telse\n@@ -762,6 +769,29 @@ void axgbe_dev_enable_tx(struct rte_eth_dev *dev)\n \tAXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);\n }\n \n+/* Free Tx conformed mbufs segments */\n+static void\n+axgbe_xmit_cleanup_seg(struct axgbe_tx_queue *txq)\n+{\n+\tvolatile struct axgbe_tx_desc *desc;\n+\tuint16_t idx;\n+\n+\tidx = AXGBE_GET_DESC_IDX(txq, txq->dirty);\n+\twhile (txq->cur != txq->dirty) {\n+\t\tif (unlikely(idx == txq->nb_desc))\n+\t\t\tidx = 0;\n+\t\tdesc = &txq->desc[idx];\n+\t\t/* Check for ownership */\n+\t\tif (AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN))\n+\t\t\treturn;\n+\t\tmemset((void *)&desc->desc2, 0, 8);\n+\t\t/* Free mbuf */\n+\t\trte_pktmbuf_free_seg(txq->sw_ring[idx]);\n+\t\ttxq->sw_ring[idx++] = NULL;\n+\t\ttxq->dirty++;\n+\t}\n+}\n+\n /* Free Tx conformed mbufs */\n static void axgbe_xmit_cleanup(struct axgbe_tx_queue *txq)\n {\n@@ -854,6 +884,187 @@ static int axgbe_xmit_hw(struct axgbe_tx_queue *txq,\n \treturn 0;\n }\n \n+/* Tx Descriptor formation for segmented mbuf\n+ * Each mbuf will require multiple descriptors\n+ */\n+\n+static int\n+axgbe_xmit_hw_seg(struct axgbe_tx_queue *txq,\n+\t\tstruct rte_mbuf *mbuf)\n+{\n+\tvolatile struct axgbe_tx_desc *desc;\n+\tuint16_t idx;\n+\tuint64_t mask;\n+\tint start_index;\n+\tuint32_t pkt_len = 0;\n+\tint nb_desc_free;\n+\tstruct rte_mbuf *tx_pkt;\n+\n+\tnb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);\n+\n+\tif (mbuf->nb_segs > nb_desc_free) {\n+\t\taxgbe_xmit_cleanup_seg(txq);\n+\t\tnb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);\n+\t\tif (unlikely(mbuf->nb_segs > nb_desc_free))\n+\t\t\treturn RTE_ETH_TX_DESC_UNAVAIL;\n+\t}\n+\n+\tidx = AXGBE_GET_DESC_IDX(txq, txq->cur);\n+\tdesc = &txq->desc[idx];\n+\t/* Saving the start index for setting the OWN bit finally */\n+\tstart_index = idx;\n+\n+\ttx_pkt = mbuf;\n+\t/* Max_pkt len = 9018 ; need to update it according to Jumbo pkt size */\n+\tpkt_len = tx_pkt->pkt_len;\n+\n+\t/* Update buffer address and length */\n+\tdesc->baddr = rte_mbuf_data_iova(tx_pkt);\n+\tAXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, HL_B1L,\n+\t\t\t\t\t tx_pkt->data_len);\n+\t/* Total msg length to transmit */\n+\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL,\n+\t\t\t\t\t tx_pkt->pkt_len);\n+\t/* Timestamp enablement check */\n+\tif (mbuf->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST)\n+\t\tAXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, TTSE, 1);\n+\n+\trte_wmb();\n+\t/* Mark it as First Descriptor */\n+\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1);\n+\t/* Mark it as a NORMAL descriptor */\n+\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CTXT, 0);\n+\t/* configure h/w Offload */\n+\tmask = mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK;\n+\tif (mask == RTE_MBUF_F_TX_TCP_CKSUM || mask == RTE_MBUF_F_TX_UDP_CKSUM)\n+\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x3);\n+\telse if (mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM)\n+\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x1);\n+\trte_wmb();\n+\n+\tif (mbuf->ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) {\n+\t\t/* Mark it as a CONTEXT descriptor */\n+\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,\n+\t\t\t\tCTXT, 1);\n+\t\t/* Set the VLAN tag */\n+\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,\n+\t\t\t\tVT, mbuf->vlan_tci);\n+\t\t/* Indicate this descriptor contains the VLAN tag */\n+\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3,\n+\t\t\t\tVLTV, 1);\n+\t\tAXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, VTIR,\n+\t\t\t\tTX_NORMAL_DESC2_VLAN_INSERT);\n+\t} else {\n+\t\tAXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, VTIR, 0x0);\n+\t}\n+\trte_wmb();\n+\n+\t/* Save mbuf */\n+\ttxq->sw_ring[idx] = tx_pkt;\n+\t/* Update current index*/\n+\ttxq->cur++;\n+\n+\ttx_pkt = tx_pkt->next;\n+\n+\twhile (tx_pkt != NULL) {\n+\t\tidx = AXGBE_GET_DESC_IDX(txq, txq->cur);\n+\t\tdesc = &txq->desc[idx];\n+\n+\t\t/* Update buffer address and length */\n+\t\tdesc->baddr = rte_mbuf_data_iova(tx_pkt);\n+\n+\t\tAXGMAC_SET_BITS_LE(desc->desc2,\n+\t\t\t\tTX_NORMAL_DESC2, HL_B1L, tx_pkt->data_len);\n+\n+\t\trte_wmb();\n+\n+\t\t/* Mark it as a NORMAL descriptor */\n+\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CTXT, 0);\n+\t\t/* configure h/w Offload */\n+\t\tmask = mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK;\n+\t\tif (mask == RTE_MBUF_F_TX_TCP_CKSUM ||\n+\t\t\t\tmask == RTE_MBUF_F_TX_UDP_CKSUM)\n+\t\t\tAXGMAC_SET_BITS_LE(desc->desc3,\n+\t\t\t\t\tTX_NORMAL_DESC3, CIC, 0x3);\n+\t\telse if (mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM)\n+\t\t\tAXGMAC_SET_BITS_LE(desc->desc3,\n+\t\t\t\t\tTX_NORMAL_DESC3, CIC, 0x1);\n+\n+\t\trte_wmb();\n+\n+\t\t /* Set OWN bit */\n+\t\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1);\n+\t\trte_wmb();\n+\n+\t\t/* Save mbuf */\n+\t\ttxq->sw_ring[idx] = tx_pkt;\n+\t\t/* Update current index*/\n+\t\ttxq->cur++;\n+\n+\t\ttx_pkt = tx_pkt->next;\n+\t}\n+\n+\t/* Set LD bit for the last descriptor */\n+\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1);\n+\trte_wmb();\n+\n+\t/* Update stats */\n+\ttxq->bytes += pkt_len;\n+\n+\t/* Set OWN bit for the first descriptor */\n+\tdesc = &txq->desc[start_index];\n+\tAXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1);\n+\trte_wmb();\n+\n+\treturn 0;\n+}\n+\n+/* Eal supported tx wrapper- Segmented*/\n+uint16_t\n+axgbe_xmit_pkts_seg(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\tuint16_t nb_pkts)\n+{\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\tstruct axgbe_tx_queue *txq;\n+\tuint16_t nb_desc_free;\n+\tuint16_t nb_pkt_sent = 0;\n+\tuint16_t idx;\n+\tuint32_t tail_addr;\n+\tstruct rte_mbuf *mbuf = NULL;\n+\n+\tif (unlikely(nb_pkts == 0))\n+\t\treturn nb_pkts;\n+\n+\ttxq = (struct axgbe_tx_queue *)tx_queue;\n+\n+\tnb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);\n+\tif (unlikely(nb_desc_free <= txq->free_thresh)) {\n+\t\taxgbe_xmit_cleanup_seg(txq);\n+\t\tnb_desc_free = txq->nb_desc - (txq->cur - txq->dirty);\n+\t\tif (unlikely(nb_desc_free == 0))\n+\t\t\treturn 0;\n+\t}\n+\n+\twhile (nb_pkts--) {\n+\t\tmbuf = *tx_pkts++;\n+\n+\t\tif (axgbe_xmit_hw_seg(txq, mbuf))\n+\t\t\tgoto out;\n+\t\tnb_pkt_sent++;\n+\t}\n+out:\n+\t/* Sync read and write */\n+\trte_mb();\n+\tidx = AXGBE_GET_DESC_IDX(txq, txq->cur);\n+\ttail_addr = low32_value(txq->ring_phys_addr +\n+\t\t\t\tidx * sizeof(struct axgbe_tx_desc));\n+\t/* Update tail reg with next immediate address to kick Tx DMA channel*/\n+\tAXGMAC_DMA_IOWRITE(txq, DMA_CH_TDTR_LO, tail_addr);\n+\ttxq->pkts += nb_pkt_sent;\n+\treturn nb_pkt_sent;\n+}\n+\n /* Eal supported tx wrapper*/\n uint16_t\n axgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\ndiff --git a/drivers/net/axgbe/axgbe_rxtx.h b/drivers/net/axgbe/axgbe_rxtx.h\nindex 2a330339cd..c19d6d9db1 100644\n--- a/drivers/net/axgbe/axgbe_rxtx.h\n+++ b/drivers/net/axgbe/axgbe_rxtx.h\n@@ -167,6 +167,10 @@ int axgbe_dev_fw_version_get(struct rte_eth_dev *eth_dev,\n \n uint16_t axgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t uint16_t nb_pkts);\n+\n+uint16_t axgbe_xmit_pkts_seg(void *tx_queue, struct rte_mbuf **tx_pkts,\n+\t\tuint16_t nb_pkts);\n+\n uint16_t axgbe_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t uint16_t nb_pkts);\n \n", "prefixes": [ "v2" ] }