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{
    "id": 115071,
    "url": "http://patches.dpdk.org/api/patches/115071/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220815073206.2917968-44-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220815073206.2917968-44-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220815073206.2917968-44-qi.z.zhang@intel.com",
    "date": "2022-08-15T07:31:39",
    "name": "[v2,43/70] net/ice/base: move functions",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "8909262a5aa39486d1b1135763309e7ecc9e05ba",
    "submitter": {
        "id": 504,
        "url": "http://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220815073206.2917968-44-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 24308,
            "url": "http://patches.dpdk.org/api/series/24308/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24308",
            "date": "2022-08-15T07:30:56",
            "name": "ice base code update",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/24308/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/115071/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/115071/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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        "X-IronPort-AV": [
            "E=McAfee;i=\"6400,9594,10439\"; a=\"291857991\"",
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            "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"635283230\""
        ],
        "X-ExtLoop1": "1",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "qiming.yang@intel.com",
        "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Jacob Keller <jacob.e.keller@intel.com>",
        "Subject": "[PATCH v2 43/70] net/ice/base: move functions",
        "Date": "Mon, 15 Aug 2022 03:31:39 -0400",
        "Message-Id": "<20220815073206.2917968-44-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.31.1",
        "In-Reply-To": "<20220815073206.2917968-1-qi.z.zhang@intel.com>",
        "References": "<20220815071306.2910599-1-qi.z.zhang@intel.com>\n <20220815073206.2917968-1-qi.z.zhang@intel.com>",
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        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Move function ice_ptp_set_vernier_wl and ice_ptp_src_cmd to align with\nkernel driver.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_ptp_hw.c | 130 +++++++++++++++---------------\n 1 file changed, 66 insertions(+), 64 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex 712b7dedfb..dfb9d08224 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -381,6 +381,47 @@ static enum ice_status ice_init_cgu_e822(struct ice_hw *hw)\n \treturn ICE_SUCCESS;\n }\n \n+/**\n+ * ice_ptp_src_cmd - Prepare source timer for a timer command\n+ * @hw: pointer to HW structure\n+ * @cmd: Timer command\n+ *\n+ * Prepare the source timer for an upcoming timer sync command.\n+ */\n+void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)\n+{\n+\tu32 cmd_val;\n+\tu8 tmr_idx;\n+\n+\ttmr_idx = ice_get_ptp_src_clock_index(hw);\n+\tcmd_val = tmr_idx << SEL_CPK_SRC;\n+\n+\tswitch (cmd) {\n+\tcase ICE_PTP_INIT_TIME:\n+\t\tcmd_val |= GLTSYN_CMD_INIT_TIME;\n+\t\tbreak;\n+\tcase ICE_PTP_INIT_INCVAL:\n+\t\tcmd_val |= GLTSYN_CMD_INIT_INCVAL;\n+\t\tbreak;\n+\tcase ICE_PTP_ADJ_TIME:\n+\t\tcmd_val |= GLTSYN_CMD_ADJ_TIME;\n+\t\tbreak;\n+\tcase ICE_PTP_ADJ_TIME_AT_TIME:\n+\t\tcmd_val |= GLTSYN_CMD_ADJ_INIT_TIME;\n+\t\tbreak;\n+\tcase ICE_PTP_READ_TIME:\n+\t\tcmd_val |= GLTSYN_CMD_READ_TIME;\n+\t\tbreak;\n+\tcase ICE_PTP_NOP:\n+\t\tbreak;\n+\tdefault:\n+\t\tice_warn(hw, \"Unknown timer command %u\\n\", cmd);\n+\t\treturn;\n+\t}\n+\n+\twr32(hw, GLTSYN_CMD, cmd_val);\n+}\n+\n /**\n  * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands\n  * @hw: pointer to HW struct\n@@ -2365,6 +2406,31 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)\n \treturn ICE_SUCCESS;\n }\n \n+/**\n+ * ice_ptp_set_vernier_wl - Set the window length for vernier calibration\n+ * @hw: pointer to the HW struct\n+ *\n+ * Set the window length used for the vernier port calibration process.\n+ */\n+enum ice_status ice_ptp_set_vernier_wl(struct ice_hw *hw)\n+{\n+\tu8 port;\n+\n+\tfor (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {\n+\t\tenum ice_status status;\n+\n+\t\tstatus = ice_write_phy_reg_e822_lp(hw, port, P_REG_WL,\n+\t\t\t\t\t\t   PTP_VERNIER_WL, true);\n+\t\tif (status) {\n+\t\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to set vernier window length for port %u, status %d\\n\",\n+\t\t\t\t  port, status);\n+\t\t\treturn status;\n+\t\t}\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n /**\n  * ice_ptp_init_phc_e822 - Perform E822 specific PHC initialization\n  * @hw: pointer to HW struct\n@@ -2817,31 +2883,6 @@ ice_ptp_port_cmd_e822(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,\n  * port.\n  */\n \n-/**\n- * ice_ptp_set_vernier_wl - Set the window length for vernier calibration\n- * @hw: pointer to the HW struct\n- *\n- * Set the window length used for the vernier port calibration process.\n- */\n-enum ice_status ice_ptp_set_vernier_wl(struct ice_hw *hw)\n-{\n-\tu8 port;\n-\n-\tfor (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {\n-\t\tenum ice_status status;\n-\n-\t\tstatus = ice_write_phy_reg_e822_lp(hw, port, P_REG_WL,\n-\t\t\t\t\t\t   PTP_VERNIER_WL, true);\n-\t\tif (status) {\n-\t\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to set vernier window length for port %u, status %d\\n\",\n-\t\t\t\t  port, status);\n-\t\t\treturn status;\n-\t\t}\n-\t}\n-\n-\treturn ICE_SUCCESS;\n-}\n-\n /**\n  * ice_phy_get_speed_and_fec_e822 - Get link speed and FEC based on serdes mode\n  * @hw: pointer to HW struct\n@@ -4829,45 +4870,6 @@ void ice_ptp_unlock(struct ice_hw *hw)\n \twr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);\n }\n \n-/**\n- * ice_ptp_src_cmd - Prepare source timer for a timer command\n- * @hw: pointer to HW structure\n- * @cmd: Timer command\n- *\n- * Prepare the source timer for an upcoming timer sync command.\n- */\n-void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)\n-{\n-\tu32 cmd_val;\n-\tu8 tmr_idx;\n-\n-\ttmr_idx = ice_get_ptp_src_clock_index(hw);\n-\tcmd_val = tmr_idx << SEL_CPK_SRC;\n-\n-\tswitch (cmd) {\n-\tcase ICE_PTP_INIT_TIME:\n-\t\tcmd_val |= GLTSYN_CMD_INIT_TIME;\n-\t\tbreak;\n-\tcase ICE_PTP_INIT_INCVAL:\n-\t\tcmd_val |= GLTSYN_CMD_INIT_INCVAL;\n-\t\tbreak;\n-\tcase ICE_PTP_ADJ_TIME:\n-\t\tcmd_val |= GLTSYN_CMD_ADJ_TIME;\n-\t\tbreak;\n-\tcase ICE_PTP_ADJ_TIME_AT_TIME:\n-\t\tcmd_val |= GLTSYN_CMD_ADJ_INIT_TIME;\n-\t\tbreak;\n-\tcase ICE_PTP_READ_TIME:\n-\t\tcmd_val |= GLTSYN_CMD_READ_TIME;\n-\t\tbreak;\n-\tdefault:\n-\t\tice_warn(hw, \"Unknown timer command %u\\n\", cmd);\n-\t\treturn;\n-\t}\n-\n-\twr32(hw, GLTSYN_CMD, cmd_val);\n-}\n-\n /**\n  * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command\n  * @hw: pointer to HW struct\n",
    "prefixes": [
        "v2",
        "43/70"
    ]
}