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GET /api/patches/115069/?format=api
{ "id": 115069, "url": "http://patches.dpdk.org/api/patches/115069/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220815073206.2917968-42-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220815073206.2917968-42-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220815073206.2917968-42-qi.z.zhang@intel.com", "date": "2022-08-15T07:31:37", "name": "[v2,41/70] net/ice/base: add low latency Tx timestamp read", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8dba367b4ca89e5e26eb6cd66ebf6a57afac0985", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220815073206.2917968-42-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 24308, "url": "http://patches.dpdk.org/api/series/24308/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24308", "date": "2022-08-15T07:30:56", "name": "ice base code update", "version": 2, "mbox": "http://patches.dpdk.org/series/24308/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/115069/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/115069/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C1D23A00C3;\n\tMon, 15 Aug 2022 01:26:01 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3C05142C71;\n\tMon, 15 Aug 2022 01:23:27 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by mails.dpdk.org (Postfix) with ESMTP id 977EB42CB2\n for <dev@dpdk.org>; Mon, 15 Aug 2022 01:23:24 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Aug 2022 16:23:24 -0700", "from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4])\n by orsmga008.jf.intel.com with ESMTP; 14 Aug 2022 16:23:22 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1660519404; x=1692055404;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=v68MfeKfGXo/sMyUzpvUeYZKcXPbe3vzWW8WOnx7GBM=;\n b=IyeU//doloiypzITdP4SdamRdAndHE0zZogRphPpu5mVzDvyDGty39q1\n r8GC1pk3rm+nX+Bc7W2s8DjR9c0H2f0t+588EwSUvH4yTKGPMsZRLHJog\n LeXi9u3BFptryXCCM0NXZ1UfL0RHIVTemPFSdj5sRpwEptOAIyOB5/Zeu\n QwTzlRPy3OOC6PifhlIoAk2GfLUETvP6WnSEWS2eN7ftnhVainkuNf/rn\n 6+1oxTNcmrPk+Mh/MJGAGRP9BPVS5zqswT//yXFLdqZQHMQHrCN39JuOW\n czRhEhe7pxgBkIcMXkH6Jiru7h/LXEM8Azg+C5JXCcnK1wWaz3c3ipBEJ w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10439\"; a=\"291857987\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"291857987\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"635283220\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Karol Kolacinski <karol.kolacinski@intel.com>", "Subject": "[PATCH v2 41/70] net/ice/base: add low latency Tx timestamp read", "Date": "Mon, 15 Aug 2022 03:31:37 -0400", "Message-Id": "<20220815073206.2917968-42-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20220815073206.2917968-1-qi.z.zhang@intel.com>", "References": "<20220815071306.2910599-1-qi.z.zhang@intel.com>\n <20220815073206.2917968-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "E810 products can support low latency Tx timestamp register read.\nAdd a check for the device capability and use the new method if\nsupported.\n\nSigned-off-by: Karol Kolacinski <karol.kolacinski@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 7 ++-\n drivers/net/ice/base/ice_ptp_hw.c | 95 +++++++++++++++++++++++++++----\n drivers/net/ice/base/ice_ptp_hw.h | 12 +++-\n drivers/net/ice/base/ice_type.h | 2 +\n 4 files changed, 101 insertions(+), 15 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex c90ae20c43..2014f8361d 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -2757,7 +2757,8 @@ ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,\n \tinfo->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0);\n \tinfo->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0);\n \n-\tinfo->ena_ports = logical_id;\n+\tinfo->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0);\n+\n \tinfo->tmr_own_map = phys_id;\n \n \tice_debug(hw, ICE_DBG_INIT, \"dev caps: ieee_1588 = %u\\n\",\n@@ -2774,8 +2775,8 @@ ice_parse_1588_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,\n \t\t info->tmr1_owned);\n \tice_debug(hw, ICE_DBG_INIT, \"dev caps: tmr1_ena = %u\\n\",\n \t\t info->tmr1_ena);\n-\tice_debug(hw, ICE_DBG_INIT, \"dev caps: ieee_1588 ena_ports = %u\\n\",\n-\t\t info->ena_ports);\n+\tice_debug(hw, ICE_DBG_INIT, \"dev caps: ts_ll_read = %u\\n\",\n+\t\t info->ts_ll_read);\n \tice_debug(hw, ICE_DBG_INIT, \"dev caps: tmr_own_map = %u\\n\",\n \t\t info->tmr_own_map);\n }\ndiff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex 7ed420be8e..712b7dedfb 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -4142,38 +4142,111 @@ ice_write_phy_reg_e810(struct ice_hw *hw, u32 addr, u32 val)\n }\n \n /**\n- * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY\n+ * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW\n+ * @hw: pointer to the HW struct\n+ * @idx: the timestamp index to read\n+ * @hi: 8 bit timestamp high value\n+ * @lo: 32 bit timestamp low value\n+ *\n+ * Read a 8bit timestamp high value and 32 bit timestamp low value out of the\n+ * timestamp block of the external PHY on the E810 device using the low latency\n+ * timestamp read.\n+ */\n+static enum ice_status\n+ice_read_phy_tstamp_ll_e810(struct ice_hw *hw, u8 idx, u8 *hi, u32 *lo)\n+{\n+\tu8 i;\n+\n+\t/* Write TS index to read to the PF register so the FW can read it */\n+\twr32(hw, PF_SB_ATQBAL, TS_LL_READ_TS_IDX(idx));\n+\n+\t/* Read the register repeatedly until the FW provides us the TS */\n+\tfor (i = TS_LL_READ_RETRIES; i > 0; i--) {\n+\t\tu32 val = rd32(hw, PF_SB_ATQBAL);\n+\n+\t\t/* When the bit is cleared, the TS is ready in the register */\n+\t\tif (!(val & TS_LL_READ_TS)) {\n+\t\t\t/* High 8 bit value of the TS is on the bits 16:23 */\n+\t\t\t*hi = (u8)(val >> TS_LL_READ_TS_HIGH_S);\n+\n+\t\t\t/* Read the low 32 bit value and set the TS valid bit */\n+\t\t\t*lo = rd32(hw, PF_SB_ATQBAH) | TS_VALID;\n+\t\t\treturn ICE_SUCCESS;\n+\t\t}\n+\n+\t\tice_usec_delay(10, false);\n+\t}\n+\n+\t/* FW failed to provide the TS in time */\n+\tice_debug(hw, ICE_DBG_PTP, \"Failed to read PTP timestamp using low latency read\\n\");\n+\treturn ICE_ERR_NOT_READY;\n+}\n+\n+/**\n+ * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq\n * @hw: pointer to the HW struct\n * @lport: the lport to read from\n * @idx: the timestamp index to read\n- * @tstamp: on return, the 40bit timestamp value\n+ * @hi: 8 bit timestamp high value\n+ * @lo: 32 bit timestamp low value\n *\n- * Read a 40bit timestamp value out of the timestamp block of the external PHY\n- * on the E810 device.\n+ * Read a 8bit timestamp high value and 32 bit timestamp low value out of the\n+ * timestamp block of the external PHY on the E810 device using sideband queue.\n */\n static enum ice_status\n-ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)\n+ice_read_phy_tstamp_sbq_e810(struct ice_hw *hw, u8 lport, u8 idx, u8 *hi,\n+\t\t\t u32 *lo)\n {\n+\tu32 hi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);\n+\tu32 lo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);\n \tenum ice_status status;\n-\tu32 lo_addr, hi_addr, lo, hi;\n-\n-\tlo_addr = TS_EXT(LOW_TX_MEMORY_BANK_START, lport, idx);\n-\thi_addr = TS_EXT(HIGH_TX_MEMORY_BANK_START, lport, idx);\n+\tu32 lo_val, hi_val;\n \n-\tstatus = ice_read_phy_reg_e810(hw, lo_addr, &lo);\n+\tstatus = ice_read_phy_reg_e810(hw, lo_addr, &lo_val);\n \tif (status) {\n \t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read low PTP timestamp register, status %d\\n\",\n \t\t\t status);\n \t\treturn status;\n \t}\n \n-\tstatus = ice_read_phy_reg_e810(hw, hi_addr, &hi);\n+\tstatus = ice_read_phy_reg_e810(hw, hi_addr, &hi_val);\n \tif (status) {\n \t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read high PTP timestamp register, status %d\\n\",\n \t\t\t status);\n \t\treturn status;\n \t}\n \n+\t*lo = lo_val;\n+\t*hi = (u8)hi_val;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY\n+ * @hw: pointer to the HW struct\n+ * @lport: the lport to read from\n+ * @idx: the timestamp index to read\n+ * @tstamp: on return, the 40bit timestamp value\n+ *\n+ * Read a 40bit timestamp value out of the timestamp block of the external PHY\n+ * on the E810 device.\n+ */\n+static enum ice_status\n+ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp)\n+{\n+\tenum ice_status status;\n+\tu32 lo = 0;\n+\tu8 hi = 0;\n+\n+\tif (hw->dev_caps.ts_dev_info.ts_ll_read)\n+\t\tstatus = ice_read_phy_tstamp_ll_e810(hw, idx, &hi, &lo);\n+\telse\n+\t\tstatus = ice_read_phy_tstamp_sbq_e810(hw, lport, idx, &hi, &lo);\n+\n+\tif (status)\n+\t\treturn status;\n+\n \t/* For E810 devices, the timestamp is reported with the lower 32 bits\n \t * in the low register, and the upper 8 bits in the high register.\n \t */\ndiff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h\nindex 1e016ef177..9fa17787df 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.h\n+++ b/drivers/net/ice/base/ice_ptp_hw.h\n@@ -476,8 +476,8 @@ enum ice_status ice_ptp_init_phy_cfg(struct ice_hw *hw);\n #define INCVAL_HIGH_M\t\t\t0xFF\n \n /* Timestamp block macros */\n+#define TS_VALID\t\t\tBIT(0)\n #define TS_LOW_M\t\t\t0xFFFFFFFF\n-#define TS_HIGH_M\t\t\t0xFF\n #define TS_HIGH_S\t\t\t32\n \n #define TS_PHY_LOW_M\t\t\t0xFF\n@@ -487,6 +487,16 @@ enum ice_status ice_ptp_init_phy_cfg(struct ice_hw *hw);\n #define BYTES_PER_IDX_ADDR_L_U\t\t8\n #define BYTES_PER_IDX_ADDR_L\t\t4\n \n+/* Tx timestamp low latency read definitions */\n+#define TS_LL_READ_RETRIES\t\t200\n+#define TS_LL_READ_TS\t\t\tBIT(31)\n+#define TS_LL_READ_TS_IDX_S\t\t24\n+#define TS_LL_READ_TS_IDX_M\t\tMAKEMASK(0x3F, 0)\n+#define TS_LL_READ_TS_IDX(__idx)\t(TS_LL_READ_TS | \\\n+\t\t\t\t\t (((__idx) & TS_LL_READ_TS_IDX_M) << \\\n+\t\t\t\t\t TS_LL_READ_TS_IDX_S))\n+#define TS_LL_READ_TS_HIGH_S\t\t16\n+\n /* Internal PHY timestamp address */\n #define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))\n #define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U +\t\t\\\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 5c7cc06e0c..cdfef47e94 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -651,6 +651,7 @@ struct ice_ts_func_info {\n #define ICE_TS_DEV_ENA_M\t\tBIT(24)\n #define ICE_TS_TMR0_ENA_M\t\tBIT(25)\n #define ICE_TS_TMR1_ENA_M\t\tBIT(26)\n+#define ICE_TS_LL_TX_TS_READ_M\t\tBIT(28)\n \n struct ice_ts_dev_info {\n \t/* Device specific info */\n@@ -663,6 +664,7 @@ struct ice_ts_dev_info {\n \tu8 ena;\n \tu8 tmr0_ena;\n \tu8 tmr1_ena;\n+\tu8 ts_ll_read;\n };\n \n /* Function specific capabilities */\n", "prefixes": [ "v2", "41/70" ] }