Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 115043,
    "url": "http://patches.dpdk.org/api/patches/115043/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220815073206.2917968-16-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220815073206.2917968-16-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220815073206.2917968-16-qi.z.zhang@intel.com",
    "date": "2022-08-15T07:31:11",
    "name": "[v2,15/70] net/ice/base: implement 56G PHY access functions",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": true,
    "hash": "b86b8bc66d4e48c00cc43e2c7f4b50a339251fca",
    "submitter": {
        "id": 504,
        "url": "http://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220815073206.2917968-16-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 24308,
            "url": "http://patches.dpdk.org/api/series/24308/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24308",
            "date": "2022-08-15T07:30:56",
            "name": "ice base code update",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/24308/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/115043/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/115043/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 781E0A00C3;\n\tMon, 15 Aug 2022 01:23:43 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 64A1D427F0;\n\tMon, 15 Aug 2022 01:22:42 +0200 (CEST)",
            "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by mails.dpdk.org (Postfix) with ESMTP id C581742BF1\n for <dev@dpdk.org>; Mon, 15 Aug 2022 01:22:39 +0200 (CEST)",
            "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Aug 2022 16:22:39 -0700",
            "from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4])\n by orsmga008.jf.intel.com with ESMTP; 14 Aug 2022 16:22:37 -0700"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1660519360; x=1692055360;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=XtmCKa6K2ZXGMhfnjtZyjDl3qJBKvbPWM3WT2qUJLV0=;\n b=FoCLyQ9eIDmVz0LvKUbfvcW3HdplZfSOHPf5Iqgz/TcGSXHFI9soop8B\n s79zTsLFr6QZ6EtQtuoyJzL+33QgbKzPxqJ+jFEjDD2mnB2lav9VTr4Ty\n 2y3eptsredJwV+uhL06jDjM6Q4tlXlsLDrUFRZJpMd2SZ9qVVFEtlz/vo\n I6605Cp3KCII0xmvrNQOKGKkSqLP3QW6lcbwaKojVhcpGb3ovAWuscfCE\n roBc/5/4SzCPLdDhelM8HHt2BXGMzxXigVM+2uxr8k5CEZ36wEqM6rLpE\n LLMIldoL1ui7fnGiU7YB2FI7Aa5Is65suD5vJWltv0aIK9CLG+alZWMDb g==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6400,9594,10439\"; a=\"291857936\"",
            "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"291857936\"",
            "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"635283060\""
        ],
        "X-ExtLoop1": "1",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "qiming.yang@intel.com",
        "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Sergey Temerkhanov <sergey.temerkhanov@intel.com>",
        "Subject": "[PATCH v2 15/70] net/ice/base: implement 56G PHY access functions",
        "Date": "Mon, 15 Aug 2022 03:31:11 -0400",
        "Message-Id": "<20220815073206.2917968-16-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.31.1",
        "In-Reply-To": "<20220815073206.2917968-1-qi.z.zhang@intel.com>",
        "References": "<20220815071306.2910599-1-qi.z.zhang@intel.com>\n <20220815073206.2917968-1-qi.z.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "Implement 56G PHY register and memory read/write functions\nto facilitate PTP support\n\nSigned-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_ptp_hw.c | 1094 +++++++++++++++++++++++++++--\n drivers/net/ice/base/ice_ptp_hw.h |   44 +-\n drivers/net/ice/base/ice_type.h   |   11 +\n 3 files changed, 1090 insertions(+), 59 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex 22d0774dd7..1c5fd799f6 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -395,7 +395,976 @@ static void ice_ptp_exec_tmr_cmd(struct ice_hw *hw)\n \tice_flush(hw);\n }\n \n-/* E822 family functions\n+/**\n+ * ice_ptp_clean_cmd - Clean the timer command register\n+ * @hw: pointer to HW struct\n+ *\n+ * Zero out the GLTSYN_CMD to avoid any residual command execution.\n+ */\n+static void ice_ptp_clean_cmd(struct ice_hw *hw)\n+{\n+\twr32(hw, GLTSYN_CMD, 0);\n+\tice_flush(hw);\n+}\n+\n+/* 56G PHY access functions */\n+static const u32 eth56g_port_base[ICE_NUM_PHY_PORTS] = {\n+\tICE_PHY0_BASE,\n+\tICE_PHY1_BASE,\n+\tICE_PHY2_BASE,\n+\tICE_PHY3_BASE,\n+\tICE_PHY4_BASE,\n+};\n+\n+/**\n+ * ice_write_phy_eth56g_raw_lp - Write a PHY port register with lock parameter\n+ * @hw: pointer to the HW struct\n+ * @reg_addr: PHY register address\n+ * @val: Value to write\n+ * @lock_sbq: true to lock the sideband queue\n+ */\n+static enum ice_status\n+ice_write_phy_eth56g_raw_lp(struct ice_hw *hw,  u32 reg_addr, u32 val,\n+\t\t\t    bool lock_sbq)\n+{\n+\tstruct ice_sbq_msg_input phy_msg;\n+\tenum ice_status status;\n+\n+\tphy_msg.opcode = ice_sbq_msg_wr;\n+\n+\tphy_msg.msg_addr_low = ICE_LO_WORD(reg_addr);\n+\tphy_msg.msg_addr_high = ICE_HI_WORD(reg_addr);\n+\n+\tphy_msg.data = val;\n+\tphy_msg.dest_dev = phy_56g;\n+\n+\tstatus = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);\n+\n+\tif (status)\n+\t\tice_debug(hw, ICE_DBG_PTP, \"PTP failed to send msg to phy %d\\n\",\n+\t\t\t  status);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_read_phy_eth56g_raw_lp - Read a PHY port register with lock parameter\n+ * @hw: pointer to the HW struct\n+ * @reg_addr: PHY port register address\n+ * @val: Pointer to the value to read (out param)\n+ * @lock_sbq: true to lock the sideband queue\n+ */\n+static enum ice_status\n+ice_read_phy_eth56g_raw_lp(struct ice_hw *hw, u32 reg_addr, u32 *val,\n+\t\t\t   bool lock_sbq)\n+{\n+\tstruct ice_sbq_msg_input phy_msg;\n+\tenum ice_status status;\n+\n+\tphy_msg.opcode = ice_sbq_msg_rd;\n+\n+\tphy_msg.msg_addr_low = ICE_LO_WORD(reg_addr);\n+\tphy_msg.msg_addr_high = ICE_HI_WORD(reg_addr);\n+\n+\tphy_msg.dest_dev = phy_56g;\n+\n+\tstatus = ice_sbq_rw_reg_lp(hw, &phy_msg, lock_sbq);\n+\n+\tif (status)\n+\t\tice_debug(hw, ICE_DBG_PTP, \"PTP failed to send msg to phy %d\\n\",\n+\t\t\t  status);\n+\telse\n+\t\t*val = phy_msg.data;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_phy_port_reg_address_eth56g - Calculate a PHY port register address\n+ * @port: Port number to be written\n+ * @offset: Offset from PHY port register base\n+ * @address: The result address\n+ */\n+static enum ice_status\n+ice_phy_port_reg_address_eth56g(u8 port, u16 offset, u32 *address)\n+{\n+\tu8 phy, lane;\n+\n+\tif (port >= ICE_NUM_EXTERNAL_PORTS)\n+\t\treturn ICE_ERR_OUT_OF_RANGE;\n+\n+\tphy = port / ICE_PORTS_PER_QUAD;\n+\tlane = port % ICE_PORTS_PER_QUAD;\n+\n+\t*address = offset + eth56g_port_base[phy] +\n+\t\t   PHY_PTP_LANE_ADDR_STEP * lane;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_write_phy_reg_eth56g_lp - Write a PHY port register with lock parameter\n+ * @hw: pointer to the HW struct\n+ * @port: Port number to be written\n+ * @offset: Offset from PHY port register base\n+ * @val: Value to write\n+ * @lock_sbq: true to lock the sideband queue\n+ */\n+static enum ice_status\n+ice_write_phy_reg_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset, u32 val,\n+\t\t\t    bool lock_sbq)\n+{\n+\tenum ice_status status;\n+\tu32 reg_addr;\n+\n+\tstatus = ice_phy_port_reg_address_eth56g(port, offset, &reg_addr);\n+\tif (status)\n+\t\treturn status;\n+\n+\treturn ice_write_phy_eth56g_raw_lp(hw, reg_addr, val, lock_sbq);\n+}\n+\n+/**\n+ * ice_write_phy_reg_eth56g - Write a PHY port register with sbq locked\n+ * @hw: pointer to the HW struct\n+ * @port: Port number to be written\n+ * @offset: Offset from PHY port register base\n+ * @val: Value to write\n+ */\n+enum ice_status\n+ice_write_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val)\n+{\n+\treturn ice_write_phy_reg_eth56g_lp(hw, port, offset, val, true);\n+}\n+\n+/**\n+ * ice_read_phy_reg_eth56g_lp - Read a PHY port register with\n+ * lock parameter\n+ * @hw: pointer to the HW struct\n+ * @port: Port number to be read\n+ * @offset: Offset from PHY port register base\n+ * @val: Pointer to the value to read (out param)\n+ * @lock_sbq: true to lock the sideband queue\n+ */\n+static enum ice_status\n+ice_read_phy_reg_eth56g_lp(struct ice_hw *hw, u8 port, u16 offset, u32 *val,\n+\t\t\t   bool lock_sbq)\n+{\n+\tenum ice_status status;\n+\tu32 reg_addr;\n+\n+\tstatus = ice_phy_port_reg_address_eth56g(port, offset, &reg_addr);\n+\tif (status)\n+\t\treturn status;\n+\n+\treturn ice_read_phy_eth56g_raw_lp(hw, reg_addr, val, lock_sbq);\n+}\n+\n+/**\n+ * ice_read_phy_reg_eth56g - Read a PHY port register with sbq locked\n+ * @hw: pointer to the HW struct\n+ * @port: Port number to be read\n+ * @offset: Offset from PHY port register base\n+ * @val: Pointer to the value to read (out param)\n+ */\n+enum ice_status\n+ice_read_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val)\n+{\n+\treturn ice_read_phy_reg_eth56g_lp(hw, port, offset, val, true);\n+}\n+\n+/**\n+ * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register\n+ * @low_addr: the low address to check\n+ *\n+ * Checks if the provided low address is one of the known 64bit PHY values\n+ * represented as two 32bit registers.\n+ */\n+static bool ice_is_64b_phy_reg_eth56g(u16 low_addr)\n+{\n+\tswitch (low_addr) {\n+\tcase PHY_REG_TX_TIMER_INC_PRE_L:\n+\tcase PHY_REG_RX_TIMER_INC_PRE_L:\n+\tcase PHY_REG_TX_CAPTURE_L:\n+\tcase PHY_REG_RX_CAPTURE_L:\n+\tcase PHY_REG_TOTAL_TX_OFFSET_L:\n+\tcase PHY_REG_TOTAL_RX_OFFSET_L:\n+\t\treturn true;\n+\tdefault:\n+\t\treturn false;\n+\t}\n+}\n+\n+/**\n+ * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register\n+ * @low_addr: the low address to check\n+ *\n+ * Checks if the provided low address is one of the known 40bit PHY values\n+ * split into two registers with the lower 8 bits in the low register and the\n+ * upper 32 bits in the high register.\n+ */\n+static bool ice_is_40b_phy_reg_eth56g(u16 low_addr)\n+{\n+\tswitch (low_addr) {\n+\tcase PHY_REG_TIMETUS_L:\n+\t\treturn true;\n+\tdefault:\n+\t\treturn false;\n+\t}\n+}\n+\n+/**\n+ * ice_read_40b_phy_reg_eth56g - Read a 40bit value from PHY registers\n+ * @hw: pointer to the HW struct\n+ * @port: PHY port to read from\n+ * @low_addr: offset of the lower register to read from\n+ * @val: on return, the contents of the 40bit value from the PHY registers\n+ *\n+ * Reads the two registers associated with a 40bit value and returns it in the\n+ * val pointer.\n+ * This function checks that the caller has specified a known 40 bit register\n+ * offset\n+ */\n+static enum ice_status\n+ice_read_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)\n+{\n+\tu16 high_addr = low_addr + sizeof(u32);\n+\tenum ice_status status;\n+\tu32 lo, hi;\n+\n+\tif (!ice_is_40b_phy_reg_eth56g(low_addr))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tstatus = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read from low register %#08x\\n, status %d\",\n+\t\t\t  (int)low_addr, status);\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_phy_reg_eth56g(hw, port, low_addr + sizeof(u32), &hi);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read from high register %08x\\n, status %d\",\n+\t\t\t  high_addr, status);\n+\t\treturn status;\n+\t}\n+\n+\t*val = ((u64)hi << P_REG_40B_HIGH_S) | (lo & P_REG_40B_LOW_M);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers\n+ * @hw: pointer to the HW struct\n+ * @port: PHY port to read from\n+ * @low_addr: offset of the lower register to read from\n+ * @val: on return, the contents of the 64bit value from the PHY registers\n+ *\n+ * Reads the two registers associated with a 64bit value and returns it in the\n+ * val pointer.\n+ * This function checks that the caller has specified a known 64 bit register\n+ * offset\n+ */\n+static enum ice_status\n+ice_read_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)\n+{\n+\tu16 high_addr = low_addr + sizeof(u32);\n+\tenum ice_status status;\n+\tu32 lo, hi;\n+\n+\tif (!ice_is_64b_phy_reg_eth56g(low_addr))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tstatus = ice_read_phy_reg_eth56g(hw, port, low_addr, &lo);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read from low register %#08x\\n, status %d\",\n+\t\t\t  low_addr, status);\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_read_phy_reg_eth56g(hw, port, high_addr, &hi);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read from high register %#08x\\n, status %d\",\n+\t\t\t  high_addr, status);\n+\t\treturn status;\n+\t}\n+\n+\t*val = ((u64)hi << 32) | lo;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY\n+ * @hw: pointer to the HW struct\n+ * @port: port to write to\n+ * @low_addr: offset of the low register\n+ * @val: 40b value to write\n+ *\n+ * Write the provided 40b value to the two associated registers by splitting\n+ * it up into two chunks, the lower 8 bits and the upper 32 bits.\n+ * This function checks that the caller has specified a known 40 bit register\n+ * offset\n+ */\n+static enum ice_status\n+ice_write_40b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)\n+{\n+\tu16 high_addr = low_addr + sizeof(u32);\n+\tenum ice_status status;\n+\tu32 lo, hi;\n+\n+\tif (!ice_is_40b_phy_reg_eth56g(low_addr))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tlo = (u32)(val & P_REG_40B_LOW_M);\n+\thi = (u32)(val >> P_REG_40B_HIGH_S);\n+\n+\tstatus = ice_write_phy_reg_eth56g(hw, port, low_addr, lo);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write to low register 0x%08x\\n, status %d\",\n+\t\t\t  low_addr, status);\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_write_phy_reg_eth56g(hw, port, high_addr, hi);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write to high register 0x%08x\\n, status %d\",\n+\t\t\t  high_addr, status);\n+\t\treturn status;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers\n+ * @hw: pointer to the HW struct\n+ * @port: PHY port to read from\n+ * @low_addr: offset of the lower register to read from\n+ * @val: the contents of the 64bit value to write to PHY\n+ *\n+ * Write the 64bit value to the two associated 32bit PHY registers.\n+ * This function checks that the caller has specified a known 64 bit register\n+ * offset\n+ */\n+static enum ice_status\n+ice_write_64b_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)\n+{\n+\tu16 high_addr = low_addr + sizeof(u32);\n+\tenum ice_status status;\n+\tu32 lo, hi;\n+\n+\tif (!ice_is_64b_phy_reg_eth56g(low_addr))\n+\t\treturn ICE_ERR_PARAM;\n+\n+\tlo = ICE_LO_DWORD(val);\n+\thi = ICE_HI_DWORD(val);\n+\n+\tstatus = ice_write_phy_reg_eth56g(hw, port, low_addr, lo);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write to low register 0x%08x\\n, status %d\",\n+\t\t\t  low_addr, status);\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ice_write_phy_reg_eth56g(hw, port, high_addr, hi);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write to high register 0x%08x\\n, status %d\",\n+\t\t\t  high_addr, status);\n+\t\treturn status;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust\n+ * @hw: pointer to HW struct\n+ * @port: Port number to be programmed\n+ * @time: time in cycles to adjust the port Tx and Rx clocks\n+ * @lock_sbq: true to lock the sbq sq_lock (the usual case); false if the\n+ *            sq_lock has already been locked at a higher level\n+ *\n+ * Program the port for an atomic adjustment by writing the Tx and Rx timer\n+ * registers. The atomic adjustment won't be completed until the driver issues\n+ * an ICE_PTP_ADJ_TIME command.\n+ *\n+ * Note that time is not in units of nanoseconds. It is in clock time\n+ * including the lower sub-nanosecond portion of the port timer.\n+ *\n+ * Negative adjustments are supported using 2s complement arithmetic.\n+ */\n+enum ice_status\n+ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time,\n+\t\t\t     bool lock_sbq)\n+{\n+\tenum ice_status status;\n+\tu32 l_time, u_time;\n+\n+\tl_time = ICE_LO_DWORD(time);\n+\tu_time = ICE_HI_DWORD(time);\n+\n+\t/* Tx case */\n+\tstatus = ice_write_phy_reg_eth56g_lp(hw, port,\n+\t\t\t\t\t     PHY_REG_TX_TIMER_INC_PRE_L,\n+\t\t\t\t\t     l_time, lock_sbq);\n+\tif (status)\n+\t\tgoto exit_err;\n+\n+\tstatus = ice_write_phy_reg_eth56g_lp(hw, port,\n+\t\t\t\t\t     PHY_REG_TX_TIMER_INC_PRE_U,\n+\t\t\t\t\t     u_time, lock_sbq);\n+\tif (status)\n+\t\tgoto exit_err;\n+\n+\t/* Rx case */\n+\tstatus = ice_write_phy_reg_eth56g_lp(hw, port,\n+\t\t\t\t\t     PHY_REG_RX_TIMER_INC_PRE_L,\n+\t\t\t\t\t     l_time, lock_sbq);\n+\tif (status)\n+\t\tgoto exit_err;\n+\n+\tstatus = ice_write_phy_reg_eth56g_lp(hw, port,\n+\t\t\t\t\t     PHY_REG_RX_TIMER_INC_PRE_U,\n+\t\t\t\t\t     u_time, lock_sbq);\n+\tif (status)\n+\t\tgoto exit_err;\n+\n+\treturn ICE_SUCCESS;\n+\n+exit_err:\n+\tice_debug(hw, ICE_DBG_PTP, \"Failed to write time adjust for port %u, status %d\\n\",\n+\t\t  port, status);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_ptp_read_phy_incval_eth56g - Read a PHY port's current incval\n+ * @hw: pointer to the HW struct\n+ * @port: the port to read\n+ * @incval: on return, the time_clk_cyc incval for this port\n+ *\n+ * Read the time_clk_cyc increment value for a given PHY port.\n+ */\n+enum ice_status\n+ice_ptp_read_phy_incval_eth56g(struct ice_hw *hw, u8 port, u64 *incval)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_read_40b_phy_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,\n+\t\t\t\t\t     incval);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read TIMETUS_L, status %d\\n\",\n+\t\t\t  status);\n+\t\treturn status;\n+\t}\n+\n+\tice_debug(hw, ICE_DBG_PTP, \"read INCVAL = 0x%016llx\\n\",\n+\t\t  (unsigned long long)*incval);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_ptp_read_port_capture_eth56g - Read a port's local time capture\n+ * @hw: pointer to HW struct\n+ * @port: Port number to read\n+ * @tx_ts: on return, the Tx port time capture\n+ * @rx_ts: on return, the Rx port time capture\n+ *\n+ * Read the port's Tx and Rx local time capture values.\n+ */\n+enum ice_status\n+ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port, u64 *tx_ts,\n+\t\t\t\t u64 *rx_ts)\n+{\n+\tenum ice_status status;\n+\n+\t/* Tx case */\n+\tstatus = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_TX_CAPTURE_L,\n+\t\t\t\t\t     tx_ts);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read REG_TX_CAPTURE, status %d\\n\",\n+\t\t\t  status);\n+\t\treturn status;\n+\t}\n+\n+\tice_debug(hw, ICE_DBG_PTP, \"tx_init = %#016llx\\n\",\n+\t\t  (unsigned long long)*tx_ts);\n+\n+\t/* Rx case */\n+\tstatus = ice_read_64b_phy_reg_eth56g(hw, port, PHY_REG_RX_CAPTURE_L,\n+\t\t\t\t\t     rx_ts);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read RX_CAPTURE, status %d\\n\",\n+\t\t\t  status);\n+\t\treturn status;\n+\t}\n+\n+\tice_debug(hw, ICE_DBG_PTP, \"rx_init = %#016llx\\n\",\n+\t\t  (unsigned long long)*rx_ts);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_ptp_one_port_cmd_eth56g - Prepare a single PHY port for a timer command\n+ * @hw: pointer to HW struct\n+ * @port: Port to which cmd has to be sent\n+ * @cmd: Command to be sent to the port\n+ * @lock_sbq: true if the sideband queue lock must be acquired\n+ *\n+ * Prepare the requested port for an upcoming timer sync command.\n+ */\n+enum ice_status\n+ice_ptp_one_port_cmd_eth56g(struct ice_hw *hw, u8 port,\n+\t\t\t    enum ice_ptp_tmr_cmd cmd, bool lock_sbq)\n+{\n+\tenum ice_status status;\n+\tu32 cmd_val, val;\n+\tu8 tmr_idx;\n+\n+\ttmr_idx = ice_get_ptp_src_clock_index(hw);\n+\tcmd_val = tmr_idx << SEL_PHY_SRC;\n+\tswitch (cmd) {\n+\tcase ICE_PTP_INIT_TIME:\n+\t\tcmd_val |= PHY_CMD_INIT_TIME;\n+\t\tbreak;\n+\tcase ICE_PTP_INIT_INCVAL:\n+\t\tcmd_val |= PHY_CMD_INIT_INCVAL;\n+\t\tbreak;\n+\tcase ICE_PTP_ADJ_TIME:\n+\t\tcmd_val |= PHY_CMD_ADJ_TIME;\n+\t\tbreak;\n+\tcase ICE_PTP_ADJ_TIME_AT_TIME:\n+\t\tcmd_val |= PHY_CMD_ADJ_TIME_AT_TIME;\n+\t\tbreak;\n+\tcase ICE_PTP_READ_TIME:\n+\t\tcmd_val |= PHY_CMD_READ_TIME;\n+\t\tbreak;\n+\tdefault:\n+\t\tice_warn(hw, \"Unknown timer command %u\\n\", cmd);\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\t/* Tx case */\n+\t/* Read, modify, write */\n+\tstatus = ice_read_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TMR_CMD, &val,\n+\t\t\t\t\t    lock_sbq);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read TX_TMR_CMD, status %d\\n\",\n+\t\t\t  status);\n+\t\treturn status;\n+\t}\n+\n+\t/* Modify necessary bits only and perform write */\n+\tval &= ~TS_CMD_MASK;\n+\tval |= cmd_val;\n+\n+\tstatus = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_TX_TMR_CMD, val,\n+\t\t\t\t\t     lock_sbq);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write back TX_TMR_CMD, status %d\\n\",\n+\t\t\t  status);\n+\t\treturn status;\n+\t}\n+\n+\t/* Rx case */\n+\t/* Read, modify, write */\n+\tstatus = ice_read_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TMR_CMD, &val,\n+\t\t\t\t\t    lock_sbq);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read RX_TMR_CMD, status %d\\n\",\n+\t\t\t  status);\n+\t\treturn status;\n+\t}\n+\n+\t/* Modify necessary bits only and perform write */\n+\tval &= ~TS_CMD_MASK;\n+\tval |= cmd_val;\n+\n+\tstatus = ice_write_phy_reg_eth56g_lp(hw, port, PHY_REG_RX_TMR_CMD, val,\n+\t\t\t\t\t     lock_sbq);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write back RX_TMR_CMD, status %d\\n\",\n+\t\t\t  status);\n+\t\treturn status;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_ptp_port_cmd_eth56g - Prepare all ports for a timer command\n+ * @hw: pointer to the HW struct\n+ * @cmd: timer command to prepare\n+ * @lock_sbq: true if the sideband queue lock must  be acquired\n+ *\n+ * Prepare all ports connected to this device for an upcoming timer sync\n+ * command.\n+ */\n+static enum ice_status\n+ice_ptp_port_cmd_eth56g(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,\n+\t\t\tbool lock_sbq)\n+{\n+\tenum ice_status status;\n+\tu8 port;\n+\n+\tfor (port = 0; port < ICE_NUM_EXTERNAL_PORTS; port++) {\n+\t\tif (!(hw->ena_lports & BIT(port)))\n+\t\t\tcontinue;\n+\n+\t\tstatus = ice_ptp_one_port_cmd_eth56g(hw, port, cmd, lock_sbq);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_calc_fixed_tx_offset_eth56g - Calculated Fixed Tx offset for a port\n+ * @hw: pointer to the HW struct\n+ * @link_spd: the Link speed to calculate for\n+ *\n+ * Calculate the fixed offset due to known static latency data.\n+ */\n+static u64\n+ice_calc_fixed_tx_offset_eth56g(struct ice_hw *hw,\n+\t\t\t\tenum ice_ptp_link_spd link_spd)\n+{\n+\tu64 fixed_offset = 0;\n+\treturn fixed_offset;\n+}\n+\n+/**\n+ * ice_phy_cfg_tx_offset_eth56g - Configure total Tx timestamp offset\n+ * @hw: pointer to the HW struct\n+ * @port: the PHY port to configure\n+ *\n+ * Program the PHY_REG_TOTAL_TX_OFFSET register with the total number of TUs to\n+ * adjust Tx timestamps by.\n+ *\n+ * To avoid overflow, when calculating the offset based on the known static\n+ * latency values, we use measurements in 1/100th of a nanosecond, and divide\n+ * the TUs per second up front. This avoids overflow while allowing\n+ * calculation of the adjustment using integer arithmetic.\n+ */\n+enum ice_status ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port)\n+{\n+\tenum ice_ptp_link_spd link_spd = ICE_PTP_LNK_SPD_10G;\n+\tenum ice_status status;\n+\tu64 total_offset;\n+\n+\ttotal_offset = ice_calc_fixed_tx_offset_eth56g(hw, link_spd);\n+\n+\t/* Now that the total offset has been calculated, program it to the\n+\t * PHY and indicate that the Tx offset is ready. After this,\n+\t * timestamps will be enabled.\n+\t */\n+\tstatus = ice_write_64b_phy_reg_eth56g(hw, port,\n+\t\t\t\t\t      PHY_REG_TOTAL_TX_OFFSET_L,\n+\t\t\t\t\t      total_offset);\n+\tif (status)\n+\t\treturn status;\n+\n+\treturn ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 1);\n+}\n+\n+/**\n+ * ice_calc_fixed_rx_offset_eth56g - Calculated the fixed Rx offset for a port\n+ * @hw: pointer to HW struct\n+ * @link_spd: The Link speed to calculate for\n+ *\n+ * Determine the fixed Rx latency for a given link speed.\n+ */\n+static u64\n+ice_calc_fixed_rx_offset_eth56g(struct ice_hw *hw,\n+\t\t\t\tenum ice_ptp_link_spd link_spd)\n+{\n+\tu64 fixed_offset = 0;\n+\treturn fixed_offset;\n+}\n+\n+/**\n+ * ice_phy_cfg_rx_offset_eth56g - Configure total Rx timestamp offset\n+ * @hw: pointer to the HW struct\n+ * @port: the PHY port to configure\n+ *\n+ * Program the PHY_REG_TOTAL_RX_OFFSET register with the number of Time Units to\n+ * adjust Rx timestamps by. This combines calculations from the Vernier offset\n+ * measurements taken in hardware with some data about known fixed delay as\n+ * well as adjusting for multi-lane alignment delay.\n+ *\n+ * This function must be called only after the offset registers are valid,\n+ * i.e. after the Vernier calibration wait has passed, to ensure that the PHY\n+ * has measured the offset.\n+ *\n+ * To avoid overflow, when calculating the offset based on the known static\n+ * latency values, we use measurements in 1/100th of a nanosecond, and divide\n+ * the TUs per second up front. This avoids overflow while allowing\n+ * calculation of the adjustment using integer arithmetic.\n+ */\n+enum ice_status ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port)\n+{\n+\tenum ice_status status;\n+\tu64 total_offset;\n+\n+\ttotal_offset = ice_calc_fixed_rx_offset_eth56g(hw, 0);\n+\n+\t/* Now that the total offset has been calculated, program it to the\n+\t * PHY and indicate that the Rx offset is ready. After this,\n+\t * timestamps will be enabled.\n+\t */\n+\tstatus = ice_write_64b_phy_reg_eth56g(hw, port,\n+\t\t\t\t\t      PHY_REG_TOTAL_RX_OFFSET_L,\n+\t\t\t\t\t      total_offset);\n+\tif (status)\n+\t\treturn status;\n+\n+\treturn ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 1);\n+}\n+\n+/**\n+ * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time\n+ * @hw: pointer to the HW struct\n+ * @port: the PHY port to read\n+ * @phy_time: on return, the 64bit PHY timer value\n+ * @phc_time: on return, the lower 64bits of PHC time\n+ *\n+ * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY\n+ * and PHC timer values.\n+ */\n+static enum ice_status\n+ice_read_phy_and_phc_time_eth56g(struct ice_hw *hw, u8 port, u64 *phy_time,\n+\t\t\t\t u64 *phc_time)\n+{\n+\tenum ice_status status;\n+\tu64 tx_time, rx_time;\n+\tu32 zo, lo;\n+\tu8 tmr_idx;\n+\n+\ttmr_idx = ice_get_ptp_src_clock_index(hw);\n+\n+\t/* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */\n+\tice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);\n+\n+\t/* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */\n+\tstatus = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_READ_TIME, true);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Issue the sync to start the ICE_PTP_READ_TIME capture */\n+\tice_ptp_exec_tmr_cmd(hw);\n+\tice_ptp_clean_cmd(hw);\n+\n+\t/* Read the captured PHC time from the shadow time registers */\n+\tzo = rd32(hw, GLTSYN_SHTIME_0(tmr_idx));\n+\tlo = rd32(hw, GLTSYN_SHTIME_L(tmr_idx));\n+\t*phc_time = (u64)lo << 32 | zo;\n+\n+\t/* Read the captured PHY time from the PHY shadow registers */\n+\tstatus = ice_ptp_read_port_capture_eth56g(hw, port, &tx_time, &rx_time);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* If the PHY Tx and Rx timers don't match, log a warning message.\n+\t * Note that this should not happen in normal circumstances since the\n+\t * driver always programs them together.\n+\t */\n+\tif (tx_time != rx_time)\n+\t\tice_warn(hw, \"PHY port %u Tx and Rx timers do not match, tx_time 0x%016llX, rx_time 0x%016llX\\n\",\n+\t\t\t port, (unsigned long long)tx_time,\n+\t\t\t (unsigned long long)rx_time);\n+\n+\t*phy_time = tx_time;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer\n+ * @hw: pointer to the HW struct\n+ * @port: the PHY port to synchronize\n+ *\n+ * Perform an adjustment to ensure that the PHY and PHC timers are in sync.\n+ * This is done by issuing a ICE_PTP_READ_TIME command which triggers a\n+ * simultaneous read of the PHY timer and PHC timer. Then we use the\n+ * difference to calculate an appropriate 2s complement addition to add\n+ * to the PHY timer in order to ensure it reads the same value as the\n+ * primary PHC timer.\n+ */\n+static enum ice_status ice_sync_phy_timer_eth56g(struct ice_hw *hw, u8 port)\n+{\n+\tu64 phc_time, phy_time, difference;\n+\tenum ice_status status;\n+\n+\tif (!ice_ptp_lock(hw)) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to acquire PTP semaphore\\n\");\n+\t\treturn ICE_ERR_NOT_READY;\n+\t}\n+\n+\tstatus = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time,\n+\t\t\t\t\t\t  &phc_time);\n+\tif (status)\n+\t\tgoto err_unlock;\n+\n+\t/* Calculate the amount required to add to the port time in order for\n+\t * it to match the PHC time.\n+\t *\n+\t * Note that the port adjustment is done using 2s complement\n+\t * arithmetic. This is convenient since it means that we can simply\n+\t * calculate the difference between the PHC time and the port time,\n+\t * and it will be interpreted correctly.\n+\t */\n+\n+\tice_ptp_src_cmd(hw, ICE_PTP_NOP);\n+\tdifference = phc_time - phy_time;\n+\n+\tstatus = ice_ptp_prep_port_adj_eth56g(hw, port, (s64)difference, true);\n+\tif (status)\n+\t\tgoto err_unlock;\n+\n+\tstatus = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_ADJ_TIME, true);\n+\tif (status)\n+\t\tgoto err_unlock;\n+\n+\t/* Issue the sync to activate the time adjustment */\n+\tice_ptp_exec_tmr_cmd(hw);\n+\tice_ptp_clean_cmd(hw);\n+\n+\t/* Re-capture the timer values to flush the command registers and\n+\t * verify that the time was properly adjusted.\n+\t */\n+\n+\tstatus = ice_read_phy_and_phc_time_eth56g(hw, port, &phy_time,\n+\t\t\t\t\t\t  &phc_time);\n+\tif (status)\n+\t\tgoto err_unlock;\n+\n+\tice_info(hw, \"Port %u PHY time synced to PHC: 0x%016llX, 0x%016llX\\n\",\n+\t\t port, (unsigned long long)phy_time,\n+\t\t (unsigned long long)phc_time);\n+\n+err_unlock:\n+\tice_ptp_unlock(hw);\n+\treturn status;\n+}\n+\n+/**\n+ * ice_stop_phy_timer_eth56g - Stop the PHY clock timer\n+ * @hw: pointer to the HW struct\n+ * @port: the PHY port to stop\n+ * @soft_reset: if true, hold the SOFT_RESET bit of PHY_REG_PS\n+ *\n+ * Stop the clock of a PHY port. This must be done as part of the flow to\n+ * re-calibrate Tx and Rx timestamping offsets whenever the clock time is\n+ * initialized or when link speed changes.\n+ */\n+enum ice_status\n+ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_write_phy_reg_eth56g(hw, port, PHY_REG_TX_OFFSET_READY, 0);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ice_write_phy_reg_eth56g(hw, port, PHY_REG_RX_OFFSET_READY, 0);\n+\tif (status)\n+\t\treturn status;\n+\n+\tice_debug(hw, ICE_DBG_PTP, \"Disabled clock on PHY port %u\\n\", port);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_start_phy_timer_eth56g - Start the PHY clock timer\n+ * @hw: pointer to the HW struct\n+ * @port: the PHY port to start\n+ * @bypass: unused, for compatibility\n+ *\n+ * Start the clock of a PHY port. This must be done as part of the flow to\n+ * re-calibrate Tx and Rx timestamping offsets whenever the clock time is\n+ * initialized or when link speed changes.\n+ *\n+ */\n+enum ice_status\n+ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass)\n+{\n+\tenum ice_status status;\n+\tu32 lo, hi;\n+\tu64 incval;\n+\tu8 tmr_idx;\n+\n+\ttmr_idx = ice_get_ptp_src_clock_index(hw);\n+\n+\tstatus = ice_stop_phy_timer_eth56g(hw, port, false);\n+\tif (status)\n+\t\treturn status;\n+\n+\tice_ptp_src_cmd(hw, ICE_PTP_NOP);\n+\n+\tlo = rd32(hw, GLTSYN_INCVAL_L(tmr_idx));\n+\thi = rd32(hw, GLTSYN_INCVAL_H(tmr_idx));\n+\tincval = (u64)hi << 32 | lo;\n+\n+\tstatus = ice_write_40b_phy_reg_eth56g(hw, port, PHY_REG_TIMETUS_L,\n+\t\t\t\t\t      incval);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ice_ptp_one_port_cmd_eth56g(hw, port, ICE_PTP_INIT_INCVAL,\n+\t\t\t\t\t     true);\n+\tif (status)\n+\t\treturn status;\n+\n+\tice_ptp_exec_tmr_cmd(hw);\n+\n+\tstatus = ice_sync_phy_timer_eth56g(hw, port);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Program the Tx offset */\n+\tstatus = ice_phy_cfg_tx_offset_eth56g(hw, port);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Program the Rx offset */\n+\tstatus = ice_phy_cfg_rx_offset_eth56g(hw, port);\n+\tif (status)\n+\t\treturn status;\n+\n+\tice_debug(hw, ICE_DBG_PTP, \"Enabled clock on PHY port %u\\n\", port);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_ptp_read_tx_hwtstamp_status_eth56g - Get the current TX timestamp\n+ * status mask. Returns the mask of ports where TX timestamps are available\n+ * @hw: pointer to the HW struct\n+ * @ts_status: the timestamp mask pointer\n+ */\n+enum ice_status\n+ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status)\n+{\n+\tenum ice_status status;\n+\n+\tstatus = ice_read_phy_eth56g_raw_lp(hw, PHY_PTP_INT_STATUS, ts_status,\n+\t\t\t\t\t    true);\n+\tif (status)\n+\t\treturn status;\n+\n+\tice_debug(hw, ICE_DBG_PTP, \"PHY interrupt status: %x\\n\", *ts_status);\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/* ----------------------------------------------------------------------------\n+ * E822 family functions\n  *\n  * The following functions operate on the E822 family of devices.\n  */\n@@ -1013,7 +1982,7 @@ static enum ice_status ice_ptp_init_phc_e822(struct ice_hw *hw)\n  * @time: Time to initialize the PHY port clocks to\n  *\n  * Program the PHY port registers with a new initial time value. The port\n- * clock will be initialized once the driver issues an INIT_TIME sync\n+ * clock will be initialized once the driver issues an ICE_PTP_INIT_TIME sync\n  * command. The time value is the upper 32 bits of the PHY timer, usually in\n  * units of nominal nanoseconds.\n  */\n@@ -1065,7 +2034,7 @@ ice_ptp_prep_phy_time_e822(struct ice_hw *hw, u32 time)\n  *\n  * Program the port for an atomic adjustment by writing the Tx and Rx timer\n  * registers. The atomic adjustment won't be completed until the driver issues\n- * an ADJ_TIME command.\n+ * an ICE_PTP_ADJ_TIME command.\n  *\n  * Note that time is not in units of nanoseconds. It is in clock time\n  * including the lower sub-nanosecond portion of the port timer.\n@@ -1121,7 +2090,7 @@ ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time,\n  *\n  * Prepare the PHY ports for an atomic time adjustment by programming the PHY\n  * Tx and Rx port registers. The actual adjustment is completed by issuing an\n- * ADJ_TIME or ADJ_TIME_AT_TIME sync command.\n+ * ICE_PTP_ADJ_TIME or ICE_PTP_ADJ_TIME_AT_TIME sync command.\n  */\n static enum ice_status\n ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj, bool lock_sbq)\n@@ -1157,7 +2126,7 @@ ice_ptp_prep_phy_adj_e822(struct ice_hw *hw, s32 adj, bool lock_sbq)\n  *\n  * Prepare each of the PHY ports for a new increment value by programming the\n  * port's TIMETUS registers. The new increment value will be updated after\n- * issuing an INIT_INCVAL command.\n+ * issuing an ICE_PTP_INIT_INCVAL command.\n  */\n static enum ice_status\n ice_ptp_prep_phy_incval_e822(struct ice_hw *hw, u64 incval)\n@@ -1213,7 +2182,7 @@ ice_ptp_read_phy_incval_e822(struct ice_hw *hw, u8 port, u64 *incval)\n  * @target_time: target time to program\n  *\n  * Program the PHY port Tx and Rx TIMER_CNT_ADJ registers used for the\n- * ADJ_TIME_AT_TIME command. This should be used in conjunction with\n+ * ICE_PTP_ADJ_TIME_AT_TIME command. This should be used in conjunction with\n  * ice_ptp_prep_phy_adj_e822 to program an atomic adjustment that is\n  * delayed until a specified target time.\n  *\n@@ -1331,19 +2300,19 @@ ice_ptp_one_port_cmd_e822(struct ice_hw *hw, u8 port, enum ice_ptp_tmr_cmd cmd,\n \ttmr_idx = ice_get_ptp_src_clock_index(hw);\n \tcmd_val = tmr_idx << SEL_PHY_SRC;\n \tswitch (cmd) {\n-\tcase INIT_TIME:\n+\tcase ICE_PTP_INIT_TIME:\n \t\tcmd_val |= PHY_CMD_INIT_TIME;\n \t\tbreak;\n-\tcase INIT_INCVAL:\n+\tcase ICE_PTP_INIT_INCVAL:\n \t\tcmd_val |= PHY_CMD_INIT_INCVAL;\n \t\tbreak;\n-\tcase ADJ_TIME:\n+\tcase ICE_PTP_ADJ_TIME:\n \t\tcmd_val |= PHY_CMD_ADJ_TIME;\n \t\tbreak;\n-\tcase ADJ_TIME_AT_TIME:\n+\tcase ICE_PTP_ADJ_TIME_AT_TIME:\n \t\tcmd_val |= PHY_CMD_ADJ_TIME_AT_TIME;\n \t\tbreak;\n-\tcase READ_TIME:\n+\tcase ICE_PTP_READ_TIME:\n \t\tcmd_val |= PHY_CMD_READ_TIME;\n \t\tbreak;\n \tdefault:\n@@ -2300,8 +3269,8 @@ ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port)\n  * @phy_time: on return, the 64bit PHY timer value\n  * @phc_time: on return, the lower 64bits of PHC time\n  *\n- * Issue a READ_TIME timer command to simultaneously capture the PHY and PHC\n- * timer values.\n+ * Issue a ICE_PTP_READ_TIME timer command to simultaneously capture the PHY\n+ * and PHC timer values.\n  */\n static enum ice_status\n ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,\n@@ -2314,15 +3283,15 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,\n \n \ttmr_idx = ice_get_ptp_src_clock_index(hw);\n \n-\t/* Prepare the PHC timer for a READ_TIME capture command */\n-\tice_ptp_src_cmd(hw, READ_TIME);\n+\t/* Prepare the PHC timer for a ICE_PTP_READ_TIME capture command */\n+\tice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);\n \n-\t/* Prepare the PHY timer for a READ_TIME capture command */\n-\tstatus = ice_ptp_one_port_cmd_e822(hw, port, READ_TIME, true);\n+\t/* Prepare the PHY timer for a ICE_PTP_READ_TIME capture command */\n+\tstatus = ice_ptp_one_port_cmd_e822(hw, port, ICE_PTP_READ_TIME, true);\n \tif (status)\n \t\treturn status;\n \n-\t/* Issue the sync to start the READ_TIME capture */\n+\t/* Issue the sync to start the ICE_PTP_READ_TIME capture */\n \tice_ptp_exec_tmr_cmd(hw);\n \n \t/* Read the captured PHC time from the shadow time registers */\n@@ -2355,10 +3324,11 @@ ice_read_phy_and_phc_time_e822(struct ice_hw *hw, u8 port, u64 *phy_time,\n  * @port: the PHY port to synchronize\n  *\n  * Perform an adjustment to ensure that the PHY and PHC timers are in sync.\n- * This is done by issuing a READ_TIME command which triggers a simultaneous\n- * read of the PHY timer and PHC timer. Then we use the difference to\n- * calculate an appropriate 2s complement addition to add to the PHY timer in\n- * order to ensure it reads the same value as the primary PHC timer.\n+ * This is done by issuing a ICE_PTP_READ_TIME command which triggers a\n+ * simultaneous read of the PHY timer and PHC timer. Then we use the\n+ * difference to calculate an appropriate 2s complement addition to add\n+ * to the PHY timer in order to ensure it reads the same value as the\n+ * primary PHC timer.\n  */\n static enum ice_status ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)\n {\n@@ -2388,10 +3358,13 @@ static enum ice_status ice_sync_phy_timer_e822(struct ice_hw *hw, u8 port)\n \tif (status)\n \t\tgoto err_unlock;\n \n-\tstatus = ice_ptp_one_port_cmd_e822(hw, port, ADJ_TIME, true);\n+\tstatus = ice_ptp_one_port_cmd_e822(hw, port, ICE_PTP_ADJ_TIME, true);\n \tif (status)\n \t\tgoto err_unlock;\n \n+\t/* Init PHC mstr/src cmd for exec during sync */\n+\tice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);\n+\n \t/* Issue the sync to activate the time adjustment */\n \tice_ptp_exec_tmr_cmd(hw);\n \n@@ -2513,10 +3486,13 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)\n \tif (status)\n \t\treturn status;\n \n-\tstatus = ice_ptp_one_port_cmd_e822(hw, port, INIT_INCVAL, true);\n+\tstatus = ice_ptp_one_port_cmd_e822(hw, port, ICE_PTP_INIT_INCVAL, true);\n \tif (status)\n \t\treturn status;\n \n+\t/* Init PHC mstr/src cmd for exec during sync */\n+\tice_ptp_src_cmd(hw, ICE_PTP_READ_TIME);\n+\n \tice_ptp_exec_tmr_cmd(hw);\n \n \tstatus = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);\n@@ -2538,7 +3514,7 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass)\n \tif (status)\n \t\treturn status;\n \n-\tstatus = ice_ptp_one_port_cmd_e822(hw, port, INIT_INCVAL, true);\n+\tstatus = ice_ptp_one_port_cmd_e822(hw, port, ICE_PTP_INIT_INCVAL, true);\n \tif (status)\n \t\treturn status;\n \n@@ -2870,7 +3846,7 @@ static enum ice_status ice_ptp_init_phc_e810(struct ice_hw *hw)\n  *\n  * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation setting the\n  * initial clock time. The time will not actually be programmed until the\n- * driver issues an INIT_TIME command.\n+ * driver issues an ICE_PTP_INIT_TIME command.\n  *\n  * The time value is the upper 32 bits of the PHY timer, usually in units of\n  * nominal nanoseconds.\n@@ -2906,7 +3882,7 @@ static enum ice_status ice_ptp_prep_phy_time_e810(struct ice_hw *hw, u32 time)\n  *\n  * Prepare the PHY port for an atomic adjustment by programming the PHY\n  * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual adjustment\n- * is completed by issuing an ADJ_TIME sync command.\n+ * is completed by issuing an ICE_PTP_ADJ_TIME sync command.\n  *\n  * The adjustment value only contains the portion used for the upper 32bits of\n  * the PHY timer, usually in units of nominal nanoseconds. Negative\n@@ -2949,7 +3925,7 @@ ice_ptp_prep_phy_adj_e810(struct ice_hw *hw, s32 adj, bool lock_sbq)\n  *\n  * Prepare the PHY port for a new increment value by programming the PHY\n  * ETH_GLTSYN_SHADJ_L and ETH_GLTSYN_SHADJ_H registers. The actual change is\n- * completed by issuing an INIT_INCVAL command.\n+ * completed by issuing an ICE_PTP_INIT_INCVAL command.\n  */\n static enum ice_status\n ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)\n@@ -2987,8 +3963,8 @@ ice_ptp_prep_phy_incval_e810(struct ice_hw *hw, u64 incval)\n  * Program the PHY port ETH_GLTSYN_SHTIME registers in preparation for\n  * a target time adjust, which will trigger an adjustment of the clock in the\n  * future. The actual adjustment will occur the next time the PHY port timer\n- * crosses over the provided value after the driver issues an ADJ_TIME_AT_TIME\n- * command.\n+ * crosses over the provided value after the driver issues an\n+ * ICE_PTP_ADJ_TIME_AT_TIME command.\n  *\n  * The time value is the upper 32 bits of the PHY timer, usually in units of\n  * nominal nanoseconds.\n@@ -3035,19 +4011,19 @@ ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,\n \tu32 cmd_val, val;\n \n \tswitch (cmd) {\n-\tcase INIT_TIME:\n+\tcase ICE_PTP_INIT_TIME:\n \t\tcmd_val = GLTSYN_CMD_INIT_TIME;\n \t\tbreak;\n-\tcase INIT_INCVAL:\n+\tcase ICE_PTP_INIT_INCVAL:\n \t\tcmd_val = GLTSYN_CMD_INIT_INCVAL;\n \t\tbreak;\n-\tcase ADJ_TIME:\n+\tcase ICE_PTP_ADJ_TIME:\n \t\tcmd_val = GLTSYN_CMD_ADJ_TIME;\n \t\tbreak;\n-\tcase ADJ_TIME_AT_TIME:\n+\tcase ICE_PTP_ADJ_TIME_AT_TIME:\n \t\tcmd_val = GLTSYN_CMD_ADJ_INIT_TIME;\n \t\tbreak;\n-\tcase READ_TIME:\n+\tcase ICE_PTP_READ_TIME:\n \t\tcmd_val = GLTSYN_CMD_READ_TIME;\n \t\tbreak;\n \tdefault:\n@@ -3375,19 +4351,19 @@ void ice_ptp_src_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd)\n \tcmd_val = tmr_idx << SEL_CPK_SRC;\n \n \tswitch (cmd) {\n-\tcase INIT_TIME:\n+\tcase ICE_PTP_INIT_TIME:\n \t\tcmd_val |= GLTSYN_CMD_INIT_TIME;\n \t\tbreak;\n-\tcase INIT_INCVAL:\n+\tcase ICE_PTP_INIT_INCVAL:\n \t\tcmd_val |= GLTSYN_CMD_INIT_INCVAL;\n \t\tbreak;\n-\tcase ADJ_TIME:\n+\tcase ICE_PTP_ADJ_TIME:\n \t\tcmd_val |= GLTSYN_CMD_ADJ_TIME;\n \t\tbreak;\n-\tcase ADJ_TIME_AT_TIME:\n+\tcase ICE_PTP_ADJ_TIME_AT_TIME:\n \t\tcmd_val |= GLTSYN_CMD_ADJ_INIT_TIME;\n \t\tbreak;\n-\tcase READ_TIME:\n+\tcase ICE_PTP_READ_TIME:\n \t\tcmd_val |= GLTSYN_CMD_READ_TIME;\n \t\tbreak;\n \tdefault:\n@@ -3418,10 +4394,19 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd, bool lock_sbq)\n \tice_ptp_src_cmd(hw, cmd);\n \n \t/* Next, prepare the ports */\n-\tif (ice_is_e810(hw))\n+\tswitch (hw->phy_cfg) {\n+\tcase ICE_PHY_ETH56G:\n+\t\tstatus = ice_ptp_port_cmd_eth56g(hw, cmd, lock_sbq);\n+\t\tbreak;\n+\tcase ICE_PHY_E810:\n \t\tstatus = ice_ptp_port_cmd_e810(hw, cmd, lock_sbq);\n-\telse\n+\t\tbreak;\n+\tcase ICE_PHY_E822:\n \t\tstatus = ice_ptp_port_cmd_e822(hw, cmd, lock_sbq);\n+\t\tbreak;\n+\tdefault:\n+\t\tstatus = ICE_ERR_NOT_SUPPORTED;\n+\t}\n \tif (status) {\n \t\tice_debug(hw, ICE_DBG_PTP, \"Failed to prepare PHY ports for timer command %u, status %d\\n\",\n \t\t\t  cmd, status);\n@@ -3470,7 +4455,7 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)\n \tif (status)\n \t\treturn status;\n \n-\treturn ice_ptp_tmr_cmd(hw, INIT_TIME, true);\n+\treturn ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_TIME, true);\n }\n \n /**\n@@ -3483,8 +4468,8 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw, u64 time)\n  *\n  * 1) Write the increment value to the source timer shadow registers\n  * 2) Write the increment value to the PHY timer shadow registers\n- * 3) Issue an INIT_INCVAL timer command to synchronously switch both the\n- *    source and port timers to the new increment value at the next clock\n+ * 3) Issue an ICE_PTP_INIT_INCVAL timer command to synchronously switch both\n+ *    the source and port timers to the new increment value at the next clock\n  *    cycle.\n  */\n enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval)\n@@ -3505,7 +4490,7 @@ enum ice_status ice_ptp_write_incval(struct ice_hw *hw, u64 incval)\n \tif (status)\n \t\treturn status;\n \n-\treturn ice_ptp_tmr_cmd(hw, INIT_INCVAL, true);\n+\treturn ice_ptp_tmr_cmd(hw, ICE_PTP_INIT_INCVAL, true);\n }\n \n /**\n@@ -3541,8 +4526,8 @@ enum ice_status ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval)\n  *\n  * 1) Write the adjustment to the source timer shadow registers\n  * 2) Write the adjustment to the PHY timer shadow registers\n- * 3) Issue an ADJ_TIME timer command to synchronously apply the adjustment to\n- *    both the source and port timers at the next clock cycle.\n+ * 3) Issue an ICE_PTP_ADJ_TIME timer command to synchronously apply the\n+ *    adjustment to both the source and port timers at the next clock cycle.\n  */\n enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)\n {\n@@ -3566,7 +4551,7 @@ enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)\n \tif (status)\n \t\treturn status;\n \n-\treturn ice_ptp_tmr_cmd(hw, ADJ_TIME, lock_sbq);\n+\treturn ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME, lock_sbq);\n }\n \n /**\n@@ -3582,7 +4567,8 @@ enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq)\n  * 2) Write the target time to the source timer shadow time registers\n  * 3) Write the adjustment to the PHY timers shadow adjust registers\n  * 4) Write the target time to the PHY timers shadow adjust registers\n- * 5) Issue an ADJ_TIME_AT_TIME command to initiate the atomic adjustment.\n+ * 5) Issue an ICE_PTP_ADJ_TIME_AT_TIME command to initiate the atomic\n+ *    adjustment.\n  */\n enum ice_status\n ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)\n@@ -3596,9 +4582,9 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)\n \ttime_hi = ICE_HI_DWORD(at_time);\n \n \t/* Write the desired clock adjustment into the GLTSYN_SHADJ register.\n-\t * For an ADJ_TIME_AT_TIME command, this set of registers represents\n-\t * the value to add to the clock time. It supports subtraction by\n-\t * interpreting the value as a 2's complement integer.\n+\t * For an ICE_PTP_ADJ_TIME_AT_TIME command, this set of registers\n+\t * represents the value to add to the clock time. It supports\n+\t * subtraction by interpreting the value as a 2's complement integer.\n \t */\n \twr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);\n \twr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);\n@@ -3624,7 +4610,7 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj)\n \tif (status)\n \t\treturn status;\n \n-\treturn ice_ptp_tmr_cmd(hw, ADJ_TIME_AT_TIME, true);\n+\treturn ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME_AT_TIME, true);\n }\n \n /**\ndiff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h\nindex ecb79eaea9..a030a9d4ed 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.h\n+++ b/drivers/net/ice/base/ice_ptp_hw.h\n@@ -6,11 +6,12 @@\n #define _ICE_PTP_HW_H_\n \n enum ice_ptp_tmr_cmd {\n-\tINIT_TIME,\n-\tINIT_INCVAL,\n-\tADJ_TIME,\n-\tADJ_TIME_AT_TIME,\n-\tREAD_TIME\n+\tICE_PTP_INIT_TIME,\n+\tICE_PTP_INIT_INCVAL,\n+\tICE_PTP_ADJ_TIME,\n+\tICE_PTP_ADJ_TIME_AT_TIME,\n+\tICE_PTP_READ_TIME,\n+\tICE_PTP_NOP,\n };\n \n enum ice_ptp_serdes {\n@@ -232,6 +233,39 @@ enum ice_status ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);\n enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);\n bool ice_is_pca9575_present(struct ice_hw *hw);\n \n+void\n+ice_ptp_process_cgu_err(struct ice_hw *hw, struct ice_rq_event_info *event);\n+/* ETH56G family functions */\n+enum ice_status\n+ice_read_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val);\n+enum ice_status\n+ice_write_phy_reg_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val);\n+enum ice_status\n+ice_read_phy_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 *val);\n+enum ice_status\n+ice_write_phy_mem_eth56g(struct ice_hw *hw, u8 port, u16 offset, u32 val);\n+\n+enum ice_status\n+ice_ptp_prep_port_adj_eth56g(struct ice_hw *hw, u8 port, s64 time,\n+\t\t\t     bool lock_sbq);\n+\n+enum ice_status\n+ice_ptp_read_phy_incval_eth56g(struct ice_hw *hw, u8 port, u64 *incval);\n+enum ice_status\n+ice_ptp_read_port_capture_eth56g(struct ice_hw *hw, u8 port,\n+\t\t\t\t u64 *tx_ts, u64 *rx_ts);\n+enum ice_status\n+ice_ptp_one_port_cmd_eth56g(struct ice_hw *hw, u8 port,\n+\t\t\t    enum ice_ptp_tmr_cmd cmd, bool lock_sbq);\n+enum ice_status\n+ice_ptp_read_tx_hwtstamp_status_eth56g(struct ice_hw *hw, u32 *ts_status);\n+enum ice_status\n+ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset);\n+enum ice_status\n+ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool bypass);\n+enum ice_status ice_phy_cfg_tx_offset_eth56g(struct ice_hw *hw, u8 port);\n+enum ice_status ice_phy_cfg_rx_offset_eth56g(struct ice_hw *hw, u8 port);\n+\n #define PFTSYN_SEM_BYTES\t4\n \n #define ICE_PTP_CLOCK_INDEX_0\t0x00\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex 15b12bfc8d..a17accff19 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -1135,6 +1135,13 @@ struct ice_switch_info {\n \tice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);\n };\n \n+/* PHY configuration */\n+enum ice_phy_cfg {\n+\tICE_PHY_E810 = 1,\n+\tICE_PHY_E822,\n+\tICE_PHY_ETH56G,\n+};\n+\n /* Port hardware description */\n struct ice_hw {\n \tu8 *hw_addr;\n@@ -1159,6 +1166,7 @@ struct ice_hw {\n \tu8 revision_id;\n \n \tu8 pf_id;\t\t/* device profile info */\n+\tenum ice_phy_cfg phy_cfg;\n \tu8 logical_pf_id;\n \n \tu16 max_burst_size;\t/* driver sets this value */\n@@ -1233,6 +1241,9 @@ struct ice_hw {\n #define ICE_PORTS_PER_PHY\t8\n #define ICE_NUM_EXTERNAL_PORTS\t\tICE_PORTS_PER_PHY\n \n+\t/* bitmap of enabled logical ports */\n+\tu32 ena_lports;\n+\n \t/* Active package version (currently active) */\n \tstruct ice_pkg_ver active_pkg_ver;\n \tu32 pkg_seg_id;\n",
    "prefixes": [
        "v2",
        "15/70"
    ]
}