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GET /api/patches/114996/?format=api
{ "id": 114996, "url": "http://patches.dpdk.org/api/patches/114996/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220815071306.2910599-40-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220815071306.2910599-40-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220815071306.2910599-40-qi.z.zhang@intel.com", "date": "2022-08-15T07:12:35", "name": "[39/70] net/ice/base: add data typecasting to match sizes", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "12393981cb9b025af9f1b8e6348e4ad2dd352de7", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220815071306.2910599-40-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 24307, "url": "http://patches.dpdk.org/api/series/24307/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24307", "date": "2022-08-15T07:11:56", "name": "ice base code update", "version": 1, "mbox": "http://patches.dpdk.org/series/24307/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/114996/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/114996/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3881EA00C3;\n\tMon, 15 Aug 2022 01:07:09 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9A60B42C66;\n\tMon, 15 Aug 2022 01:04:14 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id 0E9AB427F9\n for <dev@dpdk.org>; Mon, 15 Aug 2022 01:04:12 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Aug 2022 16:04:12 -0700", "from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4])\n by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:04:11 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1660518253; x=1692054253;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=yCdk+Qgnumq1eSi390+mQbhsUfSRCi8/PV0iAT+AtuY=;\n b=lBSgnoSy8V59Idw93vggQqQibu7LkIs1SMSQYeFTBhDSZm3E2CrMaw3Y\n HSN6YopgH/rJOUlf8OfbrSc4QVMicJmxkjLpnj3NGi/huZ2+4FrAnGXNB\n iEMMdfwhQyXcwYjAwanttgAhXxqAU8G0/TTaB9G7F9Y1wEw5QfD8aIOuo\n 3uBevOImWnpb7EoSKz05uYspI3Lh88hQAVlGedhlLhA8n/dTuaFRKvyMq\n /xg5TcCOgLGYrWBzamWFfrcQErw+6PEFJ21BwppB1guzxVAUYlY4gNg7E\n SHqx/chT4jdQl3oGjfekK7/9N95wqtJWAmAEp15rCfy8Ud78FjTrsAJET A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10439\"; a=\"289427618\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"289427618\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"934296767\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Vignesh Sridhar <vignesh.sridhar@intel.com>", "Subject": "[PATCH 39/70] net/ice/base: add data typecasting to match sizes", "Date": "Mon, 15 Aug 2022 03:12:35 -0400", "Message-Id": "<20220815071306.2910599-40-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20220815071306.2910599-1-qi.z.zhang@intel.com>", "References": "<20220815071306.2910599-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adding typecast to variables to avoid compiler warnings generated if\nvariables of a particular data type are assigned to ones of a\nsmaller data type. For example assigning an unsigned 16 bit integer\nto an 8 bit integer could trigger data loss warnings or errors.\n\nSigned-off-by: Vignesh Sridhar <vignesh.sridhar@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_acl_ctrl.c | 34 +++++++++++++--------------\n drivers/net/ice/base/ice_adminq_cmd.h | 4 ++--\n drivers/net/ice/base/ice_common.c | 13 +++++-----\n drivers/net/ice/base/ice_dcb.c | 8 +++----\n drivers/net/ice/base/ice_flex_pipe.c | 2 +-\n drivers/net/ice/base/ice_flow.c | 26 ++++++++++----------\n drivers/net/ice/base/ice_nvm.c | 2 +-\n drivers/net/ice/base/ice_sched.c | 5 ++--\n drivers/net/ice/base/ice_switch.c | 12 +++++-----\n 9 files changed, 52 insertions(+), 54 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_acl_ctrl.c b/drivers/net/ice/base/ice_acl_ctrl.c\nindex 27aa6b62d4..2dd08e326e 100644\n--- a/drivers/net/ice/base/ice_acl_ctrl.c\n+++ b/drivers/net/ice/base/ice_acl_ctrl.c\n@@ -6,10 +6,10 @@\n #include \"ice_flow.h\"\n \n /* Determine the TCAM index of entry 'e' within the ACL table */\n-#define ICE_ACL_TBL_TCAM_IDX(e) ((e) / ICE_AQC_ACL_TCAM_DEPTH)\n+#define ICE_ACL_TBL_TCAM_IDX(e) ((u8)((e) / ICE_AQC_ACL_TCAM_DEPTH))\n \n /* Determine the entry index within the TCAM */\n-#define ICE_ACL_TBL_TCAM_ENTRY_IDX(e) ((e) % ICE_AQC_ACL_TCAM_DEPTH)\n+#define ICE_ACL_TBL_TCAM_ENTRY_IDX(e) ((u16)((e) % ICE_AQC_ACL_TCAM_DEPTH))\n \n #define ICE_ACL_SCEN_ENTRY_INVAL 0xFFFF\n \n@@ -251,10 +251,8 @@ ice_acl_assign_act_mems_to_tcam(struct ice_acl_tbl *tbl, u8 cur_tcam,\n */\n static void ice_acl_divide_act_mems_to_tcams(struct ice_acl_tbl *tbl)\n {\n-\tu16 num_cscd, stack_level, stack_idx, min_act_mem;\n-\tu8 tcam_idx = tbl->first_tcam;\n-\tu16 max_idx_to_get_extra;\n-\tu8 mem_idx = 0;\n+\tu16 num_cscd, stack_level, stack_idx, max_idx_to_get_extra;\n+\tu8 min_act_mem, tcam_idx = tbl->first_tcam, mem_idx = 0;\n \n \t/* Determine number of stacked TCAMs */\n \tstack_level = DIVIDE_AND_ROUND_UP(tbl->info.depth,\n@@ -326,7 +324,8 @@ ice_acl_create_tbl(struct ice_hw *hw, struct ice_acl_tbl_params *params)\n \tdepth = ICE_ALIGN(params->depth, ICE_ACL_ENTRY_ALLOC_UNIT);\n \n \tif (params->entry_act_pairs < width / ICE_AQC_ACL_KEY_WIDTH_BYTES) {\n-\t\tparams->entry_act_pairs = width / ICE_AQC_ACL_KEY_WIDTH_BYTES;\n+\t\tparams->entry_act_pairs =\n+\t\t\t(u8)(width / ICE_AQC_ACL_KEY_WIDTH_BYTES);\n \n \t\tif (params->entry_act_pairs > ICE_AQC_TBL_MAX_ACTION_PAIRS)\n \t\t\tparams->entry_act_pairs = ICE_AQC_TBL_MAX_ACTION_PAIRS;\n@@ -587,7 +586,7 @@ ice_acl_fill_tcam_select(struct ice_aqc_acl_scen *scen_buf,\n \t */\n \tfor (j = 0; j < ICE_AQC_ACL_KEY_WIDTH_BYTES; j++) {\n \t\t/* PKT DIR uses the 1st location of Byte Selection Base: + 1 */\n-\t\tu8 val = ICE_AQC_ACL_BYTE_SEL_BASE + 1 + idx;\n+\t\tu8 val = (u8)(ICE_AQC_ACL_BYTE_SEL_BASE + 1 + idx);\n \n \t\tif (tcam_idx_in_cascade == cascade_cnt - 1) {\n \t\t\tif (j == ICE_ACL_SCEN_RNG_CHK_IDX_IN_TCAM)\n@@ -793,7 +792,7 @@ ice_acl_create_scen(struct ice_hw *hw, u16 match_width, u16 num_entries,\n \t/* set the START_SET bit at the beginning of the stack */\n \tscen_buf.tcam_cfg[k].start_cmp_set |= ICE_AQC_ACL_ALLOC_SCE_START_SET;\n \twhile (k <= last_tcam) {\n-\t\tu8 last_tcam_idx_cascade = cascade_cnt + k - 1;\n+\t\tu16 last_tcam_idx_cascade = cascade_cnt + k - 1;\n \n \t\t/* set start_cmp for the first cascaded TCAM */\n \t\tscen_buf.tcam_cfg[k].start_cmp_set |=\n@@ -972,10 +971,10 @@ ice_acl_add_entry(struct ice_hw *hw, struct ice_acl_scen *scen,\n \t\t enum ice_acl_entry_prio prio, u8 *keys, u8 *inverts,\n \t\t struct ice_acl_act_entry *acts, u8 acts_cnt, u16 *entry_idx)\n {\n-\tu8 i, entry_tcam, num_cscd, offset;\n \tstruct ice_aqc_acl_data buf;\n+\tu8 entry_tcam, offset;\n+\tu16 i, num_cscd, idx;\n \tenum ice_status status = ICE_SUCCESS;\n-\tu16 idx;\n \n \tif (!scen)\n \t\treturn ICE_ERR_DOES_NOT_EXIST;\n@@ -1005,7 +1004,7 @@ ice_acl_add_entry(struct ice_hw *hw, struct ice_acl_scen *scen,\n \t\t * be programmed first; the TCAM entry of the leftmost TCAM\n \t\t * should be programmed last.\n \t\t */\n-\t\toffset = num_cscd - i - 1;\n+\t\toffset = (u8)(num_cscd - i - 1);\n \t\tice_memcpy(&buf.entry_key.val,\n \t\t\t &keys[offset * sizeof(buf.entry_key.val)],\n \t\t\t sizeof(buf.entry_key.val), ICE_NONDMA_TO_NONDMA);\n@@ -1049,10 +1048,9 @@ ice_acl_prog_act(struct ice_hw *hw, struct ice_acl_scen *scen,\n \t\t struct ice_acl_act_entry *acts, u8 acts_cnt,\n \t\t u16 entry_idx)\n {\n-\tu8 entry_tcam, num_cscd, i, actx_idx = 0;\n+\tu16 idx, entry_tcam, num_cscd, i, actx_idx = 0;\n \tstruct ice_aqc_actpair act_buf;\n \tenum ice_status status = ICE_SUCCESS;\n-\tu16 idx;\n \n \tif (entry_idx >= scen->num_entry)\n \t\treturn ICE_ERR_MAX_LIMIT;\n@@ -1112,9 +1110,9 @@ ice_acl_rem_entry(struct ice_hw *hw, struct ice_acl_scen *scen, u16 entry_idx)\n {\n \tstruct ice_aqc_actpair act_buf;\n \tstruct ice_aqc_acl_data buf;\n-\tu8 entry_tcam, num_cscd, i;\n \tenum ice_status status = ICE_SUCCESS;\n-\tu16 idx;\n+\tu16 num_cscd, idx, i;\n+\tu8 entry_tcam;\n \n \tif (!scen)\n \t\treturn ICE_ERR_DOES_NOT_EXIST;\n@@ -1135,8 +1133,8 @@ ice_acl_rem_entry(struct ice_hw *hw, struct ice_acl_scen *scen, u16 entry_idx)\n \t/* invalidate the flow entry */\n \tice_memset(&buf, 0, sizeof(buf), ICE_NONDMA_MEM);\n \tfor (i = 0; i < num_cscd; i++) {\n-\t\tstatus = ice_aq_program_acl_entry(hw, entry_tcam + i, idx, &buf,\n-\t\t\t\t\t\t NULL);\n+\t\tstatus = ice_aq_program_acl_entry(hw, (u8)(entry_tcam + i),\n+\t\t\t\t\t\t idx, &buf, NULL);\n \t\tif (status)\n \t\t\tice_debug(hw, ICE_DBG_ACL, \"AQ program ACL entry failed status: %d\\n\",\n \t\t\t\t status);\ndiff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex 8efbb137da..7f9bdd3cb0 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -2802,8 +2802,8 @@ struct ice_aqc_get_pkg_info_resp {\n struct ice_aqc_driver_shared_params {\n \tu8 set_or_get_op;\n #define ICE_AQC_DRIVER_PARAM_OP_MASK\t\tBIT(0)\n-#define ICE_AQC_DRIVER_PARAM_SET\t\t0\n-#define ICE_AQC_DRIVER_PARAM_GET\t\t1\n+#define ICE_AQC_DRIVER_PARAM_SET\t\t((u8)0)\n+#define ICE_AQC_DRIVER_PARAM_GET\t\t((u8)1)\n \tu8 param_indx;\n #define ICE_AQC_DRIVER_PARAM_MAX_IDX\t\t15\n \tu8 rsvd[2];\ndiff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex db78bf4152..f8a3017df8 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -2420,7 +2420,7 @@ ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,\n \tcase ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2:\n \tcase ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3:\n \t{\n-\t\tu8 index = cap - ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0;\n+\t\tu8 index = (u8)(cap - ICE_AQC_CAPS_EXT_TOPO_DEV_IMG0);\n \n \t\tcaps->ext_topo_dev_img_ver_high[index] = number;\n \t\tcaps->ext_topo_dev_img_ver_low[index] = logical_id;\n@@ -2534,11 +2534,10 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,\n \tinfo->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);\n \tinfo->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);\n \n-\tinfo->clk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S;\n \tinfo->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);\n-\n-\tif (info->clk_freq < NUM_ICE_TIME_REF_FREQ) {\n-\t\tinfo->time_ref = (enum ice_time_ref_freq)info->clk_freq;\n+\tclk_freq = (number & ICE_TS_CLK_FREQ_M) >> ICE_TS_CLK_FREQ_S;\n+\tif (clk_freq < NUM_ICE_TIME_REF_FREQ) {\n+\t\tinfo->time_ref = (enum ice_time_ref_freq)clk_freq;\n \t} else {\n \t\t/* Unknown clock frequency, so assume a (probably incorrect)\n \t\t * default to avoid out-of-bounds look ups of frequency\n@@ -5621,7 +5620,7 @@ ice_aq_set_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,\n \tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params);\n \n \tcmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_SET;\n-\tcmd->param_indx = idx;\n+\tcmd->param_indx = (u8)idx;\n \tcmd->param_val = CPU_TO_LE32(value);\n \n \treturn ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n@@ -5655,7 +5654,7 @@ ice_aq_get_driver_param(struct ice_hw *hw, enum ice_aqc_driver_params idx,\n \tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_driver_shared_params);\n \n \tcmd->set_or_get_op = ICE_AQC_DRIVER_PARAM_GET;\n-\tcmd->param_indx = idx;\n+\tcmd->param_indx = (u8)idx;\n \n \tstatus = ice_aq_send_cmd(hw, &desc, NULL, 0, cd);\n \tif (status)\ndiff --git a/drivers/net/ice/base/ice_dcb.c b/drivers/net/ice/base/ice_dcb.c\nindex 3d630757f8..7a850e62f4 100644\n--- a/drivers/net/ice/base/ice_dcb.c\n+++ b/drivers/net/ice/base/ice_dcb.c\n@@ -691,9 +691,9 @@ ice_aq_start_stop_dcbx(struct ice_hw *hw, bool start_dcbx_agent,\n \t\t bool *dcbx_agent_status, struct ice_sq_cd *cd)\n {\n \tstruct ice_aqc_lldp_stop_start_specific_agent *cmd;\n-\tenum ice_status status;\n+\tenum ice_adminq_opc opcode;\n \tstruct ice_aq_desc desc;\n-\tu16 opcode;\n+\tenum ice_status status;\n \n \tcmd = &desc.params.lldp_agent_ctrl;\n \n@@ -885,8 +885,8 @@ ice_cee_to_dcb_cfg(struct ice_aqc_get_cee_dcb_cfg_resp *cee_cfg,\n \t\t */\n \t\tif (!err && sync && oper) {\n \t\t\tdcbcfg->app[app_index].priority =\n-\t\t\t\t(app_prio & ice_aqc_cee_app_mask) >>\n-\t\t\t\tice_aqc_cee_app_shift;\n+\t\t\t\t(u8)((app_prio & ice_aqc_cee_app_mask) >>\n+\t\t\t\t ice_aqc_cee_app_shift);\n \t\t\tdcbcfg->app[app_index].selector = ice_app_sel_type;\n \t\t\tdcbcfg->app[app_index].prot_id = ice_app_prot_id_type;\n \t\t\tapp_index++;\ndiff --git a/drivers/net/ice/base/ice_flex_pipe.c b/drivers/net/ice/base/ice_flex_pipe.c\nindex 2d95ce4d74..63ddda2df9 100644\n--- a/drivers/net/ice/base/ice_flex_pipe.c\n+++ b/drivers/net/ice/base/ice_flex_pipe.c\n@@ -3445,7 +3445,7 @@ ice_rem_vsig(struct ice_hw *hw, enum ice_block blk, u16 vsig,\n \t\t\tp->type = ICE_VSIG_REM;\n \t\t\tp->orig_vsig = vsig;\n \t\t\tp->vsig = ICE_DEFAULT_VSIG;\n-\t\t\tp->vsi = vsi_cur - hw->blk[blk].xlt2.vsis;\n+\t\t\tp->vsi = (u16)(vsi_cur - hw->blk[blk].xlt2.vsis);\n \n \t\t\tLIST_ADD(&p->list_entry, chg);\n \ndiff --git a/drivers/net/ice/base/ice_flow.c b/drivers/net/ice/base/ice_flow.c\nindex b196e51276..80e7a447c3 100644\n--- a/drivers/net/ice/base/ice_flow.c\n+++ b/drivers/net/ice/base/ice_flow.c\n@@ -1325,7 +1325,7 @@ ice_flow_xtract_pkt_flags(struct ice_hw *hw,\n \t\t\t struct ice_flow_prof_params *params,\n \t\t\t enum ice_flex_mdid_pkt_flags flags)\n {\n-\tu8 fv_words = hw->blk[params->blk].es.fvw;\n+\tu8 fv_words = (u8)hw->blk[params->blk].es.fvw;\n \tu8 idx;\n \n \t/* Make sure the number of extraction sequence entries required does not\n@@ -1341,7 +1341,7 @@ ice_flow_xtract_pkt_flags(struct ice_hw *hw,\n \t\tidx = params->es_cnt;\n \n \tparams->es[idx].prot_id = ICE_PROT_META_ID;\n-\tparams->es[idx].off = flags;\n+\tparams->es[idx].off = (u16)flags;\n \tparams->es_cnt++;\n \n \treturn ICE_SUCCESS;\n@@ -1364,8 +1364,8 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,\n \t\t u8 seg, enum ice_flow_field fld, u64 match)\n {\n \tenum ice_flow_field sib = ICE_FLOW_FIELD_IDX_MAX;\n+\tu8 fv_words = (u8)hw->blk[params->blk].es.fvw;\n \tenum ice_prot_id prot_id = ICE_PROT_ID_INVAL;\n-\tu8 fv_words = hw->blk[params->blk].es.fvw;\n \tstruct ice_flow_fld_info *flds;\n \tu16 cnt, ese_bits, i;\n \tu16 sib_mask = 0;\n@@ -1548,7 +1548,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,\n \t */\n \tese_bits = ICE_FLOW_FV_EXTRACT_SZ * BITS_PER_BYTE;\n \n-\tflds[fld].xtrct.prot_id = prot_id;\n+\tflds[fld].xtrct.prot_id = (u8)prot_id;\n \tflds[fld].xtrct.off = (ice_flds_info[fld].off / ese_bits) *\n \t\tICE_FLOW_FV_EXTRACT_SZ;\n \tflds[fld].xtrct.disp = (u8)(ice_flds_info[fld].off % ese_bits);\n@@ -1590,7 +1590,7 @@ ice_flow_xtract_fld(struct ice_hw *hw, struct ice_flow_prof_params *params,\n \t\t\telse\n \t\t\t\tidx = params->es_cnt;\n \n-\t\t\tparams->es[idx].prot_id = prot_id;\n+\t\t\tparams->es[idx].prot_id = (u8)prot_id;\n \t\t\tparams->es[idx].off = off;\n \t\t\tparams->mask[idx] = mask | sib_mask;\n \t\t\tparams->es_cnt++;\n@@ -1769,10 +1769,10 @@ ice_flow_acl_def_entry_frmt(struct ice_flow_prof_params *params)\n \n \tfor (i = 0; i < params->prof->segs_cnt; i++) {\n \t\tstruct ice_flow_seg_info *seg = ¶ms->prof->segs[i];\n-\t\tu8 j;\n+\t\tu16 j;\n \n \t\tice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,\n-\t\t\t\t ICE_FLOW_FIELD_IDX_MAX) {\n+\t\t\t\t (u16)ICE_FLOW_FIELD_IDX_MAX) {\n \t\t\tstruct ice_flow_fld_info *fld = &seg->fields[j];\n \n \t\t\tfld->entry.mask = ICE_FLOW_FLD_OFF_INVAL;\n@@ -2765,7 +2765,7 @@ ice_flow_acl_check_actions(struct ice_hw *hw, struct ice_flow_action *acts,\n \t\t/* If the caller want to add two actions of the same type, then\n \t\t * it is considered invalid configuration.\n \t\t */\n-\t\tif (ice_test_and_set_bit(acts[i].type, dup_check))\n+\t\tif (ice_test_and_set_bit((u16)acts[i].type, dup_check))\n \t\t\treturn ICE_ERR_PARAM;\n \t}\n \n@@ -2826,7 +2826,7 @@ ice_flow_acl_frmt_entry_range(u16 fld, struct ice_flow_fld_info *info,\n \t\t\t(*(u16 *)(data + info->src.last)) << info->xtrct.disp;\n \t\tu16 new_low =\n \t\t\t(*(u16 *)(data + info->src.val)) << info->xtrct.disp;\n-\t\tu8 range_idx = info->entry.val;\n+\t\tu8 range_idx = (u8)info->entry.val;\n \n \t\trange_buf->checker_cfg[range_idx].low_boundary =\n \t\t\tCPU_TO_BE16(new_low);\n@@ -2983,10 +2983,10 @@ ice_flow_acl_frmt_entry(struct ice_hw *hw, struct ice_flow_prof *prof,\n \n \tfor (i = 0; i < prof->segs_cnt; i++) {\n \t\tstruct ice_flow_seg_info *seg = &prof->segs[i];\n-\t\tu8 j;\n+\t\tu16 j;\n \n \t\tice_for_each_set_bit(j, (ice_bitmap_t *)&seg->match,\n-\t\t\t\t ICE_FLOW_FIELD_IDX_MAX) {\n+\t\t\t\t (u16)ICE_FLOW_FIELD_IDX_MAX) {\n \t\t\tstruct ice_flow_fld_info *info = &seg->fields[j];\n \n \t\t\tif (info->type == ICE_FLOW_FLD_TYPE_RANGE)\n@@ -3753,13 +3753,13 @@ ice_flow_set_rss_seg_info(struct ice_flow_seg_info *segs, u8 seg_cnt,\n {\n \tstruct ice_flow_seg_info *seg;\n \tu64 val;\n-\tu8 i;\n+\tu16 i;\n \n \t/* set inner most segment */\n \tseg = &segs[seg_cnt - 1];\n \n \tice_for_each_set_bit(i, (const ice_bitmap_t *)&cfg->hash_flds,\n-\t\t\t ICE_FLOW_FIELD_IDX_MAX)\n+\t\t\t (u16)ICE_FLOW_FIELD_IDX_MAX)\n \t\tice_flow_set_fld(seg, (enum ice_flow_field)i,\n \t\t\t\t ICE_FLOW_FLD_OFF_INVAL, ICE_FLOW_FLD_OFF_INVAL,\n \t\t\t\t ICE_FLOW_FLD_OFF_INVAL, false);\ndiff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nindex ad2496e873..293b71905d 100644\n--- a/drivers/net/ice/base/ice_nvm.c\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -171,7 +171,7 @@ ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)\n \tstatus = ice_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true);\n \n \t/* Report the number of words successfully read */\n-\t*words = bytes / 2;\n+\t*words = (u16)(bytes / 2);\n \n \t/* Byte swap the words up to the amount we actually read */\n \tfor (i = 0; i < *words; i++)\ndiff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c\nindex 4d31e96fd0..f87b1c4897 100644\n--- a/drivers/net/ice/base/ice_sched.c\n+++ b/drivers/net/ice/base/ice_sched.c\n@@ -1369,9 +1369,10 @@ enum ice_status ice_sched_query_res_alloc(struct ice_hw *hw)\n \tif (status)\n \t\tgoto sched_query_out;\n \n-\thw->num_tx_sched_layers = LE16_TO_CPU(buf->sched_props.logical_levels);\n+\thw->num_tx_sched_layers =\n+\t\t(u8)LE16_TO_CPU(buf->sched_props.logical_levels);\n \thw->num_tx_sched_phys_layers =\n-\t\tLE16_TO_CPU(buf->sched_props.phys_levels);\n+\t\t(u8)LE16_TO_CPU(buf->sched_props.phys_levels);\n \thw->flattened_layers = buf->sched_props.flattening_bitmap;\n \thw->max_cgds = buf->sched_props.max_pf_cgds;\n \ndiff --git a/drivers/net/ice/base/ice_switch.c b/drivers/net/ice/base/ice_switch.c\nindex edcfa89bcb..a8f83f62ff 100644\n--- a/drivers/net/ice/base/ice_switch.c\n+++ b/drivers/net/ice/base/ice_switch.c\n@@ -2272,8 +2272,8 @@ ice_get_recp_frm_fw(struct ice_hw *hw, struct ice_sw_recipe *recps, u8 rid,\n \t\t\t\t ~ICE_AQ_RECIPE_RESULT_EN, result_bm);\n \n \t\t/* get the first profile that is associated with rid */\n-\t\tprof = ice_find_first_bit(recipe_to_profile[idx],\n-\t\t\t\t\t ICE_MAX_NUM_PROFILES);\n+\t\tprof = (u8)ice_find_first_bit(recipe_to_profile[idx],\n+\t\t\t\t\t ICE_MAX_NUM_PROFILES);\n \t\tfor (i = 0; i < ICE_NUM_WORDS_RECIPE; i++) {\n \t\t\tu8 lkup_indx = root_bufs.content.lkup_indx[i + 1];\n \n@@ -4023,7 +4023,7 @@ ice_add_counter_act(struct ice_hw *hw, struct ice_fltr_mgmt_list_entry *m_ent,\n \t\t\t\t ice_aqc_opc_update_sw_rules, NULL);\n \tif (!status) {\n \t\tm_ent->lg_act_idx = l_id;\n-\t\tm_ent->counter_index = counter_id;\n+\t\tm_ent->counter_index = (u8)counter_id;\n \t}\n \n \tice_free(hw, lg_act);\n@@ -6341,7 +6341,7 @@ ice_remove_vsi_lkup_fltr(struct ice_hw *hw, u16 vsi_handle,\n \t\tbreak;\n \tcase ICE_SW_LKUP_PROMISC:\n \tcase ICE_SW_LKUP_PROMISC_VLAN:\n-\t\tice_remove_promisc(hw, lkup, &remove_list_head);\n+\t\tice_remove_promisc(hw, (u8)lkup, &remove_list_head);\n \t\tbreak;\n \tcase ICE_SW_LKUP_MAC_VLAN:\n \t\tice_remove_mac_vlan(hw, &remove_list_head);\n@@ -7183,7 +7183,7 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,\n \t/* Allocate the recipe resources, and configure them according to the\n \t * match fields from protocol headers and extracted field vectors.\n \t */\n-\tchain_idx = ice_find_first_bit(result_idx_bm, ICE_MAX_FV_WORDS);\n+\tchain_idx = (u8)ice_find_first_bit(result_idx_bm, ICE_MAX_FV_WORDS);\n \tLIST_FOR_EACH_ENTRY(entry, &rm->rg_list, ice_recp_grp_entry, l_entry) {\n \t\tu8 i;\n \n@@ -7376,7 +7376,7 @@ ice_add_sw_recipe(struct ice_hw *hw, struct ice_sw_recipe *rm,\n \t\tis_root = (rm->root_rid == entry->rid);\n \t\trecp->is_root = is_root;\n \n-\t\trecp->root_rid = entry->rid;\n+\t\trecp->root_rid = (u8)entry->rid;\n \t\trecp->big_recp = (is_root && rm->n_grp_count > 1);\n \n \t\tice_memcpy(&recp->ext_words, entry->r_group.pairs,\n", "prefixes": [ "39/70" ] }