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{
    "id": 114969,
    "url": "http://patches.dpdk.org/api/patches/114969/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220815071306.2910599-13-qi.z.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220815071306.2910599-13-qi.z.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220815071306.2910599-13-qi.z.zhang@intel.com",
    "date": "2022-08-15T07:12:08",
    "name": "[12/70] net/ice/base: move code block",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "b63dca9cbb74cdf7bd6c27acfb97e6ea8b4bca2a",
    "submitter": {
        "id": 504,
        "url": "http://patches.dpdk.org/api/people/504/?format=api",
        "name": "Qi Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patches.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220815071306.2910599-13-qi.z.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 24307,
            "url": "http://patches.dpdk.org/api/series/24307/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24307",
            "date": "2022-08-15T07:11:56",
            "name": "ice base code update",
            "version": 1,
            "mbox": "http://patches.dpdk.org/series/24307/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/114969/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/114969/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
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            "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"934296590\""
        ],
        "X-ExtLoop1": "1",
        "From": "Qi Zhang <qi.z.zhang@intel.com>",
        "To": "qiming.yang@intel.com",
        "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Sergey Temerkhanov <sergey.temerkhanov@intel.com>",
        "Subject": "[PATCH 12/70] net/ice/base: move code block",
        "Date": "Mon, 15 Aug 2022 03:12:08 -0400",
        "Message-Id": "<20220815071306.2910599-13-qi.z.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.31.1",
        "In-Reply-To": "<20220815071306.2910599-1-qi.z.zhang@intel.com>",
        "References": "<20220815071306.2910599-1-qi.z.zhang@intel.com>",
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    "content": "Move some code block to the beginning of ice_ptp_hw.c to align\nwithkernel driver.\n\nSigned-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_ptp_hw.c | 997 +++++++++++++++---------------\n 1 file changed, 498 insertions(+), 499 deletions(-)",
    "diff": "diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex 23d90b127d..22d0774dd7 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -101,6 +101,286 @@ u64 ice_ptp_read_src_incval(struct ice_hw *hw)\n \treturn ((u64)(hi & INCVAL_HIGH_M) << 32) | lo;\n }\n \n+/**\n+ * ice_read_cgu_reg_e822 - Read a CGU register\n+ * @hw: pointer to the HW struct\n+ * @addr: Register address to read\n+ * @val: storage for register value read\n+ *\n+ * Read the contents of a register of the Clock Generation Unit. Only\n+ * applicable to E822 devices.\n+ */\n+static enum ice_status\n+ice_read_cgu_reg_e822(struct ice_hw *hw, u16 addr, u32 *val)\n+{\n+\tstruct ice_sbq_msg_input cgu_msg;\n+\tenum ice_status status;\n+\n+\tcgu_msg.opcode = ice_sbq_msg_rd;\n+\tcgu_msg.dest_dev = cgu;\n+\tcgu_msg.msg_addr_low = addr;\n+\tcgu_msg.msg_addr_high = 0x0;\n+\n+\tstatus = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read CGU register 0x%04x, status %d\\n\",\n+\t\t\t  addr, status);\n+\t\treturn status;\n+\t}\n+\n+\t*val = cgu_msg.data;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_write_cgu_reg_e822 - Write a CGU register\n+ * @hw: pointer to the HW struct\n+ * @addr: Register address to write\n+ * @val: value to write into the register\n+ *\n+ * Write the specified value to a register of the Clock Generation Unit. Only\n+ * applicable to E822 devices.\n+ */\n+static enum ice_status\n+ice_write_cgu_reg_e822(struct ice_hw *hw, u16 addr, u32 val)\n+{\n+\tstruct ice_sbq_msg_input cgu_msg;\n+\tenum ice_status status;\n+\n+\tcgu_msg.opcode = ice_sbq_msg_wr;\n+\tcgu_msg.dest_dev = cgu;\n+\tcgu_msg.msg_addr_low = addr;\n+\tcgu_msg.msg_addr_high = 0x0;\n+\tcgu_msg.data = val;\n+\n+\tstatus = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write CGU register 0x%04x, status %d\\n\",\n+\t\t\t  addr, status);\n+\t\treturn status;\n+\t}\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_clk_freq_str - Convert time_ref_freq to string\n+ * @clk_freq: Clock frequency\n+ *\n+ * Convert the specified TIME_REF clock frequency to a string.\n+ */\n+static const char *ice_clk_freq_str(u8 clk_freq)\n+{\n+\tswitch ((enum ice_time_ref_freq)clk_freq) {\n+\tcase ICE_TIME_REF_FREQ_25_000:\n+\t\treturn \"25 MHz\";\n+\tcase ICE_TIME_REF_FREQ_122_880:\n+\t\treturn \"122.88 MHz\";\n+\tcase ICE_TIME_REF_FREQ_125_000:\n+\t\treturn \"125 MHz\";\n+\tcase ICE_TIME_REF_FREQ_153_600:\n+\t\treturn \"153.6 MHz\";\n+\tcase ICE_TIME_REF_FREQ_156_250:\n+\t\treturn \"156.25 MHz\";\n+\tcase ICE_TIME_REF_FREQ_245_760:\n+\t\treturn \"245.76 MHz\";\n+\tdefault:\n+\t\treturn \"Unknown\";\n+\t}\n+}\n+\n+/**\n+ * ice_clk_src_str - Convert time_ref_src to string\n+ * @clk_src: Clock source\n+ *\n+ * Convert the specified clock source to its string name.\n+ */\n+static const char *ice_clk_src_str(u8 clk_src)\n+{\n+\tswitch ((enum ice_clk_src)clk_src) {\n+\tcase ICE_CLK_SRC_TCX0:\n+\t\treturn \"TCX0\";\n+\tcase ICE_CLK_SRC_TIME_REF:\n+\t\treturn \"TIME_REF\";\n+\tdefault:\n+\t\treturn \"Unknown\";\n+\t}\n+}\n+\n+/**\n+ * ice_cfg_cgu_pll_e822 - Configure the Clock Generation Unit\n+ * @hw: pointer to the HW struct\n+ * @clk_freq: Clock frequency to program\n+ * @clk_src: Clock source to select (TIME_REF, or TCX0)\n+ *\n+ * Configure the Clock Generation Unit with the desired clock frequency and\n+ * time reference, enabling the PLL which drives the PTP hardware clock.\n+ */\n+enum ice_status\n+ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,\n+\t\t     enum ice_clk_src clk_src)\n+{\n+\tunion tspll_ro_bwm_lf bwm_lf;\n+\tunion nac_cgu_dword19 dw19;\n+\tunion nac_cgu_dword22 dw22;\n+\tunion nac_cgu_dword24 dw24;\n+\tunion nac_cgu_dword9 dw9;\n+\tenum ice_status status;\n+\n+\tif (clk_freq >= NUM_ICE_TIME_REF_FREQ) {\n+\t\tice_warn(hw, \"Invalid TIME_REF frequency %u\\n\", clk_freq);\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tif (clk_src >= NUM_ICE_CLK_SRC) {\n+\t\tice_warn(hw, \"Invalid clock source %u\\n\", clk_src);\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tif (clk_src == ICE_CLK_SRC_TCX0 &&\n+\t    clk_freq != ICE_TIME_REF_FREQ_25_000) {\n+\t\tice_warn(hw, \"TCX0 only supports 25 MHz frequency\\n\");\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n+\n+\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD9, &dw9.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Log the current clock configuration */\n+\tice_debug(hw, ICE_DBG_PTP, \"Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\\n\",\n+\t\t  dw24.field.ts_pll_enable ? \"enabled\" : \"disabled\",\n+\t\t  ice_clk_src_str(dw24.field.time_ref_sel),\n+\t\t  ice_clk_freq_str(dw9.field.time_ref_freq_sel),\n+\t\t  bwm_lf.field.plllock_true_lock_cri ? \"locked\" : \"unlocked\");\n+\n+\t/* Disable the PLL before changing the clock source or frequency */\n+\tif (dw24.field.ts_pll_enable) {\n+\t\tdw24.field.ts_pll_enable = 0;\n+\n+\t\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\t/* Set the frequency */\n+\tdw9.field.time_ref_freq_sel = clk_freq;\n+\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD9, dw9.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Configure the TS PLL feedback divisor */\n+\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD19, &dw19.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\tdw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;\n+\tdw19.field.tspll_ndivratio = 1;\n+\n+\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD19, dw19.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Configure the TS PLL post divisor */\n+\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD22, &dw22.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\tdw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;\n+\tdw22.field.time1588clk_sel_div2 = 0;\n+\n+\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD22, dw22.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Configure the TS PLL pre divisor and clock source */\n+\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\tdw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;\n+\tdw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;\n+\tdw24.field.time_ref_sel = clk_src;\n+\n+\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Finally, enable the PLL */\n+\tdw24.field.ts_pll_enable = 1;\n+\n+\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Wait to verify if the PLL locks */\n+\tice_msec_delay(1, true);\n+\n+\tstatus = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\tif (!bwm_lf.field.plllock_true_lock_cri) {\n+\t\tice_warn(hw, \"CGU PLL failed to lock\\n\");\n+\t\treturn ICE_ERR_NOT_READY;\n+\t}\n+\n+\t/* Log the current clock configuration */\n+\tice_debug(hw, ICE_DBG_PTP, \"New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\\n\",\n+\t\t  dw24.field.ts_pll_enable ? \"enabled\" : \"disabled\",\n+\t\t  ice_clk_src_str(dw24.field.time_ref_sel),\n+\t\t  ice_clk_freq_str(dw9.field.time_ref_freq_sel),\n+\t\t  bwm_lf.field.plllock_true_lock_cri ? \"locked\" : \"unlocked\");\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_init_cgu_e822 - Initialize CGU with settings from firmware\n+ * @hw: pointer to the HW structure\n+ *\n+ * Initialize the Clock Generation Unit of the E822 device.\n+ */\n+static enum ice_status ice_init_cgu_e822(struct ice_hw *hw)\n+{\n+\tstruct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;\n+\tunion tspll_cntr_bist_settings cntr_bist;\n+\tenum ice_status status;\n+\n+\tstatus = ice_read_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,\n+\t\t\t\t       &cntr_bist.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Disable sticky lock detection so lock status reported is accurate */\n+\tcntr_bist.field.i_plllock_sel_0 = 0;\n+\tcntr_bist.field.i_plllock_sel_1 = 0;\n+\n+\tstatus = ice_write_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,\n+\t\t\t\t\tcntr_bist.val);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Configure the CGU PLL using the parameters from the function\n+\t * capabilities.\n+\t */\n+\tstatus = ice_cfg_cgu_pll_e822(hw, ts_info->time_ref,\n+\t\t\t\t      (enum ice_clk_src)ts_info->clk_src);\n+\tif (status)\n+\t\treturn status;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n /**\n  * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands\n  * @hw: pointer to HW struct\n@@ -346,261 +626,59 @@ ice_read_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)\n  * The high offset is looked up. This function only operates on registers\n  * known to be two parts of a 64bit value.\n  */\n-static enum ice_status\n-ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)\n-{\n-\tenum ice_status status;\n-\tu32 low, high;\n-\tu16 high_addr;\n-\n-\t/* Only operate on registers known to be split into two 32bit\n-\t * registers.\n-\t */\n-\tif (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Invalid 64b register addr 0x%08x\\n\",\n-\t\t\t  low_addr);\n-\t\treturn ICE_ERR_PARAM;\n-\t}\n-\n-\tstatus = ice_read_phy_reg_e822(hw, port, low_addr, &low);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read from low register 0x%08x\\n, status %d\",\n-\t\t\t  low_addr, status);\n-\t\treturn status;\n-\t}\n-\n-\tstatus = ice_read_phy_reg_e822(hw, port, high_addr, &high);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read from high register 0x%08x\\n, status %d\",\n-\t\t\t  high_addr, status);\n-\t\treturn status;\n-\t}\n-\n-\t*val = (u64)high << 32 | low;\n-\n-\treturn ICE_SUCCESS;\n-}\n-\n-/**\n- * ice_write_phy_reg_e822_lp - Write a PHY register\n- * @hw: pointer to the HW struct\n- * @port: PHY port to write to\n- * @offset: PHY register offset to write\n- * @val: The value to write to the register\n- * @lock_sbq: true if the sideband queue lock must be acquired\n- *\n- * Write a PHY register for the given port over the device sideband queue.\n- */\n-static enum ice_status\n-ice_write_phy_reg_e822_lp(struct ice_hw *hw, u8 port, u16 offset, u32 val,\n-\t\t\t  bool lock_sbq)\n-{\n-\tstruct ice_sbq_msg_input msg = {0};\n-\tenum ice_status status;\n-\n-\tice_fill_phy_msg_e822(&msg, port, offset);\n-\tmsg.opcode = ice_sbq_msg_wr;\n-\tmsg.data = val;\n-\n-\tstatus = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to send message to phy, status %d\\n\",\n-\t\t\t  status);\n-\t\treturn status;\n-\t}\n-\n-\treturn ICE_SUCCESS;\n-}\n-\n-enum ice_status\n-ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val)\n-{\n-\treturn ice_write_phy_reg_e822_lp(hw, port, offset, val, true);\n-}\n-\n-/**\n- * ice_write_40b_phy_reg_e822 - Write a 40b value to the PHY\n- * @hw: pointer to the HW struct\n- * @port: port to write to\n- * @low_addr: offset of the low register\n- * @val: 40b value to write\n- *\n- * Write the provided 40b value to the two associated registers by splitting\n- * it up into two chunks, the lower 8 bits and the upper 32 bits.\n- */\n-static enum ice_status\n-ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)\n-{\n-\tenum ice_status status;\n-\tu32 low, high;\n-\tu16 high_addr;\n-\n-\t/* Only operate on registers known to be split into a lower 8 bit\n-\t * register and an upper 32 bit register.\n-\t */\n-\tif (!ice_is_40b_phy_reg_e822(low_addr, &high_addr)) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Invalid 40b register addr 0x%08x\\n\",\n-\t\t\t  low_addr);\n-\t\treturn ICE_ERR_PARAM;\n-\t}\n-\n-\tlow = (u32)(val & P_REG_40B_LOW_M);\n-\thigh = (u32)(val >> P_REG_40B_HIGH_S);\n-\n-\tstatus = ice_write_phy_reg_e822(hw, port, low_addr, low);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write to low register 0x%08x\\n, status %d\",\n-\t\t\t  low_addr, status);\n-\t\treturn status;\n-\t}\n-\n-\tstatus = ice_write_phy_reg_e822(hw, port, high_addr, high);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write to high register 0x%08x\\n, status %d\",\n-\t\t\t  high_addr, status);\n-\t\treturn status;\n-\t}\n-\n-\treturn ICE_SUCCESS;\n-}\n-\n-/**\n- * ice_write_64b_phy_reg_e822 - Write a 64bit value to PHY registers\n- * @hw: pointer to the HW struct\n- * @port: PHY port to read from\n- * @low_addr: offset of the lower register to read from\n- * @val: the contents of the 64bit value to write to PHY\n- *\n- * Write the 64bit value to the two associated 32bit PHY registers. The offset\n- * is always specified as the lower register, and the high address is looked\n- * up. This function only operates on registers known to be two parts of\n- * a 64bit value.\n- */\n-static enum ice_status\n-ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)\n-{\n-\tenum ice_status status;\n-\tu32 low, high;\n-\tu16 high_addr;\n-\n-\t/* Only operate on registers known to be split into two 32bit\n-\t * registers.\n-\t */\n-\tif (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Invalid 64b register addr 0x%08x\\n\",\n-\t\t\t  low_addr);\n-\t\treturn ICE_ERR_PARAM;\n-\t}\n-\n-\tlow = ICE_LO_DWORD(val);\n-\thigh = ICE_HI_DWORD(val);\n-\n-\tstatus = ice_write_phy_reg_e822(hw, port, low_addr, low);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write to low register 0x%08x\\n, status %d\",\n-\t\t\t  low_addr, status);\n-\t\treturn status;\n-\t}\n-\n-\tstatus = ice_write_phy_reg_e822(hw, port, high_addr, high);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write to high register 0x%08x\\n, status %d\",\n-\t\t\t  high_addr, status);\n-\t\treturn status;\n-\t}\n-\n-\treturn ICE_SUCCESS;\n-}\n-\n-/**\n- * ice_fill_quad_msg_e822 - Fill message data for quad register access\n- * @msg: the PHY message buffer to fill in\n- * @quad: the quad to access\n- * @offset: the register offset\n- *\n- * Fill a message buffer for accessing a register in a quad shared between\n- * multiple PHYs.\n- */\n-static void\n-ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)\n-{\n-\tu32 addr;\n-\n-\tmsg->dest_dev = rmn_0;\n-\n-\tif ((quad % ICE_NUM_QUAD_TYPE) == 0)\n-\t\taddr = Q_0_BASE + offset;\n-\telse\n-\t\taddr = Q_1_BASE + offset;\n-\n-\tmsg->msg_addr_low = ICE_LO_WORD(addr);\n-\tmsg->msg_addr_high = ICE_HI_WORD(addr);\n-}\n-\n-/**\n- * ice_read_quad_reg_e822_lp - Read a PHY quad register\n- * @hw: pointer to the HW struct\n- * @quad: quad to read from\n- * @offset: quad register offset to read\n- * @val: on return, the contents read from the quad\n- * @lock_sbq: true if the sideband queue lock must be acquired\n- *\n- * Read a quad register over the device sideband queue. Quad registers are\n- * shared between multiple PHYs.\n- */\n-static enum ice_status\n-ice_read_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 *val,\n-\t\t\t  bool lock_sbq)\n+static enum ice_status\n+ice_read_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 *val)\n {\n-\tstruct ice_sbq_msg_input msg = {0};\n \tenum ice_status status;\n+\tu32 low, high;\n+\tu16 high_addr;\n \n-\tif (quad >= ICE_MAX_QUAD)\n+\t/* Only operate on registers known to be split into two 32bit\n+\t * registers.\n+\t */\n+\tif (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Invalid 64b register addr 0x%08x\\n\",\n+\t\t\t  low_addr);\n \t\treturn ICE_ERR_PARAM;\n+\t}\n \n-\tice_fill_quad_msg_e822(&msg, quad, offset);\n-\tmsg.opcode = ice_sbq_msg_rd;\n+\tstatus = ice_read_phy_reg_e822(hw, port, low_addr, &low);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read from low register 0x%08x\\n, status %d\",\n+\t\t\t  low_addr, status);\n+\t\treturn status;\n+\t}\n \n-\tstatus = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);\n+\tstatus = ice_read_phy_reg_e822(hw, port, high_addr, &high);\n \tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to send message to phy, status %d\\n\",\n-\t\t\t  status);\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read from high register 0x%08x\\n, status %d\",\n+\t\t\t  high_addr, status);\n \t\treturn status;\n \t}\n \n-\t*val = msg.data;\n+\t*val = (u64)high << 32 | low;\n \n \treturn ICE_SUCCESS;\n }\n \n-enum ice_status\n-ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)\n-{\n-\treturn ice_read_quad_reg_e822_lp(hw, quad, offset, val, true);\n-}\n-\n /**\n- * ice_write_quad_reg_e822_lp - Write a PHY quad register\n+ * ice_write_phy_reg_e822_lp - Write a PHY register\n  * @hw: pointer to the HW struct\n- * @quad: quad to write to\n- * @offset: quad register offset to write\n+ * @port: PHY port to write to\n+ * @offset: PHY register offset to write\n  * @val: The value to write to the register\n  * @lock_sbq: true if the sideband queue lock must be acquired\n  *\n- * Write a quad register over the device sideband queue. Quad registers are\n- * shared between multiple PHYs.\n+ * Write a PHY register for the given port over the device sideband queue.\n  */\n static enum ice_status\n-ice_write_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 val,\n-\t\t\t   bool lock_sbq)\n+ice_write_phy_reg_e822_lp(struct ice_hw *hw, u8 port, u16 offset, u32 val,\n+\t\t\t  bool lock_sbq)\n {\n \tstruct ice_sbq_msg_input msg = {0};\n \tenum ice_status status;\n \n-\tif (quad >= ICE_MAX_QUAD)\n-\t\treturn ICE_ERR_PARAM;\n-\n-\tice_fill_quad_msg_e822(&msg, quad, offset);\n+\tice_fill_phy_msg_e822(&msg, port, offset);\n \tmsg.opcode = ice_sbq_msg_wr;\n \tmsg.data = val;\n \n@@ -615,84 +693,51 @@ ice_write_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 val,\n }\n \n enum ice_status\n-ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val)\n+ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val)\n {\n-\treturn ice_write_quad_reg_e822_lp(hw, quad, offset, val, true);\n+\treturn ice_write_phy_reg_e822_lp(hw, port, offset, val, true);\n }\n \n /**\n- * ice_read_phy_tstamp_e822 - Read a PHY timestamp out of the quad block\n+ * ice_write_40b_phy_reg_e822 - Write a 40b value to the PHY\n  * @hw: pointer to the HW struct\n- * @quad: the quad to read from\n- * @idx: the timestamp index to read\n- * @tstamp: on return, the 40bit timestamp value\n+ * @port: port to write to\n+ * @low_addr: offset of the low register\n+ * @val: 40b value to write\n  *\n- * Read a 40bit timestamp value out of the two associated registers in the\n- * quad memory block that is shared between the internal PHYs of the E822\n- * family of devices.\n+ * Write the provided 40b value to the two associated registers by splitting\n+ * it up into two chunks, the lower 8 bits and the upper 32 bits.\n  */\n static enum ice_status\n-ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)\n+ice_write_40b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)\n {\n \tenum ice_status status;\n-\tu16 lo_addr, hi_addr;\n-\tu32 lo, hi;\n-\n-\tlo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);\n-\thi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);\n-\n-\tstatus = ice_read_quad_reg_e822(hw, quad, lo_addr, &lo);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read low PTP timestamp register, status %d\\n\",\n-\t\t\t  status);\n-\t\treturn status;\n-\t}\n-\n-\tstatus = ice_read_quad_reg_e822(hw, quad, hi_addr, &hi);\n-\tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read high PTP timestamp register, status %d\\n\",\n-\t\t\t  status);\n-\t\treturn status;\n-\t}\n+\tu32 low, high;\n+\tu16 high_addr;\n \n-\t/* For E822 based internal PHYs, the timestamp is reported with the\n-\t * lower 8 bits in the low register, and the upper 32 bits in the high\n-\t * register.\n+\t/* Only operate on registers known to be split into a lower 8 bit\n+\t * register and an upper 32 bit register.\n \t */\n-\t*tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M);\n-\n-\treturn ICE_SUCCESS;\n-}\n-\n-/**\n- * ice_clear_phy_tstamp_e822 - Clear a timestamp from the quad block\n- * @hw: pointer to the HW struct\n- * @quad: the quad to read from\n- * @idx: the timestamp index to reset\n- *\n- * Clear a timestamp, resetting its valid bit, from the PHY quad block that is\n- * shared between the internal PHYs on the E822 devices.\n- */\n-static enum ice_status\n-ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)\n-{\n-\tenum ice_status status;\n-\tu16 lo_addr, hi_addr;\n+\tif (!ice_is_40b_phy_reg_e822(low_addr, &high_addr)) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Invalid 40b register addr 0x%08x\\n\",\n+\t\t\t  low_addr);\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n \n-\tlo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);\n-\thi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);\n+\tlow = (u32)(val & P_REG_40B_LOW_M);\n+\thigh = (u32)(val >> P_REG_40B_HIGH_S);\n \n-\tstatus = ice_write_quad_reg_e822(hw, quad, lo_addr, 0);\n+\tstatus = ice_write_phy_reg_e822(hw, port, low_addr, low);\n \tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to clear low PTP timestamp register, status %d\\n\",\n-\t\t\t  status);\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write to low register 0x%08x\\n, status %d\",\n+\t\t\t  low_addr, status);\n \t\treturn status;\n \t}\n \n-\tstatus = ice_write_quad_reg_e822(hw, quad, hi_addr, 0);\n+\tstatus = ice_write_phy_reg_e822(hw, port, high_addr, high);\n \tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to clear high PTP timestamp register, status %d\\n\",\n-\t\t\t  status);\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write to high register 0x%08x\\n, status %d\",\n+\t\t\t  high_addr, status);\n \t\treturn status;\n \t}\n \n@@ -700,282 +745,236 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)\n }\n \n /**\n- * ice_read_cgu_reg_e822 - Read a CGU register\n+ * ice_write_64b_phy_reg_e822 - Write a 64bit value to PHY registers\n  * @hw: pointer to the HW struct\n- * @addr: Register address to read\n- * @val: storage for register value read\n+ * @port: PHY port to read from\n+ * @low_addr: offset of the lower register to read from\n+ * @val: the contents of the 64bit value to write to PHY\n  *\n- * Read the contents of a register of the Clock Generation Unit. Only\n- * applicable to E822 devices.\n+ * Write the 64bit value to the two associated 32bit PHY registers. The offset\n+ * is always specified as the lower register, and the high address is looked\n+ * up. This function only operates on registers known to be two parts of\n+ * a 64bit value.\n  */\n static enum ice_status\n-ice_read_cgu_reg_e822(struct ice_hw *hw, u16 addr, u32 *val)\n+ice_write_64b_phy_reg_e822(struct ice_hw *hw, u8 port, u16 low_addr, u64 val)\n {\n-\tstruct ice_sbq_msg_input cgu_msg;\n \tenum ice_status status;\n+\tu32 low, high;\n+\tu16 high_addr;\n \n-\tcgu_msg.opcode = ice_sbq_msg_rd;\n-\tcgu_msg.dest_dev = cgu;\n-\tcgu_msg.msg_addr_low = addr;\n-\tcgu_msg.msg_addr_high = 0x0;\n+\t/* Only operate on registers known to be split into two 32bit\n+\t * registers.\n+\t */\n+\tif (!ice_is_64b_phy_reg_e822(low_addr, &high_addr)) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Invalid 64b register addr 0x%08x\\n\",\n+\t\t\t  low_addr);\n+\t\treturn ICE_ERR_PARAM;\n+\t}\n \n-\tstatus = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);\n+\tlow = ICE_LO_DWORD(val);\n+\thigh = ICE_HI_DWORD(val);\n+\n+\tstatus = ice_write_phy_reg_e822(hw, port, low_addr, low);\n \tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read CGU register 0x%04x, status %d\\n\",\n-\t\t\t  addr, status);\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write to low register 0x%08x\\n, status %d\",\n+\t\t\t  low_addr, status);\n \t\treturn status;\n \t}\n \n-\t*val = cgu_msg.data;\n-\n-\treturn status;\n-}\n-\n-/**\n- * ice_write_cgu_reg_e822 - Write a CGU register\n- * @hw: pointer to the HW struct\n- * @addr: Register address to write\n- * @val: value to write into the register\n- *\n- * Write the specified value to a register of the Clock Generation Unit. Only\n- * applicable to E822 devices.\n- */\n-static enum ice_status\n-ice_write_cgu_reg_e822(struct ice_hw *hw, u16 addr, u32 val)\n-{\n-\tstruct ice_sbq_msg_input cgu_msg;\n-\tenum ice_status status;\n-\n-\tcgu_msg.opcode = ice_sbq_msg_wr;\n-\tcgu_msg.dest_dev = cgu;\n-\tcgu_msg.msg_addr_low = addr;\n-\tcgu_msg.msg_addr_high = 0x0;\n-\tcgu_msg.data = val;\n-\n-\tstatus = ice_sbq_rw_reg_lp(hw, &cgu_msg, true);\n+\tstatus = ice_write_phy_reg_e822(hw, port, high_addr, high);\n \tif (status) {\n-\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write CGU register 0x%04x, status %d\\n\",\n-\t\t\t  addr, status);\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to write to high register 0x%08x\\n, status %d\",\n+\t\t\t  high_addr, status);\n \t\treturn status;\n \t}\n \n-\treturn status;\n-}\n-\n-/**\n- * ice_clk_freq_str - Convert time_ref_freq to string\n- * @clk_freq: Clock frequency\n- *\n- * Convert the specified TIME_REF clock frequency to a string.\n- */\n-static const char *ice_clk_freq_str(u8 clk_freq)\n-{\n-\tswitch ((enum ice_time_ref_freq)clk_freq) {\n-\tcase ICE_TIME_REF_FREQ_25_000:\n-\t\treturn \"25 MHz\";\n-\tcase ICE_TIME_REF_FREQ_122_880:\n-\t\treturn \"122.88 MHz\";\n-\tcase ICE_TIME_REF_FREQ_125_000:\n-\t\treturn \"125 MHz\";\n-\tcase ICE_TIME_REF_FREQ_153_600:\n-\t\treturn \"153.6 MHz\";\n-\tcase ICE_TIME_REF_FREQ_156_250:\n-\t\treturn \"156.25 MHz\";\n-\tcase ICE_TIME_REF_FREQ_245_760:\n-\t\treturn \"245.76 MHz\";\n-\tdefault:\n-\t\treturn \"Unknown\";\n-\t}\n+\treturn ICE_SUCCESS;\n }\n \n /**\n- * ice_clk_src_str - Convert time_ref_src to string\n- * @clk_src: Clock source\n+ * ice_fill_quad_msg_e822 - Fill message data for quad register access\n+ * @msg: the PHY message buffer to fill in\n+ * @quad: the quad to access\n+ * @offset: the register offset\n  *\n- * Convert the specified clock source to its string name.\n- */\n-static const char *ice_clk_src_str(u8 clk_src)\n-{\n-\tswitch ((enum ice_clk_src)clk_src) {\n-\tcase ICE_CLK_SRC_TCX0:\n-\t\treturn \"TCX0\";\n-\tcase ICE_CLK_SRC_TIME_REF:\n-\t\treturn \"TIME_REF\";\n-\tdefault:\n-\t\treturn \"Unknown\";\n-\t}\n+ * Fill a message buffer for accessing a register in a quad shared between\n+ * multiple PHYs.\n+ */\n+static void\n+ice_fill_quad_msg_e822(struct ice_sbq_msg_input *msg, u8 quad, u16 offset)\n+{\n+\tu32 addr;\n+\n+\tmsg->dest_dev = rmn_0;\n+\n+\tif ((quad % ICE_NUM_QUAD_TYPE) == 0)\n+\t\taddr = Q_0_BASE + offset;\n+\telse\n+\t\taddr = Q_1_BASE + offset;\n+\n+\tmsg->msg_addr_low = ICE_LO_WORD(addr);\n+\tmsg->msg_addr_high = ICE_HI_WORD(addr);\n }\n \n /**\n- * ice_cfg_cgu_pll_e822 - Configure the Clock Generation Unit\n+ * ice_read_quad_reg_e822_lp - Read a PHY quad register\n  * @hw: pointer to the HW struct\n- * @clk_freq: Clock frequency to program\n- * @clk_src: Clock source to select (TIME_REF, or TCX0)\n+ * @quad: quad to read from\n+ * @offset: quad register offset to read\n+ * @val: on return, the contents read from the quad\n+ * @lock_sbq: true if the sideband queue lock must be acquired\n  *\n- * Configure the Clock Generation Unit with the desired clock frequency and\n- * time reference, enabling the PLL which drives the PTP hardware clock.\n+ * Read a quad register over the device sideband queue. Quad registers are\n+ * shared between multiple PHYs.\n  */\n-enum ice_status\n-ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,\n-\t\t     enum ice_clk_src clk_src)\n+static enum ice_status\n+ice_read_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 *val,\n+\t\t\t  bool lock_sbq)\n {\n-\tunion tspll_ro_bwm_lf bwm_lf;\n-\tunion nac_cgu_dword19 dw19;\n-\tunion nac_cgu_dword22 dw22;\n-\tunion nac_cgu_dword24 dw24;\n-\tunion nac_cgu_dword9 dw9;\n+\tstruct ice_sbq_msg_input msg = {0};\n \tenum ice_status status;\n \n-\tif (clk_freq >= NUM_ICE_TIME_REF_FREQ) {\n-\t\tice_warn(hw, \"Invalid TIME_REF frequency %u\\n\", clk_freq);\n-\t\treturn ICE_ERR_PARAM;\n-\t}\n-\n-\tif (clk_src >= NUM_ICE_CLK_SRC) {\n-\t\tice_warn(hw, \"Invalid clock source %u\\n\", clk_src);\n-\t\treturn ICE_ERR_PARAM;\n-\t}\n-\n-\tif (clk_src == ICE_CLK_SRC_TCX0 &&\n-\t    clk_freq != ICE_TIME_REF_FREQ_25_000) {\n-\t\tice_warn(hw, \"TCX0 only supports 25 MHz frequency\\n\");\n+\tif (quad >= ICE_MAX_QUAD)\n \t\treturn ICE_ERR_PARAM;\n-\t}\n-\n-\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD9, &dw9.val);\n-\tif (status)\n-\t\treturn status;\n \n-\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);\n-\tif (status)\n-\t\treturn status;\n+\tice_fill_quad_msg_e822(&msg, quad, offset);\n+\tmsg.opcode = ice_sbq_msg_rd;\n \n-\tstatus = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);\n-\tif (status)\n+\tstatus = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to send message to phy, status %d\\n\",\n+\t\t\t  status);\n \t\treturn status;\n-\n-\t/* Log the current clock configuration */\n-\tice_debug(hw, ICE_DBG_PTP, \"Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\\n\",\n-\t\t  dw24.field.ts_pll_enable ? \"enabled\" : \"disabled\",\n-\t\t  ice_clk_src_str(dw24.field.time_ref_sel),\n-\t\t  ice_clk_freq_str(dw9.field.time_ref_freq_sel),\n-\t\t  bwm_lf.field.plllock_true_lock_cri ? \"locked\" : \"unlocked\");\n-\n-\t/* Disable the PLL before changing the clock source or frequency */\n-\tif (dw24.field.ts_pll_enable) {\n-\t\tdw24.field.ts_pll_enable = 0;\n-\n-\t\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);\n-\t\tif (status)\n-\t\t\treturn status;\n \t}\n \n-\t/* Set the frequency */\n-\tdw9.field.time_ref_freq_sel = clk_freq;\n-\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD9, dw9.val);\n-\tif (status)\n-\t\treturn status;\n+\t*val = msg.data;\n \n-\t/* Configure the TS PLL feedback divisor */\n-\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD19, &dw19.val);\n-\tif (status)\n-\t\treturn status;\n+\treturn ICE_SUCCESS;\n+}\n \n-\tdw19.field.tspll_fbdiv_intgr = e822_cgu_params[clk_freq].feedback_div;\n-\tdw19.field.tspll_ndivratio = 1;\n+enum ice_status\n+ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val)\n+{\n+\treturn ice_read_quad_reg_e822_lp(hw, quad, offset, val, true);\n+}\n \n-\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD19, dw19.val);\n-\tif (status)\n-\t\treturn status;\n+/**\n+ * ice_write_quad_reg_e822_lp - Write a PHY quad register\n+ * @hw: pointer to the HW struct\n+ * @quad: quad to write to\n+ * @offset: quad register offset to write\n+ * @val: The value to write to the register\n+ * @lock_sbq: true if the sideband queue lock must be acquired\n+ *\n+ * Write a quad register over the device sideband queue. Quad registers are\n+ * shared between multiple PHYs.\n+ */\n+static enum ice_status\n+ice_write_quad_reg_e822_lp(struct ice_hw *hw, u8 quad, u16 offset, u32 val,\n+\t\t\t   bool lock_sbq)\n+{\n+\tstruct ice_sbq_msg_input msg = {0};\n+\tenum ice_status status;\n \n-\t/* Configure the TS PLL post divisor */\n-\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD22, &dw22.val);\n-\tif (status)\n-\t\treturn status;\n+\tif (quad >= ICE_MAX_QUAD)\n+\t\treturn ICE_ERR_PARAM;\n \n-\tdw22.field.time1588clk_div = e822_cgu_params[clk_freq].post_pll_div;\n-\tdw22.field.time1588clk_sel_div2 = 0;\n+\tice_fill_quad_msg_e822(&msg, quad, offset);\n+\tmsg.opcode = ice_sbq_msg_wr;\n+\tmsg.data = val;\n \n-\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD22, dw22.val);\n-\tif (status)\n+\tstatus = ice_sbq_rw_reg_lp(hw, &msg, lock_sbq);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to send message to phy, status %d\\n\",\n+\t\t\t  status);\n \t\treturn status;\n+\t}\n \n-\t/* Configure the TS PLL pre divisor and clock source */\n-\tstatus = ice_read_cgu_reg_e822(hw, NAC_CGU_DWORD24, &dw24.val);\n-\tif (status)\n-\t\treturn status;\n+\treturn ICE_SUCCESS;\n+}\n \n-\tdw24.field.ref1588_ck_div = e822_cgu_params[clk_freq].refclk_pre_div;\n-\tdw24.field.tspll_fbdiv_frac = e822_cgu_params[clk_freq].frac_n_div;\n-\tdw24.field.time_ref_sel = clk_src;\n+enum ice_status\n+ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val)\n+{\n+\treturn ice_write_quad_reg_e822_lp(hw, quad, offset, val, true);\n+}\n \n-\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);\n-\tif (status)\n-\t\treturn status;\n+/**\n+ * ice_read_phy_tstamp_e822 - Read a PHY timestamp out of the quad block\n+ * @hw: pointer to the HW struct\n+ * @quad: the quad to read from\n+ * @idx: the timestamp index to read\n+ * @tstamp: on return, the 40bit timestamp value\n+ *\n+ * Read a 40bit timestamp value out of the two associated registers in the\n+ * quad memory block that is shared between the internal PHYs of the E822\n+ * family of devices.\n+ */\n+static enum ice_status\n+ice_read_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp)\n+{\n+\tenum ice_status status;\n+\tu16 lo_addr, hi_addr;\n+\tu32 lo, hi;\n \n-\t/* Finally, enable the PLL */\n-\tdw24.field.ts_pll_enable = 1;\n+\tlo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);\n+\thi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);\n \n-\tstatus = ice_write_cgu_reg_e822(hw, NAC_CGU_DWORD24, dw24.val);\n-\tif (status)\n+\tstatus = ice_read_quad_reg_e822(hw, quad, lo_addr, &lo);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read low PTP timestamp register, status %d\\n\",\n+\t\t\t  status);\n \t\treturn status;\n+\t}\n \n-\t/* Wait to verify if the PLL locks */\n-\tice_msec_delay(1, true);\n-\n-\tstatus = ice_read_cgu_reg_e822(hw, TSPLL_RO_BWM_LF, &bwm_lf.val);\n-\tif (status)\n+\tstatus = ice_read_quad_reg_e822(hw, quad, hi_addr, &hi);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to read high PTP timestamp register, status %d\\n\",\n+\t\t\t  status);\n \t\treturn status;\n-\n-\tif (!bwm_lf.field.plllock_true_lock_cri) {\n-\t\tice_warn(hw, \"CGU PLL failed to lock\\n\");\n-\t\treturn ICE_ERR_NOT_READY;\n \t}\n \n-\t/* Log the current clock configuration */\n-\tice_debug(hw, ICE_DBG_PTP, \"New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\\n\",\n-\t\t  dw24.field.ts_pll_enable ? \"enabled\" : \"disabled\",\n-\t\t  ice_clk_src_str(dw24.field.time_ref_sel),\n-\t\t  ice_clk_freq_str(dw9.field.time_ref_freq_sel),\n-\t\t  bwm_lf.field.plllock_true_lock_cri ? \"locked\" : \"unlocked\");\n-\n+\t/* For E822 based internal PHYs, the timestamp is reported with the\n+\t * lower 8 bits in the low register, and the upper 32 bits in the high\n+\t * register.\n+\t */\n+\t*tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M);\n \n \treturn ICE_SUCCESS;\n }\n \n /**\n- * ice_init_cgu_e822 - Initialize CGU with settings from firmware\n- * @hw: pointer to the HW structure\n+ * ice_clear_phy_tstamp_e822 - Clear a timestamp from the quad block\n+ * @hw: pointer to the HW struct\n+ * @quad: the quad to read from\n+ * @idx: the timestamp index to reset\n  *\n- * Initialize the Clock Generation Unit of the E822 device.\n+ * Clear a timestamp, resetting its valid bit, from the PHY quad block that is\n+ * shared between the internal PHYs on the E822 devices.\n  */\n-static enum ice_status ice_init_cgu_e822(struct ice_hw *hw)\n+static enum ice_status\n+ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8 idx)\n {\n-\tstruct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info;\n-\tunion tspll_cntr_bist_settings cntr_bist;\n \tenum ice_status status;\n+\tu16 lo_addr, hi_addr;\n \n-\tstatus = ice_read_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,\n-\t\t\t\t       &cntr_bist.val);\n-\tif (status)\n-\t\treturn status;\n-\n-\t/* Disable sticky lock detection so lock status reported is accurate */\n-\tcntr_bist.field.i_plllock_sel_0 = 0;\n-\tcntr_bist.field.i_plllock_sel_1 = 0;\n+\tlo_addr = (u16)TS_L(Q_REG_TX_MEMORY_BANK_START, idx);\n+\thi_addr = (u16)TS_H(Q_REG_TX_MEMORY_BANK_START, idx);\n \n-\tstatus = ice_write_cgu_reg_e822(hw, TSPLL_CNTR_BIST_SETTINGS,\n-\t\t\t\t\tcntr_bist.val);\n-\tif (status)\n+\tstatus = ice_write_quad_reg_e822(hw, quad, lo_addr, 0);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to clear low PTP timestamp register, status %d\\n\",\n+\t\t\t  status);\n \t\treturn status;\n+\t}\n \n-\t/* Configure the CGU PLL using the parameters from the function\n-\t * capabilities.\n-\t */\n-\tstatus = ice_cfg_cgu_pll_e822(hw, ts_info->time_ref,\n-\t\t\t\t      (enum ice_clk_src)ts_info->clk_src);\n-\tif (status)\n+\tstatus = ice_write_quad_reg_e822(hw, quad, hi_addr, 0);\n+\tif (status) {\n+\t\tice_debug(hw, ICE_DBG_PTP, \"Failed to clear high PTP timestamp register, status %d\\n\",\n+\t\t\t  status);\n \t\treturn status;\n+\t}\n \n \treturn ICE_SUCCESS;\n }\n",
    "prefixes": [
        "12/70"
    ]
}