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GET /api/patches/114962/?format=api
{ "id": 114962, "url": "http://patches.dpdk.org/api/patches/114962/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220815071306.2910599-6-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220815071306.2910599-6-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220815071306.2910599-6-qi.z.zhang@intel.com", "date": "2022-08-15T07:12:01", "name": "[05/70] net/ice/base: fix incorrect division during E822 PTP init", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9f507200b82511ad2f0661c11c2d8f9cb764cf11", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220815071306.2910599-6-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 24307, "url": "http://patches.dpdk.org/api/series/24307/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24307", "date": "2022-08-15T07:11:56", "name": "ice base code update", "version": 1, "mbox": "http://patches.dpdk.org/series/24307/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/114962/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/114962/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D3046A00C3;\n\tMon, 15 Aug 2022 01:03:47 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 38EFE4282D;\n\tMon, 15 Aug 2022 01:03:23 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id 0EAEC400EF;\n Mon, 15 Aug 2022 01:03:20 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Aug 2022 16:03:20 -0700", "from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4])\n by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:03:18 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1660518201; x=1692054201;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=3LarfuzS9mghQcNBkML3FS9NUQeDZieUUzSMokegb/c=;\n b=hGGzeMqNuD/ye0n6EeoKPW3AczmMOSdCmgi51Bu4o3T4Qkwfz1Voxe4j\n PixVZU3BivlVExGmPjpEtW9Alz/uBwxoUCNiDvy5jfEwgKl/+4VD8hTaQ\n pat1bjzTTnv3thKIMjEeqJvI5cpdOMFRRaKKINJ/ooRyyiXxvcRXVxnwe\n b/2FystjbJyUrafXM1YgXDm6zYbxcyq+zWXENkDKeeVDJwjAt9KSLr/Ul\n HnVhuVLGKHmnl7mgbfgu7FTVKByMcQQoC/ot+5QZQ9JoGf19G9WSx0XAD\n TWtBF72MRGBwiCVU+X9oMrC/RO0Jkmd57SJ6bS/5DfPJ0Uu/JSVMjZR5C w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10439\"; a=\"289427540\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"289427540\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"934296549\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>, stable@dpdk.org,\n Jacob Keller <jacob.e.keller@intel.com>", "Subject": "[PATCH 05/70] net/ice/base: fix incorrect division during E822 PTP\n init", "Date": "Mon, 15 Aug 2022 03:12:01 -0400", "Message-Id": "<20220815071306.2910599-6-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20220815071306.2910599-1-qi.z.zhang@intel.com>", "References": "<20220815071306.2910599-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "When initializing the device hardware for PTP, the E822 devices\nrequirea number of values to be calculated and programmed to\nhardware.These values are calculated using unsigned 64-bit\ndivision.\n\nThe DIV_64BIT macro currently translates into a specific Linux\nfunctionthat triggers a *signed* division. This produces incorrect\nresults when operating on a dividend larger than an s64. The\ndivision calculation effectively overflows and results in totally\nunexpected behavior.\n\nIn this case, the UIX value for 10Gb/40Gb link speeds are calculated\nincorrectly. This ultimately cascades into a failure of the Tx\ntimestamps. Specifically, the reported Tx timestamps become wildly\ninaccurate and not representing nominal time.\n\nThe root cause of this bug is the assumption that DIV_64BIT can\ncorrectly handle both signed and unsigned division. In fact the\nentire reason we need this is because the Linux kernel compilation\ntarget does not provide native 64 bit division ops, and requires\nexplicit use of kernel functions which explicitly do either signed\nor unsigned division.\n\nTo correctly solve this, introduce new functions, DIV_U64 and\nDIV_S64 which are specifically intended for signed or unsigned\ndivision. To help catch issues, use static inline functions so\nthat we get strict type checking.\n\nFixes: 97f4f78bbd9f (\"net/ice/base: add functions for device clock control\")\nCc: stable@dpdk.org\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_ptp_hw.c | 56 +++++++++++++++----------------\n drivers/net/ice/base/ice_sched.c | 24 ++++++-------\n drivers/net/ice/base/ice_type.h | 30 +++++++++++++++--\n 3 files changed, 68 insertions(+), 42 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex 632a3f5bae..76119364e4 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -1634,7 +1634,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)\n #define LINE_UI_25G_100G 256 /* 6600 UIs is 256 nanoseconds at 25Gb/100Gb */\n \n \t/* Program the 10Gb/40Gb conversion ratio */\n-\tuix = DIV_64BIT(tu_per_sec * LINE_UI_10G_40G, 390625000);\n+\tuix = DIV_U64(tu_per_sec * LINE_UI_10G_40G, 390625000);\n \n \tstatus = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_10G_40G_L,\n \t\t\t\t\t uix);\n@@ -1645,7 +1645,7 @@ static enum ice_status ice_phy_cfg_uix_e822(struct ice_hw *hw, u8 port)\n \t}\n \n \t/* Program the 25Gb/100Gb conversion ratio */\n-\tuix = DIV_64BIT(tu_per_sec * LINE_UI_25G_100G, 390625000);\n+\tuix = DIV_U64(tu_per_sec * LINE_UI_25G_100G, 390625000);\n \n \tstatus = ice_write_64b_phy_reg_e822(hw, port, P_REG_UIX66_25G_100G_L,\n \t\t\t\t\t uix);\n@@ -1727,8 +1727,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_PAR_TX_TUS */\n \tif (e822_vernier[link_spd].tx_par_clk)\n-\t\tphy_tus = DIV_64BIT(tu_per_sec,\n-\t\t\t\t e822_vernier[link_spd].tx_par_clk);\n+\t\tphy_tus = DIV_U64(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].tx_par_clk);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1739,8 +1739,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_PAR_RX_TUS */\n \tif (e822_vernier[link_spd].rx_par_clk)\n-\t\tphy_tus = DIV_64BIT(tu_per_sec,\n-\t\t\t\t e822_vernier[link_spd].rx_par_clk);\n+\t\tphy_tus = DIV_U64(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].rx_par_clk);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1751,8 +1751,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_PCS_TX_TUS */\n \tif (e822_vernier[link_spd].tx_pcs_clk)\n-\t\tphy_tus = DIV_64BIT(tu_per_sec,\n-\t\t\t\t e822_vernier[link_spd].tx_pcs_clk);\n+\t\tphy_tus = DIV_U64(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].tx_pcs_clk);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1763,8 +1763,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_PCS_RX_TUS */\n \tif (e822_vernier[link_spd].rx_pcs_clk)\n-\t\tphy_tus = DIV_64BIT(tu_per_sec,\n-\t\t\t\t e822_vernier[link_spd].rx_pcs_clk);\n+\t\tphy_tus = DIV_U64(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].rx_pcs_clk);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1775,8 +1775,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_DESK_PAR_TX_TUS */\n \tif (e822_vernier[link_spd].tx_desk_rsgb_par)\n-\t\tphy_tus = DIV_64BIT(tu_per_sec,\n-\t\t\t\t e822_vernier[link_spd].tx_desk_rsgb_par);\n+\t\tphy_tus = DIV_U64(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].tx_desk_rsgb_par);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1787,8 +1787,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_DESK_PAR_RX_TUS */\n \tif (e822_vernier[link_spd].rx_desk_rsgb_par)\n-\t\tphy_tus = DIV_64BIT(tu_per_sec,\n-\t\t\t\t e822_vernier[link_spd].rx_desk_rsgb_par);\n+\t\tphy_tus = DIV_U64(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].rx_desk_rsgb_par);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1799,8 +1799,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_DESK_PCS_TX_TUS */\n \tif (e822_vernier[link_spd].tx_desk_rsgb_pcs)\n-\t\tphy_tus = DIV_64BIT(tu_per_sec,\n-\t\t\t\t e822_vernier[link_spd].tx_desk_rsgb_pcs);\n+\t\tphy_tus = DIV_U64(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].tx_desk_rsgb_pcs);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1811,8 +1811,8 @@ static enum ice_status ice_phy_cfg_parpcs_e822(struct ice_hw *hw, u8 port)\n \n \t/* P_REG_DESK_PCS_RX_TUS */\n \tif (e822_vernier[link_spd].rx_desk_rsgb_pcs)\n-\t\tphy_tus = DIV_64BIT(tu_per_sec,\n-\t\t\t\t e822_vernier[link_spd].rx_desk_rsgb_pcs);\n+\t\tphy_tus = DIV_U64(tu_per_sec,\n+\t\t\t\t e822_vernier[link_spd].rx_desk_rsgb_pcs);\n \telse\n \t\tphy_tus = 0;\n \n@@ -1844,9 +1844,9 @@ ice_calc_fixed_tx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)\n \t * overflows 64 bit integer arithmetic, so break it up into two\n \t * divisions by 1e4 first then by 1e7.\n \t */\n-\tfixed_offset = DIV_64BIT(tu_per_sec, 10000);\n+\tfixed_offset = DIV_U64(tu_per_sec, 10000);\n \tfixed_offset *= e822_vernier[link_spd].tx_fixed_delay;\n-\tfixed_offset = DIV_64BIT(fixed_offset, 10000000);\n+\tfixed_offset = DIV_U64(fixed_offset, 10000000);\n \n \treturn fixed_offset;\n }\n@@ -2074,9 +2074,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,\n \t * divide by 125, and then handle remaining divisor based on the link\n \t * speed pmd_adj_divisor value.\n \t */\n-\tadj = DIV_64BIT(tu_per_sec, 125);\n+\tadj = DIV_U64(tu_per_sec, 125);\n \tadj *= mult;\n-\tadj = DIV_64BIT(adj, pmd_adj_divisor);\n+\tadj = DIV_U64(adj, pmd_adj_divisor);\n \n \t/* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx\n \t * cycle count is necessary.\n@@ -2097,9 +2097,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,\n \t\tif (rx_cycle) {\n \t\t\tmult = (4 - rx_cycle) * 40;\n \n-\t\t\tcycle_adj = DIV_64BIT(tu_per_sec, 125);\n+\t\t\tcycle_adj = DIV_U64(tu_per_sec, 125);\n \t\t\tcycle_adj *= mult;\n-\t\t\tcycle_adj = DIV_64BIT(cycle_adj, pmd_adj_divisor);\n+\t\t\tcycle_adj = DIV_U64(cycle_adj, pmd_adj_divisor);\n \n \t\t\tadj += cycle_adj;\n \t\t}\n@@ -2119,9 +2119,9 @@ ice_phy_calc_pmd_adj_e822(struct ice_hw *hw, u8 port,\n \t\tif (rx_cycle) {\n \t\t\tmult = rx_cycle * 40;\n \n-\t\t\tcycle_adj = DIV_64BIT(tu_per_sec, 125);\n+\t\t\tcycle_adj = DIV_U64(tu_per_sec, 125);\n \t\t\tcycle_adj *= mult;\n-\t\t\tcycle_adj = DIV_64BIT(cycle_adj, pmd_adj_divisor);\n+\t\t\tcycle_adj = DIV_U64(cycle_adj, pmd_adj_divisor);\n \n \t\t\tadj += cycle_adj;\n \t\t}\n@@ -2157,9 +2157,9 @@ ice_calc_fixed_rx_offset_e822(struct ice_hw *hw, enum ice_ptp_link_spd link_spd)\n \t * overflows 64 bit integer arithmetic, so break it up into two\n \t * divisions by 1e4 first then by 1e7.\n \t */\n-\tfixed_offset = DIV_64BIT(tu_per_sec, 10000);\n+\tfixed_offset = DIV_U64(tu_per_sec, 10000);\n \tfixed_offset *= e822_vernier[link_spd].rx_fixed_delay;\n-\tfixed_offset = DIV_64BIT(fixed_offset, 10000000);\n+\tfixed_offset = DIV_U64(fixed_offset, 10000000);\n \n \treturn fixed_offset;\n }\ndiff --git a/drivers/net/ice/base/ice_sched.c b/drivers/net/ice/base/ice_sched.c\nindex 1b060d3567..71b5677f43 100644\n--- a/drivers/net/ice/base/ice_sched.c\n+++ b/drivers/net/ice/base/ice_sched.c\n@@ -3916,8 +3916,8 @@ static u16 ice_sched_calc_wakeup(struct ice_hw *hw, s32 bw)\n \tu16 wakeup = 0;\n \n \t/* Get the wakeup integer value */\n-\tbytes_per_sec = DIV_64BIT(((s64)bw * 1000), BITS_PER_BYTE);\n-\twakeup_int = DIV_64BIT(hw->psm_clk_freq, bytes_per_sec);\n+\tbytes_per_sec = DIV_S64((s64)bw * 1000, BITS_PER_BYTE);\n+\twakeup_int = DIV_S64(hw->psm_clk_freq, bytes_per_sec);\n \tif (wakeup_int > 63) {\n \t\twakeup = (u16)((1 << 15) | wakeup_int);\n \t} else {\n@@ -3925,18 +3925,18 @@ static u16 ice_sched_calc_wakeup(struct ice_hw *hw, s32 bw)\n \t\t * Convert Integer value to a constant multiplier\n \t\t */\n \t\twakeup_b = (s64)ICE_RL_PROF_MULTIPLIER * wakeup_int;\n-\t\twakeup_a = DIV_64BIT((s64)ICE_RL_PROF_MULTIPLIER *\n-\t\t\t\t hw->psm_clk_freq, bytes_per_sec);\n+\t\twakeup_a = DIV_S64((s64)ICE_RL_PROF_MULTIPLIER *\n+\t\t\t\t hw->psm_clk_freq, bytes_per_sec);\n \n \t\t/* Get Fraction value */\n \t\twakeup_f = wakeup_a - wakeup_b;\n \n \t\t/* Round up the Fractional value via Ceil(Fractional value) */\n-\t\tif (wakeup_f > DIV_64BIT(ICE_RL_PROF_MULTIPLIER, 2))\n+\t\tif (wakeup_f > DIV_S64(ICE_RL_PROF_MULTIPLIER, 2))\n \t\t\twakeup_f += 1;\n \n-\t\twakeup_f_int = (s32)DIV_64BIT(wakeup_f * ICE_RL_PROF_FRACTION,\n-\t\t\t\t\t ICE_RL_PROF_MULTIPLIER);\n+\t\twakeup_f_int = (s32)DIV_S64(wakeup_f * ICE_RL_PROF_FRACTION,\n+\t\t\t\t\t ICE_RL_PROF_MULTIPLIER);\n \t\twakeup |= (u16)(wakeup_int << 9);\n \t\twakeup |= (u16)(0x1ff & wakeup_f_int);\n \t}\n@@ -3968,20 +3968,20 @@ ice_sched_bw_to_rl_profile(struct ice_hw *hw, u32 bw,\n \t\treturn status;\n \n \t/* Bytes per second from Kbps */\n-\tbytes_per_sec = DIV_64BIT(((s64)bw * 1000), BITS_PER_BYTE);\n+\tbytes_per_sec = DIV_S64((s64)bw * 1000, BITS_PER_BYTE);\n \n \t/* encode is 6 bits but really useful are 5 bits */\n \tfor (i = 0; i < 64; i++) {\n \t\tu64 pow_result = BIT_ULL(i);\n \n-\t\tts_rate = DIV_64BIT((s64)hw->psm_clk_freq,\n-\t\t\t\t pow_result * ICE_RL_PROF_TS_MULTIPLIER);\n+\t\tts_rate = DIV_S64((s64)hw->psm_clk_freq,\n+\t\t\t\t pow_result * ICE_RL_PROF_TS_MULTIPLIER);\n \t\tif (ts_rate <= 0)\n \t\t\tcontinue;\n \n \t\t/* Multiplier value */\n-\t\tmv_tmp = DIV_64BIT(bytes_per_sec * ICE_RL_PROF_MULTIPLIER,\n-\t\t\t\t ts_rate);\n+\t\tmv_tmp = DIV_S64(bytes_per_sec * ICE_RL_PROF_MULTIPLIER,\n+\t\t\t\t ts_rate);\n \n \t\t/* Round to the nearest ICE_RL_PROF_MULTIPLIER */\n \t\tmv = round_up_64bit(mv_tmp, ICE_RL_PROF_MULTIPLIER);\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex d4d0cab089..3da3de38af 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -87,11 +87,37 @@ static inline bool ice_is_tc_ena(ice_bitmap_t bitmap, u8 tc)\n \treturn ice_is_bit_set(&bitmap, tc);\n }\n \n-#define DIV_64BIT(n, d) ((n) / (d))\n+/**\n+ * DIV_S64 - Divide signed 64-bit value with signed 64-bit divisor\n+ * @dividend: value to divide\n+ * @divisor: value to divide by\n+ *\n+ * Use DIV_S64 for any 64-bit divide which operates on signed 64-bit dividends.\n+ * Do not use this for unsigned 64-bit dividends as it will not produce\n+ * correct results if the dividend is larger than S64_MAX.\n+ */\n+static inline s64 DIV_S64(s64 dividend, s64 divisor)\n+{\n+\treturn dividend / divisor;\n+}\n+\n+/**\n+ * DIV_U64 - Divide unsigned 64-bit value by unsigned 64-bit divisor\n+ * @dividend: value to divide\n+ * @divisor: value to divide by\n+ *\n+ * Use DIV_U64 for any 64-bit divide which operates on unsigned 64-bit\n+ * dividends. Do not use this for signed 64-bit dividends as it will not\n+ * handle negative values correctly.\n+ */\n+static inline u64 DIV_U64(u64 dividend, u64 divisor)\n+{\n+\treturn dividend / divisor;\n+}\n \n static inline u64 round_up_64bit(u64 a, u32 b)\n {\n-\treturn DIV_64BIT(((a) + (b) / 2), (b));\n+\treturn DIV_U64(((a) + (b) / 2), (b));\n }\n \n static inline u32 ice_round_to_num(u32 N, u32 R)\n", "prefixes": [ "05/70" ] }