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GET /api/patches/114959/?format=api
{ "id": 114959, "url": "http://patches.dpdk.org/api/patches/114959/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220815071306.2910599-3-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220815071306.2910599-3-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220815071306.2910599-3-qi.z.zhang@intel.com", "date": "2022-08-15T07:11:58", "name": "[02/70] net/ice/base: get NVM CSS Header length from the CSS Header", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6b3ec6aa71d1244306e5d62a4d2af244b5e8c849", "submitter": { "id": 504, "url": "http://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220815071306.2910599-3-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 24307, "url": "http://patches.dpdk.org/api/series/24307/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24307", "date": "2022-08-15T07:11:56", "name": "ice base code update", "version": 1, "mbox": "http://patches.dpdk.org/series/24307/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/114959/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/114959/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id EB000A00C3;\n\tMon, 15 Aug 2022 01:03:30 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 7051D427F3;\n\tMon, 15 Aug 2022 01:03:18 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id B5B6A40A79\n for <dev@dpdk.org>; Mon, 15 Aug 2022 01:03:16 +0200 (CEST)", "from fmsmga005.fm.intel.com ([10.253.24.32])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 14 Aug 2022 16:03:15 -0700", "from dpdk-qzhan15-test02.sh.intel.com ([10.67.115.4])\n by fmsmga005.fm.intel.com with ESMTP; 14 Aug 2022 16:03:14 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1660518196; x=1692054196;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=AJqw2dRH11a7S77g80A7JC/txMovlXgtA8Oz4wKfWBE=;\n b=A6goyq9mALuTZjpfIbUlJ4pwgs7BwyjAdqZE77CTbs52W6nqvAILz2YG\n iloD/A0G6ER6H0YHQD9UJwKOIzOOpT5doJw47Zd1RUQmlRjdEmRgIKj3F\n eSnyqLpswXlTQq3tEOXKFb067YD0m3sHbIeRSckQ//A8HY0uwP6eJlWa5\n ao1QUEm2W2QMIMPMnvT/I5Z8lmCoVRs4FUk/zuWQgv5yyzHYcPSm9H8JO\n 5A1FudK2D96JF78rakadwatPrPgdC6XMX1d9SrMnRa2ayoNLAAqXIntiI\n cGjrrfPc0S2FHrtOu+v7e6dTLFY0q19fCghHXMtGF8oe9GZTsEPR/itnA A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10439\"; a=\"289427528\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"289427528\"", "E=Sophos;i=\"5.93,237,1654585200\"; d=\"scan'208\";a=\"934296524\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Paul Greenwalt <paul.greenwalt@intel.com>", "Subject": "[PATCH 02/70] net/ice/base: get NVM CSS Header length from the CSS\n Header", "Date": "Mon, 15 Aug 2022 03:11:58 -0400", "Message-Id": "<20220815071306.2910599-3-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20220815071306.2910599-1-qi.z.zhang@intel.com>", "References": "<20220815071306.2910599-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The CSS Header length is defined as ICE_CSS_HEADER_LENGTH. To\nsupport changes in CSS Header length, calculate the CSS Header\nlength from the NVM CSS Header length field plus the Authentication\nHeader length.\n\nSigned-off-by: Paul Greenwalt <paul.greenwalt@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_nvm.c | 61 +++++++++++++++++++++++++++++----\n drivers/net/ice/base/ice_type.h | 12 +++----\n 2 files changed, 59 insertions(+), 14 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c\nindex 7860006206..ad2496e873 100644\n--- a/drivers/net/ice/base/ice_nvm.c\n+++ b/drivers/net/ice/base/ice_nvm.c\n@@ -350,6 +350,42 @@ ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u1\n \treturn status;\n }\n \n+/**\n+ * ice_get_nvm_css_hdr_len - Read the CSS header length from the NVM CSS header\n+ * @hw: pointer to the HW struct\n+ * @bank: whether to read from the active or inactive flash bank\n+ * @hdr_len: storage for header length in words\n+ *\n+ * Read the CSS header length from the NVM CSS header and add the Authentication\n+ * header size, and then convert to words.\n+ */\n+static enum ice_status\n+ice_get_nvm_css_hdr_len(struct ice_hw *hw, enum ice_bank_select bank,\n+\t\t\tu32 *hdr_len)\n+{\n+\tu16 hdr_len_l, hdr_len_h;\n+\tenum ice_status status;\n+\tu32 hdr_len_dword;\n+\n+\tstatus = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_L,\n+\t\t\t\t &hdr_len_l);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ice_read_nvm_module(hw, bank, ICE_NVM_CSS_HDR_LEN_H,\n+\t\t\t\t &hdr_len_h);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* CSS header length is in DWORD, so convert to words and add\n+\t * authentication header size\n+\t */\n+\thdr_len_dword = hdr_len_h << 16 | hdr_len_l;\n+\t*hdr_len = (hdr_len_dword * 2) + ICE_NVM_AUTH_HEADER_LEN;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n /**\n * ice_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank\n * @hw: pointer to the HW structure\n@@ -363,7 +399,16 @@ ice_read_nvm_module(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u1\n static enum ice_status\n ice_read_nvm_sr_copy(struct ice_hw *hw, enum ice_bank_select bank, u32 offset, u16 *data)\n {\n-\treturn ice_read_nvm_module(hw, bank, ICE_NVM_SR_COPY_WORD_OFFSET + offset, data);\n+\tenum ice_status status;\n+\tu32 hdr_len;\n+\n+\tstatus = ice_get_nvm_css_hdr_len(hw, bank, &hdr_len);\n+\tif (status)\n+\t\treturn status;\n+\n+\thdr_len = ROUND_UP(hdr_len, 32);\n+\n+\treturn ice_read_nvm_module(hw, bank, hdr_len + offset, data);\n }\n \n /**\n@@ -633,22 +678,26 @@ enum ice_status ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info\n */\n static enum ice_status ice_get_orom_srev(struct ice_hw *hw, enum ice_bank_select bank, u32 *srev)\n {\n+\tu32 orom_size_word = hw->flash.banks.orom_size / 2;\n \tenum ice_status status;\n \tu16 srev_l, srev_h;\n \tu32 css_start;\n+\tu32 hdr_len;\n \n-\tif (hw->flash.banks.orom_size < ICE_NVM_OROM_TRAILER_LENGTH) {\n+\tstatus = ice_get_nvm_css_hdr_len(hw, bank, &hdr_len);\n+\tif (status)\n+\t\treturn status;\n+\n+\tif (orom_size_word < hdr_len) {\n \t\tice_debug(hw, ICE_DBG_NVM, \"Unexpected Option ROM Size of %u\\n\",\n \t\t\t hw->flash.banks.orom_size);\n \t\treturn ICE_ERR_CFG;\n \t}\n \n \t/* calculate how far into the Option ROM the CSS header starts. Note\n-\t * that ice_read_orom_module takes a word offset so we need to\n-\t * divide by 2 here.\n+\t * that ice_read_orom_module takes a word offset\n \t */\n-\tcss_start = (hw->flash.banks.orom_size - ICE_NVM_OROM_TRAILER_LENGTH) / 2;\n-\n+\tcss_start = orom_size_word - hdr_len;\n \tstatus = ice_read_orom_module(hw, bank, css_start + ICE_NVM_CSS_SREV_L, &srev_l);\n \tif (status)\n \t\treturn status;\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex d81984633a..d4d0cab089 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -1419,17 +1419,13 @@ struct ice_aq_get_set_rss_lut_params {\n #define ICE_SR_POR_REGISTERS_AUTOLOAD_PTR\t0x118\n \n /* CSS Header words */\n+#define ICE_NVM_CSS_HDR_LEN_L\t\t\t0x02\n+#define ICE_NVM_CSS_HDR_LEN_H\t\t\t0x03\n #define ICE_NVM_CSS_SREV_L\t\t\t0x14\n #define ICE_NVM_CSS_SREV_H\t\t\t0x15\n \n-/* Length of CSS header section in words */\n-#define ICE_CSS_HEADER_LENGTH\t\t\t330\n-\n-/* Offset of Shadow RAM copy in the NVM bank area. */\n-#define ICE_NVM_SR_COPY_WORD_OFFSET\t\tROUND_UP(ICE_CSS_HEADER_LENGTH, 32)\n-\n-/* Size in bytes of Option ROM trailer */\n-#define ICE_NVM_OROM_TRAILER_LENGTH\t\t(2 * ICE_CSS_HEADER_LENGTH)\n+/* Length of Authentication header section in words */\n+#define ICE_NVM_AUTH_HEADER_LEN\t\t\t0x08\n \n /* The Link Topology Netlist section is stored as a series of words. It is\n * stored in the NVM as a TLV, with the first two words containing the type\n", "prefixes": [ "02/70" ] }