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GET /api/patches/114887/?format=api
{ "id": 114887, "url": "http://patches.dpdk.org/api/patches/114887/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220812095445.1253138-5-cristian.dumitrescu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220812095445.1253138-5-cristian.dumitrescu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220812095445.1253138-5-cristian.dumitrescu@intel.com", "date": "2022-08-12T09:54:45", "name": "[4/4] pipeline: add instruction support for moving large structure fields", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "9a07cb858adc7227a5cf0268a2740160471a2dc1", "submitter": { "id": 19, "url": "http://patches.dpdk.org/api/people/19/?format=api", "name": "Cristian Dumitrescu", "email": "cristian.dumitrescu@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220812095445.1253138-5-cristian.dumitrescu@intel.com/mbox/", "series": [ { "id": 24289, "url": "http://patches.dpdk.org/api/series/24289/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24289", "date": "2022-08-12T09:54:41", "name": "pipeline: support large structure fields", "version": 1, "mbox": "http://patches.dpdk.org/series/24289/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/114887/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/114887/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id F2ACAA0543;\n\tFri, 12 Aug 2022 11:55:10 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E126842C0D;\n\tFri, 12 Aug 2022 11:54:53 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id 25AAE42C14\n for <dev@dpdk.org>; Fri, 12 Aug 2022 11:54:52 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Aug 2022 02:54:51 -0700", "from silpixa00400573.ir.intel.com (HELO\n silpixa00400573.ger.corp.intel.com.) ([10.237.223.157])\n by orsmga008.jf.intel.com with ESMTP; 12 Aug 2022 02:54:50 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1660298092; x=1691834092;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=11zWIaxIq2VxwFcumCoqO5OeyLpXxUZxPHyyG9Uya2Q=;\n b=fTjCIrtj/gLLCvZp8d1Tz02TXhZgs9HjoXkUAcdPI6ytoThP4Z6YjStz\n IlflzGoD6gu67h3ZhnrYUHFA3p7koz7+wOvYsQHa0uU01VjyW83vxMtAi\n JI3iQZfFOr+4GhbhAKtM0uUM0Ws1/nW7WvRzJwvsX8hAxPPog1/0d2UiX\n W3dIHwizJ43K6vcvaGJgOVZZ3Coh3sBmb71BhPp3sXOtkjp/zo2rskO5D\n qzkmgkZ1mc8SWgeBbgrWMoWUdDXzCdvIpkp8HmkVoN1QuN4Q5S/Td11hs\n LLX8qiaGgAqqd3rMZjzO1cy6lg0gjAYcxWg1r+NSXPx3pXe2MNkKPIfHz g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10436\"; a=\"289135021\"", "E=Sophos;i=\"5.93,231,1654585200\"; d=\"scan'208\";a=\"289135021\"", "E=Sophos;i=\"5.93,231,1654585200\"; d=\"scan'208\";a=\"634589102\"" ], "X-ExtLoop1": "1", "From": "Cristian Dumitrescu <cristian.dumitrescu@intel.com>", "To": "dev@dpdk.org", "Cc": "Harshad Suresh Narayane <harshad.suresh.narayane@intel.com>", "Subject": "[PATCH 4/4] pipeline: add instruction support for moving large\n structure fields", "Date": "Fri, 12 Aug 2022 09:54:45 +0000", "Message-Id": "<20220812095445.1253138-5-cristian.dumitrescu@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20220812095445.1253138-1-cristian.dumitrescu@intel.com>", "References": "<20220812095445.1253138-1-cristian.dumitrescu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support to the move instruction for operands bigger than 64 bits.\n\nSigned-off-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>\nSigned-off-by: Harshad Suresh Narayane <harshad.suresh.narayane@intel.com>\n---\n lib/pipeline/rte_swx_pipeline.c | 71 +++++++++++++++++----\n lib/pipeline/rte_swx_pipeline_internal.h | 78 ++++++++++++++++++++++--\n 2 files changed, 131 insertions(+), 18 deletions(-)", "diff": "diff --git a/lib/pipeline/rte_swx_pipeline.c b/lib/pipeline/rte_swx_pipeline.c\nindex 48b9df0fef..2cac4caa95 100644\n--- a/lib/pipeline/rte_swx_pipeline.c\n+++ b/lib/pipeline/rte_swx_pipeline.c\n@@ -2969,20 +2969,28 @@ instr_mov_translate(struct rte_swx_pipeline *p,\n \n \tfdst = struct_field_parse(p, NULL, dst, &dst_struct_id);\n \tCHECK(fdst, EINVAL);\n-\tCHECK(!fdst->var_size && (fdst->n_bits <= 64), EINVAL);\n+\tCHECK(!fdst->var_size, EINVAL);\n \n-\t/* MOV, MOV_MH, MOV_HM or MOV_HH. */\n+\t/* MOV, MOV_MH, MOV_HM, MOV_HH, MOV16, MOVDMA. */\n \tfsrc = struct_field_parse(p, action, src, &src_struct_id);\n \tif (fsrc) {\n-\t\tCHECK(!fsrc->var_size && (fsrc->n_bits <= 64), EINVAL);\n+\t\tCHECK(!fsrc->var_size, EINVAL);\n+\n+\t\tif (fdst->n_bits <= 64 && fsrc->n_bits <= 64) {\n+\t\t\tinstr->type = INSTR_MOV;\n+\t\t\tif (dst[0] != 'h' && src[0] == 'h')\n+\t\t\t\tinstr->type = INSTR_MOV_MH;\n+\t\t\tif (dst[0] == 'h' && src[0] != 'h')\n+\t\t\t\tinstr->type = INSTR_MOV_HM;\n+\t\t\tif (dst[0] == 'h' && src[0] == 'h')\n+\t\t\t\tinstr->type = INSTR_MOV_HH;\n+\t\t} else {\n+\t\t\tCHECK(fdst->n_bits == fsrc->n_bits, EINVAL);\n \n-\t\tinstr->type = INSTR_MOV;\n-\t\tif (dst[0] != 'h' && src[0] == 'h')\n-\t\t\tinstr->type = INSTR_MOV_MH;\n-\t\tif (dst[0] == 'h' && src[0] != 'h')\n-\t\t\tinstr->type = INSTR_MOV_HM;\n-\t\tif (dst[0] == 'h' && src[0] == 'h')\n-\t\t\tinstr->type = INSTR_MOV_HH;\n+\t\t\tinstr->type = INSTR_MOV_DMA;\n+\t\t\tif (fdst->n_bits == 128)\n+\t\t\t\tinstr->type = INSTR_MOV_128;\n+\t\t}\n \n \t\tinstr->mov.dst.struct_id = (uint8_t)dst_struct_id;\n \t\tinstr->mov.dst.n_bits = fdst->n_bits;\n@@ -2994,6 +3002,7 @@ instr_mov_translate(struct rte_swx_pipeline *p,\n \t}\n \n \t/* MOV_I. */\n+\tCHECK(fdst->n_bits <= 64, EINVAL);\n \tsrc_val = strtoull(src, &src, 0);\n \tCHECK(!src[0], EINVAL);\n \n@@ -3056,6 +3065,30 @@ instr_mov_hh_exec(struct rte_swx_pipeline *p)\n \tthread_ip_inc(p);\n }\n \n+static inline void\n+instr_mov_dma_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\t__instr_mov_dma_exec(p, t, ip);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n+static inline void\n+instr_mov_128_exec(struct rte_swx_pipeline *p)\n+{\n+\tstruct thread *t = &p->threads[p->thread_id];\n+\tstruct instruction *ip = t->ip;\n+\n+\t__instr_mov_128_exec(p, t, ip);\n+\n+\t/* Thread. */\n+\tthread_ip_inc(p);\n+}\n+\n static inline void\n instr_mov_i_exec(struct rte_swx_pipeline *p)\n {\n@@ -6781,12 +6814,14 @@ instr_pattern_validate_mov_all_search(struct rte_swx_pipeline *p,\n \tif (!a || !a->st)\n \t\treturn 0;\n \n-\t/* First instruction: HDR_VALIDATE. Second instruction: MOV_HM. */\n+\t/* First instruction: HDR_VALIDATE. Second instruction: MOV_HM, MOV_DMA or MOV_128. */\n \tif (data[0].invalid ||\n \t (instr[0].type != INSTR_HDR_VALIDATE) ||\n \t (n_instr < 2) ||\n \t data[1].invalid ||\n-\t (instr[1].type != INSTR_MOV_HM) ||\n+\t (instr[1].type != INSTR_MOV_HM &&\n+\t instr[1].type != INSTR_MOV_DMA &&\n+\t instr[1].type != INSTR_MOV_128) ||\n \t instr[1].mov.src.struct_id)\n \t\treturn 0;\n \n@@ -6807,7 +6842,9 @@ instr_pattern_validate_mov_all_search(struct rte_swx_pipeline *p,\n \tfor (i = 0; i < h->st->n_fields; i++)\n \t\tif (data[1 + i].invalid ||\n \t\t data[1 + i].n_users ||\n-\t\t (instr[1 + i].type != INSTR_MOV_HM) ||\n+\t\t (instr[1 + i].type != INSTR_MOV_HM &&\n+\t\t instr[1 + i].type != INSTR_MOV_DMA &&\n+\t\t instr[1 + i].type != INSTR_MOV_128) ||\n \t\t (instr[1 + i].mov.dst.struct_id != h->struct_id) ||\n \t\t (instr[1 + i].mov.dst.offset != h->st->fields[i].offset / 8) ||\n \t\t (instr[1 + i].mov.dst.n_bits != h->st->fields[i].n_bits) ||\n@@ -7147,6 +7184,8 @@ static instr_exec_t instruction_table[] = {\n \t[INSTR_MOV_MH] = instr_mov_mh_exec,\n \t[INSTR_MOV_HM] = instr_mov_hm_exec,\n \t[INSTR_MOV_HH] = instr_mov_hh_exec,\n+\t[INSTR_MOV_DMA] = instr_mov_dma_exec,\n+\t[INSTR_MOV_128] = instr_mov_128_exec,\n \t[INSTR_MOV_I] = instr_mov_i_exec,\n \n \t[INSTR_DMA_HT] = instr_dma_ht_exec,\n@@ -10950,6 +10989,8 @@ instr_type_to_name(struct instruction *instr)\n \tcase INSTR_MOV_MH: return \"INSTR_MOV_MH\";\n \tcase INSTR_MOV_HM: return \"INSTR_MOV_HM\";\n \tcase INSTR_MOV_HH: return \"INSTR_MOV_HH\";\n+\tcase INSTR_MOV_DMA: return \"INSTR_MOV_DMA\";\n+\tcase INSTR_MOV_128: return \"INSTR_MOV_128\";\n \tcase INSTR_MOV_I: return \"INSTR_MOV_I\";\n \n \tcase INSTR_DMA_HT: return \"INSTR_DMA_HT\";\n@@ -11938,6 +11979,8 @@ static instruction_export_t export_table[] = {\n \t[INSTR_MOV_MH] = instr_mov_export,\n \t[INSTR_MOV_HM] = instr_mov_export,\n \t[INSTR_MOV_HH] = instr_mov_export,\n+\t[INSTR_MOV_DMA] = instr_mov_export,\n+\t[INSTR_MOV_128] = instr_mov_export,\n \t[INSTR_MOV_I] = instr_mov_export,\n \n \t[INSTR_DMA_HT] = instr_dma_ht_export,\n@@ -12162,6 +12205,8 @@ instr_type_to_func(struct instruction *instr)\n \tcase INSTR_MOV_MH: return \"__instr_mov_mh_exec\";\n \tcase INSTR_MOV_HM: return \"__instr_mov_hm_exec\";\n \tcase INSTR_MOV_HH: return \"__instr_mov_hh_exec\";\n+\tcase INSTR_MOV_DMA: return \"__instr_mov_dma_exec\";\n+\tcase INSTR_MOV_128: return \"__instr_mov_128_exec\";\n \tcase INSTR_MOV_I: return \"__instr_mov_i_exec\";\n \n \tcase INSTR_DMA_HT: return \"__instr_dma_ht_exec\";\ndiff --git a/lib/pipeline/rte_swx_pipeline_internal.h b/lib/pipeline/rte_swx_pipeline_internal.h\nindex 588cad62b5..6d65b635c6 100644\n--- a/lib/pipeline/rte_swx_pipeline_internal.h\n+++ b/lib/pipeline/rte_swx_pipeline_internal.h\n@@ -307,11 +307,13 @@ enum instruction_type {\n \t * dst = src\n \t * dst = HMEF, src = HMEFTI\n \t */\n-\tINSTR_MOV, /* dst = MEF, src = MEFT */\n-\tINSTR_MOV_MH, /* dst = MEF, src = H */\n-\tINSTR_MOV_HM, /* dst = H, src = MEFT */\n-\tINSTR_MOV_HH, /* dst = H, src = H */\n-\tINSTR_MOV_I, /* dst = HMEF, src = I */\n+\tINSTR_MOV, /* dst = MEF, src = MEFT; size(dst) <= 64 bits, size(src) <= 64 bits. */\n+\tINSTR_MOV_MH, /* dst = MEF, src = H; size(dst) <= 64 bits, size(src) <= 64 bits. */\n+\tINSTR_MOV_HM, /* dst = H, src = MEFT; size(dst) <= 64 bits, size(src) <= 64 bits. */\n+\tINSTR_MOV_HH, /* dst = H, src = H; size(dst) <= 64 bits, size(src) <= 64 bits. */\n+\tINSTR_MOV_DMA, /* dst = HMEF, src = HMEF; size(dst) = size(src) > 64 bits, NBO format. */\n+\tINSTR_MOV_128, /* dst = HMEF, src = HMEF; size(dst) = size(src) = 128 bits, NBO format. */\n+\tINSTR_MOV_I, /* dst = HMEF, src = I; size(dst) <= 64 bits. */\n \n \t/* dma h.header t.field\n \t * memcpy(h.header, t.field, sizeof(h.header))\n@@ -2485,6 +2487,72 @@ __instr_mov_hh_exec(struct rte_swx_pipeline *p __rte_unused,\n \tMOV_HH(t, ip);\n }\n \n+static inline void\n+__instr_mov_dma_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t struct thread *t,\n+\t\t const struct instruction *ip)\n+{\n+\tuint8_t *dst_struct = t->structs[ip->mov.dst.struct_id];\n+\tuint64_t *dst64_ptr = (uint64_t *)&dst_struct[ip->mov.dst.offset];\n+\tuint32_t *dst32_ptr;\n+\tuint16_t *dst16_ptr;\n+\tuint8_t *dst8_ptr;\n+\n+\tuint8_t *src_struct = t->structs[ip->mov.src.struct_id];\n+\tuint64_t *src64_ptr = (uint64_t *)&src_struct[ip->mov.src.offset];\n+\tuint32_t *src32_ptr;\n+\tuint16_t *src16_ptr;\n+\tuint8_t *src8_ptr;\n+\n+\tuint32_t n = ip->mov.dst.n_bits >> 3, i;\n+\n+\tTRACE(\"[Thread %2u] mov (dma) %u bytes\\n\", p->thread_id, n);\n+\n+\t/* 8-byte transfers. */\n+\tfor (i = 0; i < n >> 3; i++)\n+\t\t*dst64_ptr++ = *src64_ptr++;\n+\n+\t/* 4-byte transfers. */\n+\tn &= 7;\n+\tdst32_ptr = (uint32_t *)dst64_ptr;\n+\tsrc32_ptr = (uint32_t *)src64_ptr;\n+\n+\tfor (i = 0; i < n >> 2; i++)\n+\t\t*dst32_ptr++ = *src32_ptr++;\n+\n+\t/* 2-byte transfers. */\n+\tn &= 3;\n+\tdst16_ptr = (uint16_t *)dst32_ptr;\n+\tsrc16_ptr = (uint16_t *)src32_ptr;\n+\n+\tfor (i = 0; i < n >> 1; i++)\n+\t\t*dst16_ptr++ = *src16_ptr++;\n+\n+\t/* 1-byte transfer. */\n+\tn &= 1;\n+\tdst8_ptr = (uint8_t *)dst16_ptr;\n+\tsrc8_ptr = (uint8_t *)src16_ptr;\n+\tif (n)\n+\t\t*dst8_ptr = *src8_ptr;\n+}\n+\n+static inline void\n+__instr_mov_128_exec(struct rte_swx_pipeline *p __rte_unused,\n+\t\t struct thread *t,\n+\t\t const struct instruction *ip)\n+{\n+\tuint8_t *dst_struct = t->structs[ip->mov.dst.struct_id];\n+\tuint64_t *dst64_ptr = (uint64_t *)&dst_struct[ip->mov.dst.offset];\n+\n+\tuint8_t *src_struct = t->structs[ip->mov.src.struct_id];\n+\tuint64_t *src64_ptr = (uint64_t *)&src_struct[ip->mov.src.offset];\n+\n+\tTRACE(\"[Thread %2u] mov (128)\\n\", p->thread_id);\n+\n+\tdst64_ptr[0] = src64_ptr[0];\n+\tdst64_ptr[1] = src64_ptr[1];\n+}\n+\n static inline void\n __instr_mov_i_exec(struct rte_swx_pipeline *p __rte_unused,\n \t\t struct thread *t,\n", "prefixes": [ "4/4" ] }