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GET /api/patches/114788/?format=api
{ "id": 114788, "url": "http://patches.dpdk.org/api/patches/114788/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220809184908.24030-10-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220809184908.24030-10-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220809184908.24030-10-ndabilpuram@marvell.com", "date": "2022-08-09T18:48:54", "name": "[10/23] common/cnxk: support zero aura for inline inbound meta", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "2ae79214d17dd0f299d6e48857608a75603e86e9", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220809184908.24030-10-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 24239, "url": "http://patches.dpdk.org/api/series/24239/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24239", "date": "2022-08-09T18:48:45", "name": "[01/23] common/cnxk: fix part value for cn10k", "version": 1, "mbox": "http://patches.dpdk.org/series/24239/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/114788/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/114788/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 02422A04FD;\n\tTue, 9 Aug 2022 20:52:30 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E9F6942C02;\n\tTue, 9 Aug 2022 20:52:29 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id B8B1E42BE5\n for <dev@dpdk.org>; Tue, 9 Aug 2022 20:52:28 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 279CrYUm017200;\n Tue, 9 Aug 2022 11:50:22 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3hudy6ujv0-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Tue, 09 Aug 2022 11:50:22 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Tue, 9 Aug 2022 11:50:20 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 9 Aug 2022 11:50:20 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id D864B3F7149;\n Tue, 9 Aug 2022 11:50:08 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=o+8/U/26mZ1gwp4y53/ndyAac1k3QFj5KP0eng5X6L4=;\n b=UoE/jHm087EAGzb9OpxW48eHSPG9lv+wz+WpTEXOhW4lcnGRQA31ChFqrfdoqO8HcTDb\n yGubxeDt0+zTZgbV3A8koySyWwX8OsrZsFb+mWOLW6HE97cag0oBzX5T1fRye2ziIxwt\n hWfTD76BUXBVhZ5PA7osseMjpECLSquVPAjUkClWVQ3BCeSqTonZQyro/vJSfUwqFi0B\n Pr9RTr+h/v9aYkymkFuMzlghZ6hNPFH1kO5yZVn3oo2FFmkspmuofT6rgq05ge/1NVcZ\n 2E2a1YNDf+m9BePXvnPe5H77dY4l0mjFAWDSAgsE1pv1mbeD4gzgKzwiQ+q3wFFtvbfL uA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 10/23] common/cnxk: support zero aura for inline inbound meta", "Date": "Wed, 10 Aug 2022 00:18:54 +0530", "Message-ID": "<20220809184908.24030-10-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220809184908.24030-1-ndabilpuram@marvell.com>", "References": "<20220809184908.24030-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "1g9cZlJ3MWzO3M0-wjI7PvtqDR7OvRmx", "X-Proofpoint-ORIG-GUID": "1g9cZlJ3MWzO3M0-wjI7PvtqDR7OvRmx", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1\n definitions=2022-08-09_05,2022-08-09_02,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support to create zero aura for inline inbound meta pkts when platform\nsupports it. Aura zero will hold as many buffers as all the available\npkt pool with a data to accommodate 384B in best case to store\nmeta packets coming from Inline IPsec.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_idev.c | 10 ++\n drivers/common/cnxk/roc_idev.h | 1 +\n drivers/common/cnxk/roc_idev_priv.h | 9 ++\n drivers/common/cnxk/roc_nix.h | 1 +\n drivers/common/cnxk/roc_nix_inl.c | 211 +++++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_inl.h | 8 ++\n drivers/common/cnxk/roc_nix_inl_dev.c | 2 +\n drivers/common/cnxk/roc_nix_inl_priv.h | 4 +\n drivers/common/cnxk/roc_nix_priv.h | 1 +\n drivers/common/cnxk/roc_nix_queue.c | 19 +++\n drivers/common/cnxk/version.map | 4 +\n 11 files changed, 270 insertions(+)", "diff": "diff --git a/drivers/common/cnxk/roc_idev.c b/drivers/common/cnxk/roc_idev.c\nindex a08c7ce..4d2eff9 100644\n--- a/drivers/common/cnxk/roc_idev.c\n+++ b/drivers/common/cnxk/roc_idev.c\n@@ -241,3 +241,13 @@ idev_sso_set(struct roc_sso *sso)\n \tif (idev != NULL)\n \t\t__atomic_store_n(&idev->sso, sso, __ATOMIC_RELEASE);\n }\n+\n+uint64_t\n+roc_idev_nix_inl_meta_aura_get(void)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\n+\tif (idev != NULL)\n+\t\treturn idev->inl_cfg.meta_aura;\n+\treturn 0;\n+}\ndiff --git a/drivers/common/cnxk/roc_idev.h b/drivers/common/cnxk/roc_idev.h\nindex 16793c2..926aac0 100644\n--- a/drivers/common/cnxk/roc_idev.h\n+++ b/drivers/common/cnxk/roc_idev.h\n@@ -16,5 +16,6 @@ struct roc_cpt *__roc_api roc_idev_cpt_get(void);\n void __roc_api roc_idev_cpt_set(struct roc_cpt *cpt);\n \n struct roc_nix *__roc_api roc_idev_npa_nix_get(void);\n+uint64_t __roc_api roc_idev_nix_inl_meta_aura_get(void);\n \n #endif /* _ROC_IDEV_H_ */\ndiff --git a/drivers/common/cnxk/roc_idev_priv.h b/drivers/common/cnxk/roc_idev_priv.h\nindex 46eebff..315cc6f 100644\n--- a/drivers/common/cnxk/roc_idev_priv.h\n+++ b/drivers/common/cnxk/roc_idev_priv.h\n@@ -10,6 +10,14 @@ struct npa_lf;\n struct roc_bphy;\n struct roc_cpt;\n struct nix_inl_dev;\n+\n+struct idev_nix_inl_cfg {\n+\tuint64_t meta_aura;\n+\tuint32_t nb_bufs;\n+\tuint32_t buf_sz;\n+\tuint32_t refs;\n+};\n+\n struct idev_cfg {\n \tuint16_t sso_pf_func;\n \tuint16_t npa_pf_func;\n@@ -23,6 +31,7 @@ struct idev_cfg {\n \tstruct roc_cpt *cpt;\n \tstruct roc_sso *sso;\n \tstruct nix_inl_dev *nix_inl_dev;\n+\tstruct idev_nix_inl_cfg inl_cfg;\n \tplt_spinlock_t nix_inl_dev_lock;\n };\n \ndiff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 3ad3a7e..5f5f5f9 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -315,6 +315,7 @@ struct roc_nix_rq {\n \tbool spb_drop_ena;\n \t/* End of Input parameters */\n \tstruct roc_nix *roc_nix;\n+\tuint64_t meta_aura_handle;\n \tuint16_t inl_dev_refs;\n };\n \ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex c621867..507a153 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -6,6 +6,7 @@\n #include \"roc_priv.h\"\n \n uint32_t soft_exp_consumer_cnt;\n+roc_nix_inl_meta_pool_cb_t meta_pool_cb;\n \n PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ ==\n \t\t 1UL << ROC_NIX_INL_ONF_IPSEC_INB_SA_SZ_LOG2);\n@@ -19,6 +20,155 @@ PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ ==\n \t\t 1UL << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2);\n \n static int\n+nix_inl_meta_aura_destroy(void)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct idev_nix_inl_cfg *inl_cfg;\n+\tint rc;\n+\n+\tif (!idev)\n+\t\treturn -EINVAL;\n+\n+\tinl_cfg = &idev->inl_cfg;\n+\t/* Destroy existing Meta aura */\n+\tif (inl_cfg->meta_aura) {\n+\t\tuint64_t avail, limit;\n+\n+\t\t/* Check if all buffers are back to pool */\n+\t\tavail = roc_npa_aura_op_available(inl_cfg->meta_aura);\n+\t\tlimit = roc_npa_aura_op_limit_get(inl_cfg->meta_aura);\n+\t\tif (avail != limit)\n+\t\t\tplt_warn(\"Not all buffers are back to meta pool,\"\n+\t\t\t\t \" %\" PRIu64 \" != %\" PRIu64, avail, limit);\n+\n+\t\trc = meta_pool_cb(&inl_cfg->meta_aura, 0, 0, true);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to destroy meta aura, rc=%d\", rc);\n+\t\t\treturn rc;\n+\t\t}\n+\t\tinl_cfg->meta_aura = 0;\n+\t\tinl_cfg->buf_sz = 0;\n+\t\tinl_cfg->nb_bufs = 0;\n+\t\tinl_cfg->refs = 0;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+nix_inl_meta_aura_create(struct idev_cfg *idev, uint16_t first_skip)\n+{\n+\tuint64_t mask = BIT_ULL(ROC_NPA_BUF_TYPE_PACKET_IPSEC);\n+\tstruct idev_nix_inl_cfg *inl_cfg;\n+\tstruct nix_inl_dev *nix_inl_dev;\n+\tuint32_t nb_bufs, buf_sz;\n+\tint rc;\n+\n+\tinl_cfg = &idev->inl_cfg;\n+\tnix_inl_dev = idev->nix_inl_dev;\n+\n+\t/* Override meta buf count from devargs if present */\n+\tif (nix_inl_dev && nix_inl_dev->nb_meta_bufs)\n+\t\tnb_bufs = nix_inl_dev->nb_meta_bufs;\n+\telse\n+\t\tnb_bufs = roc_npa_buf_type_limit_get(mask);\n+\n+\t/* Override meta buf size from devargs if present */\n+\tif (nix_inl_dev && nix_inl_dev->meta_buf_sz)\n+\t\tbuf_sz = nix_inl_dev->meta_buf_sz;\n+\telse\n+\t\tbuf_sz = first_skip + NIX_INL_META_SIZE;\n+\n+\t/* Allocate meta aura */\n+\trc = meta_pool_cb(&inl_cfg->meta_aura, buf_sz, nb_bufs, false);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to allocate meta aura, rc=%d\", rc);\n+\t\treturn rc;\n+\t}\n+\n+\tinl_cfg->buf_sz = buf_sz;\n+\tinl_cfg->nb_bufs = nb_bufs;\n+\treturn 0;\n+}\n+\n+int\n+roc_nix_inl_meta_aura_check(struct roc_nix_rq *rq)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct idev_nix_inl_cfg *inl_cfg;\n+\tuint32_t actual, expected;\n+\tuint64_t mask, type_mask;\n+\tint rc;\n+\n+\tif (!idev || !meta_pool_cb)\n+\t\treturn -EFAULT;\n+\tinl_cfg = &idev->inl_cfg;\n+\n+\t/* Create meta aura if not present */\n+\tif (!inl_cfg->meta_aura) {\n+\t\trc = nix_inl_meta_aura_create(idev, rq->first_skip);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n+\t/* Validate if we have enough meta buffers */\n+\tmask = BIT_ULL(ROC_NPA_BUF_TYPE_PACKET_IPSEC);\n+\texpected = roc_npa_buf_type_limit_get(mask);\n+\tactual = inl_cfg->nb_bufs;\n+\n+\tif (actual < expected) {\n+\t\tplt_err(\"Insufficient buffers in meta aura %u < %u (expected)\",\n+\t\t\tactual, expected);\n+\t\treturn -EIO;\n+\t}\n+\n+\t/* Validate if we have enough space for meta buffer */\n+\tif (rq->first_skip + NIX_INL_META_SIZE > inl_cfg->buf_sz) {\n+\t\tplt_err(\"Meta buffer size %u not sufficient to meet RQ first skip %u\",\n+\t\t\tinl_cfg->buf_sz, rq->first_skip);\n+\t\treturn -EIO;\n+\t}\n+\n+\t/* Validate if we have enough VWQE buffers */\n+\tif (rq->vwqe_ena) {\n+\t\tactual = roc_npa_aura_op_limit_get(rq->vwqe_aura_handle);\n+\n+\t\ttype_mask = roc_npa_buf_type_mask(rq->vwqe_aura_handle);\n+\t\tif (type_mask & BIT_ULL(ROC_NPA_BUF_TYPE_VWQE_IPSEC) &&\n+\t\t type_mask & BIT_ULL(ROC_NPA_BUF_TYPE_VWQE)) {\n+\t\t\t/* VWQE aura shared b/w Inline enabled and non Inline\n+\t\t\t * enabled ports needs enough buffers to store all the\n+\t\t\t * packet buffers, one per vwqe.\n+\t\t\t */\n+\t\t\tmask = (BIT_ULL(ROC_NPA_BUF_TYPE_PACKET_IPSEC) |\n+\t\t\t\tBIT_ULL(ROC_NPA_BUF_TYPE_PACKET));\n+\t\t\texpected = roc_npa_buf_type_limit_get(mask);\n+\n+\t\t\tif (actual < expected) {\n+\t\t\t\tplt_err(\"VWQE aura shared b/w Inline inbound and non-Inline inbound \"\n+\t\t\t\t\t\"ports needs vwqe bufs(%u) minimum of all pkt bufs (%u)\",\n+\t\t\t\t\tactual, expected);\n+\t\t\t\treturn -EIO;\n+\t\t\t}\n+\t\t} else {\n+\t\t\t/* VWQE aura not shared b/w Inline and non Inline ports have relaxed\n+\t\t\t * requirement of match all the meta buffers.\n+\t\t\t */\n+\t\t\texpected = inl_cfg->nb_bufs;\n+\n+\t\t\tif (actual < expected) {\n+\t\t\t\tplt_err(\"VWQE aura not shared b/w Inline inbound and non-Inline \"\n+\t\t\t\t\t\"ports needs vwqe bufs(%u) minimum of all meta bufs (%u)\",\n+\t\t\t\t\tactual, expected);\n+\t\t\t\treturn -EIO;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)\n {\n \tuint32_t ipsec_in_min_spi = roc_nix->ipsec_in_min_spi;\n@@ -310,6 +460,10 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n \tif (rc)\n \t\treturn rc;\n \n+\tif (!roc_model_is_cn9k() && !roc_errata_nix_no_meta_aura()) {\n+\t\tnix->need_meta_aura = true;\n+\t\tidev->inl_cfg.refs++;\n+\t}\n \tnix->inl_inb_ena = true;\n \treturn 0;\n }\n@@ -317,12 +471,22 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n int\n roc_nix_inl_inb_fini(struct roc_nix *roc_nix)\n {\n+\tstruct idev_cfg *idev = idev_get_cfg();\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \n \tif (!nix->inl_inb_ena)\n \t\treturn 0;\n \n+\tif (!idev)\n+\t\treturn -EFAULT;\n+\n \tnix->inl_inb_ena = false;\n+\tif (nix->need_meta_aura) {\n+\t\tnix->need_meta_aura = false;\n+\t\tidev->inl_cfg.refs--;\n+\t\tif (!idev->inl_cfg.refs)\n+\t\t\tnix_inl_meta_aura_destroy();\n+\t}\n \n \t/* Flush Inbound CTX cache entries */\n \troc_nix_cpt_ctx_cache_sync(roc_nix);\n@@ -592,6 +756,7 @@ roc_nix_inl_outb_is_enabled(struct roc_nix *roc_nix)\n int\n roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool enable)\n {\n+\tstruct nix *nix = roc_nix_to_nix_priv(rq->roc_nix);\n \tstruct idev_cfg *idev = idev_get_cfg();\n \tint port_id = rq->roc_nix->port_id;\n \tstruct nix_inl_dev *inl_dev;\n@@ -603,6 +768,10 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool enable)\n \tif (idev == NULL)\n \t\treturn 0;\n \n+\t/* Update meta aura handle in RQ */\n+\tif (nix->need_meta_aura)\n+\t\trq->meta_aura_handle = roc_npa_zero_aura_handle();\n+\n \tinl_dev = idev->nix_inl_dev;\n \t/* Nothing to do if no inline device */\n \tif (!inl_dev)\n@@ -705,6 +874,13 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool enable)\n \t\treturn rc;\n \t}\n \n+\t/* Check meta aura */\n+\tif (enable && nix->need_meta_aura) {\n+\t\trc = roc_nix_inl_meta_aura_check(rq);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n \tinl_rq->inl_dev_refs++;\n \trq->inl_dev_refs = 1;\n \treturn 0;\n@@ -724,6 +900,7 @@ roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq)\n \tif (idev == NULL)\n \t\treturn 0;\n \n+\trq->meta_aura_handle = 0;\n \tif (!rq->inl_dev_refs)\n \t\treturn 0;\n \n@@ -779,6 +956,9 @@ roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool enable)\n \t\trc = nix_rq_ena_dis(&inl_dev->dev, inl_rq, enable);\n \t\tif (rc)\n \t\t\treturn rc;\n+\n+\t\tif (enable && nix->need_meta_aura)\n+\t\t\treturn roc_nix_inl_meta_aura_check(inl_rq);\n \t}\n \treturn 0;\n }\n@@ -792,6 +972,31 @@ roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev)\n \tnix->inb_inl_dev = use_inl_dev;\n }\n \n+void\n+roc_nix_inl_inb_set(struct roc_nix *roc_nix, bool ena)\n+{\n+\tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\n+\tif (!idev)\n+\t\treturn;\n+\t/* Need to set here for cases when inbound SA table is\n+\t * managed outside RoC.\n+\t */\n+\tnix->inl_inb_ena = ena;\n+\tif (!roc_model_is_cn9k() && !roc_errata_nix_no_meta_aura()) {\n+\t\tif (ena) {\n+\t\t\tnix->need_meta_aura = true;\n+\t\t\tidev->inl_cfg.refs++;\n+\t\t} else if (nix->need_meta_aura) {\n+\t\t\tnix->need_meta_aura = false;\n+\t\t\tidev->inl_cfg.refs--;\n+\t\t\tif (!idev->inl_cfg.refs)\n+\t\t\t\tnix_inl_meta_aura_destroy();\n+\t\t}\n+\t}\n+}\n+\n int\n roc_nix_inl_outb_soft_exp_poll_switch(struct roc_nix *roc_nix, bool poll)\n {\n@@ -1128,3 +1333,9 @@ roc_nix_inl_dev_unlock(void)\n \tif (idev != NULL)\n \t\tplt_spinlock_unlock(&idev->nix_inl_dev_lock);\n }\n+\n+void\n+roc_nix_inl_meta_pool_cb_register(roc_nix_inl_meta_pool_cb_t cb)\n+{\n+\tmeta_pool_cb = cb;\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nindex 702ec01..9911a48 100644\n--- a/drivers/common/cnxk/roc_nix_inl.h\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -121,6 +121,9 @@ roc_nix_inl_ot_ipsec_outb_sa_sw_rsvd(void *sa)\n typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args,\n \t\t\t\t\t uint32_t soft_exp_event);\n \n+typedef int (*roc_nix_inl_meta_pool_cb_t)(uint64_t *aura_handle, uint32_t blk_sz, uint32_t nb_bufs,\n+\t\t\t\t\t bool destroy);\n+\n struct roc_nix_inl_dev {\n \t/* Input parameters */\n \tstruct plt_pci_device *pci_dev;\n@@ -135,6 +138,8 @@ struct roc_nix_inl_dev {\n \tuint8_t spb_drop_pc;\n \tuint8_t lpb_drop_pc;\n \tbool set_soft_exp_poll;\n+\tuint32_t nb_meta_bufs;\n+\tuint32_t meta_buf_sz;\n \t/* End of input parameters */\n \n #define ROC_NIX_INL_MEM_SZ (1280)\n@@ -165,6 +170,7 @@ uint32_t __roc_api roc_nix_inl_inb_sa_sz(struct roc_nix *roc_nix,\n uintptr_t __roc_api roc_nix_inl_inb_sa_get(struct roc_nix *roc_nix,\n \t\t\t\t\t bool inl_dev_sa, uint32_t spi);\n void __roc_api roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev);\n+void __roc_api roc_nix_inl_inb_set(struct roc_nix *roc_nix, bool ena);\n int __roc_api roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq, bool ena);\n int __roc_api roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq);\n bool __roc_api roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix);\n@@ -176,6 +182,7 @@ int __roc_api roc_nix_reassembly_configure(uint32_t max_wait_time,\n int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena,\n \t\t\t\t bool inb_inl_dev);\n int __roc_api roc_nix_inl_rq_ena_dis(struct roc_nix *roc_nix, bool ena);\n+int __roc_api roc_nix_inl_meta_aura_check(struct roc_nix_rq *rq);\n \n /* NIX Inline Outbound API */\n int __roc_api roc_nix_inl_outb_init(struct roc_nix *roc_nix);\n@@ -191,6 +198,7 @@ int __roc_api roc_nix_inl_cb_unregister(roc_nix_inl_sso_work_cb_t cb,\n int __roc_api roc_nix_inl_outb_soft_exp_poll_switch(struct roc_nix *roc_nix,\n \t\t\t\t\t\t bool poll);\n uint64_t *__roc_api roc_nix_inl_outb_ring_base_get(struct roc_nix *roc_nix);\n+void __roc_api roc_nix_inl_meta_pool_cb_register(roc_nix_inl_meta_pool_cb_t cb);\n \n /* NIX Inline/Outbound API */\n enum roc_nix_inl_sa_sync_op {\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c\nindex 3a96498..1e9b2b9 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev.c\n@@ -841,6 +841,8 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)\n \tinl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT;\n \tinl_dev->set_soft_exp_poll = roc_inl_dev->set_soft_exp_poll;\n \tinl_dev->nb_rqs = inl_dev->is_multi_channel ? 1 : PLT_MAX_ETHPORTS;\n+\tinl_dev->nb_meta_bufs = roc_inl_dev->nb_meta_bufs;\n+\tinl_dev->meta_buf_sz = roc_inl_dev->meta_buf_sz;\n \n \tif (roc_inl_dev->spb_drop_pc)\n \t\tinl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc;\ndiff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h\nindex a775efc..ccd2adf 100644\n--- a/drivers/common/cnxk/roc_nix_inl_priv.h\n+++ b/drivers/common/cnxk/roc_nix_inl_priv.h\n@@ -6,6 +6,8 @@\n #include <pthread.h>\n #include <sys/types.h>\n \n+#define NIX_INL_META_SIZE 384u\n+\n struct nix_inl_dev;\n struct nix_inl_qint {\n \tstruct nix_inl_dev *inl_dev;\n@@ -86,6 +88,8 @@ struct nix_inl_dev {\n \tbool attach_cptlf;\n \tuint16_t wqe_skip;\n \tbool ts_ena;\n+\tuint32_t nb_meta_bufs;\n+\tuint32_t meta_buf_sz;\n };\n \n int nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev);\ndiff --git a/drivers/common/cnxk/roc_nix_priv.h b/drivers/common/cnxk/roc_nix_priv.h\nindex a3d4ddf..a253f41 100644\n--- a/drivers/common/cnxk/roc_nix_priv.h\n+++ b/drivers/common/cnxk/roc_nix_priv.h\n@@ -202,6 +202,7 @@ struct nix {\n \tuint16_t nb_cpt_lf;\n \tuint16_t outb_se_ring_cnt;\n \tuint16_t outb_se_ring_base;\n+\tbool need_meta_aura;\n \t/* Mode provided by driver */\n \tbool inb_inl_dev;\n \ndiff --git a/drivers/common/cnxk/roc_nix_queue.c b/drivers/common/cnxk/roc_nix_queue.c\nindex 98b9fb4..b197de0 100644\n--- a/drivers/common/cnxk/roc_nix_queue.c\n+++ b/drivers/common/cnxk/roc_nix_queue.c\n@@ -89,7 +89,12 @@ roc_nix_rq_ena_dis(struct roc_nix_rq *rq, bool enable)\n \n \trc = nix_rq_ena_dis(&nix->dev, rq, enable);\n \tnix_rq_vwqe_flush(rq, nix->vwqe_interval);\n+\tif (rc)\n+\t\treturn rc;\n \n+\t/* Check for meta aura if RQ is enabled */\n+\tif (enable && nix->need_meta_aura)\n+\t\trc = roc_nix_inl_meta_aura_check(rq);\n \treturn rc;\n }\n \n@@ -556,6 +561,13 @@ roc_nix_rq_init(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \t/* Update aura buf type to indicate its use */\n \tnix_rq_aura_buf_type_update(rq, true);\n \n+\t/* Check for meta aura if RQ is enabled */\n+\tif (ena && nix->need_meta_aura) {\n+\t\trc = roc_nix_inl_meta_aura_check(rq);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n \treturn nix_tel_node_add_rq(rq);\n }\n \n@@ -594,6 +606,13 @@ roc_nix_rq_modify(struct roc_nix *roc_nix, struct roc_nix_rq *rq, bool ena)\n \t/* Update aura attribute to indicate its use */\n \tnix_rq_aura_buf_type_update(rq, true);\n \n+\t/* Check for meta aura if RQ is enabled */\n+\tif (ena && nix->need_meta_aura) {\n+\t\trc = roc_nix_inl_meta_aura_check(rq);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n \treturn nix_tel_node_add_rq(rq);\n }\n \ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 6f3de2a..276fec3 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -95,6 +95,7 @@ INTERNAL {\n \troc_idev_npa_maxpools_set;\n \troc_idev_npa_nix_get;\n \troc_idev_num_lmtlines_get;\n+\troc_idev_nix_inl_meta_aura_get;\n \troc_model;\n \troc_se_auth_key_set;\n \troc_se_ciph_key_set;\n@@ -156,7 +157,10 @@ INTERNAL {\n \troc_nix_inl_inb_sa_sz;\n \troc_nix_inl_inb_tag_update;\n \troc_nix_inl_inb_fini;\n+\troc_nix_inl_inb_set;\n \troc_nix_inb_is_with_inl_dev;\n+\troc_nix_inl_meta_aura_check;\n+\troc_nix_inl_meta_pool_cb_register;\n \troc_nix_inb_mode_set;\n \troc_nix_inl_outb_fini;\n \troc_nix_inl_outb_init;\n", "prefixes": [ "10/23" ] }