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GET /api/patches/114746/?format=api
{ "id": 114746, "url": "http://patches.dpdk.org/api/patches/114746/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220809105356.561-3-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220809105356.561-3-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220809105356.561-3-anoobj@marvell.com", "date": "2022-08-09T10:53:40", "name": "[v2,02/18] crypto/cnxk: add burst enqueue for event crypto", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f3830d7c52545a4b3f4bd010f29912cb670b52af", "submitter": { "id": 1205, "url": "http://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220809105356.561-3-anoobj@marvell.com/mbox/", "series": [ { "id": 24235, "url": "http://patches.dpdk.org/api/series/24235/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=24235", "date": "2022-08-09T10:53:38", "name": "Fixes and improvements in cnxk crypto PMDs", "version": 2, "mbox": "http://patches.dpdk.org/series/24235/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/114746/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/114746/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7D0CFA00C5;\n\tTue, 9 Aug 2022 12:54:18 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B1FF042BB1;\n\tTue, 9 Aug 2022 12:54:09 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 1210942BAE\n for <dev@dpdk.org>; Tue, 9 Aug 2022 12:54:06 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 2791T39W017143\n for <dev@dpdk.org>; Tue, 9 Aug 2022 03:54:06 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3hudy6spgk-2\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 09 Aug 2022 03:54:06 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 9 Aug 2022 03:54:04 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Tue, 9 Aug 2022 03:54:04 -0700", "from BG-LT92004.corp.innovium.com (unknown [10.193.69.70])\n by maili.marvell.com (Postfix) with ESMTP id 5C1B03F706A;\n Tue, 9 Aug 2022 03:54:02 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=2sEp2bU0Gn60Tb6nO1uddLqqiCn1mbPS5Z3qmxYEUY0=;\n b=YxJzSXxk0oV0Fm3x588jcHIn7fxaLX2KQyuGCdmJ8b/YpqFMf4DiiH0NzkgT9lCsArjE\n fGMH+rPr9yM73r8B0ml1O+n1NHfO/VGQpB3SeRdMYZxgFuBklSDLL1bAz/s+VL74fyZE\n iGHGWStQsGp6J9ppJC8dUsfYNGYqEkmIT/ZobicHORh9S/wVPW2GQOdJJ8yux4356vAs\n hg/dicnhp9VOLp4coOTw1KAGJHduVIHZxColntAnsz2SfzZZt4CfeMm42GTAU9agKlXd\n Fh2mAxP9equh4Y6jjGSTADXxvl7PfGD3gfGlxd7SLhpi9maC5y76d00fcFT1QWnZz081 Mg==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Jerin Jacob <jerinj@marvell.com>", "CC": "Volodymyr Fialko <vfialko@marvell.com>, Archana Muniganti\n <marchana@marvell.com>,\n Tejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH v2 02/18] crypto/cnxk: add burst enqueue for event crypto", "Date": "Tue, 9 Aug 2022 16:23:40 +0530", "Message-ID": "<20220809105356.561-3-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220809105356.561-1-anoobj@marvell.com>", "References": "<20220808080606.220-1-anoobj@marvell.com>\n <20220809105356.561-1-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "VQrGWKKKJ33u4rtQ49mO83Oup1h22w3f", "X-Proofpoint-ORIG-GUID": "VQrGWKKKJ33u4rtQ49mO83Oup1h22w3f", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1\n definitions=2022-08-09_03,2022-08-09_02,2022-06-22_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Volodymyr Fialko <vfialko@marvell.com>\n\nAdded support for burst enqueue for cn10k event crypto adapter.\nInstruction will be grouped based on the queue pair and sent in a burst.\n\nSigned-off-by: Volodymyr Fialko <vfialko@marvell.com>\n---\n drivers/crypto/cnxk/cn10k_cryptodev_ops.c | 141 +++++++++++++++-------\n drivers/crypto/cnxk/cn10k_cryptodev_ops.h | 7 +-\n drivers/crypto/cnxk/meson.build | 2 +-\n drivers/event/cnxk/cn10k_eventdev.c | 2 +-\n drivers/event/cnxk/cn10k_worker.c | 10 --\n drivers/event/cnxk/cn10k_worker.h | 2 -\n 6 files changed, 105 insertions(+), 59 deletions(-)", "diff": "diff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\nindex f761ba36e2..bfa6374005 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.c\n@@ -9,11 +9,12 @@\n \n #include \"cn10k_cryptodev.h\"\n #include \"cn10k_cryptodev_ops.h\"\n-#include \"cn10k_ipsec_la_ops.h\"\n #include \"cn10k_ipsec.h\"\n+#include \"cn10k_ipsec_la_ops.h\"\n #include \"cnxk_ae.h\"\n #include \"cnxk_cryptodev.h\"\n #include \"cnxk_cryptodev_ops.h\"\n+#include \"cnxk_eventdev.h\"\n #include \"cnxk_se.h\"\n \n #include \"roc_api.h\"\n@@ -391,79 +392,135 @@ cn10k_ca_meta_info_extract(struct rte_crypto_op *op,\n \treturn 0;\n }\n \n-uint16_t\n-cn10k_cpt_crypto_adapter_enqueue(uintptr_t base, struct rte_crypto_op *op)\n+static inline uint16_t\n+ca_lmtst_burst_submit(struct cn10k_sso_hws *ws, uint64_t w2[], struct cnxk_cpt_qp *qp,\n+\t\t struct rte_crypto_op *op[], uint16_t nb_ops)\n {\n+\tstruct cpt_inflight_req *infl_reqs[PKTS_PER_LOOP];\n+\tuint64_t lmt_base, lmt_arg, io_addr;\n+\tstruct cpt_inst_s *inst, *inst_base;\n \tstruct cpt_inflight_req *infl_req;\n-\tuint64_t lmt_base, lmt_arg, w2;\n-\tstruct cpt_inst_s *inst;\n \tunion cpt_fc_write_s fc;\n-\tstruct cnxk_cpt_qp *qp;\n \tuint64_t *fc_addr;\n \tuint16_t lmt_id;\n-\tint ret;\n+\tint ret, i;\n \n-\tret = cn10k_ca_meta_info_extract(op, &qp, &w2);\n-\tif (unlikely(ret)) {\n-\t\trte_errno = EINVAL;\n-\t\treturn 0;\n-\t}\n+\tlmt_base = qp->lmtline.lmt_base;\n+\tio_addr = qp->lmtline.io_addr;\n+\tfc_addr = qp->lmtline.fc_addr;\n+\n+\tconst uint32_t fc_thresh = qp->lmtline.fc_thresh;\n+\n+\tROC_LMT_BASE_ID_GET(lmt_base, lmt_id);\n+\tinst_base = (struct cpt_inst_s *)lmt_base;\n \n \tif (unlikely(!qp->ca.enabled)) {\n \t\trte_errno = EINVAL;\n \t\treturn 0;\n \t}\n \n-\tif (unlikely(rte_mempool_get(qp->ca.req_mp, (void **)&infl_req))) {\n+\tif (unlikely(rte_mempool_get_bulk(qp->ca.req_mp, (void **)infl_reqs, nb_ops))) {\n \t\trte_errno = ENOMEM;\n \t\treturn 0;\n \t}\n-\tinfl_req->op_flags = 0;\n-\n-\tlmt_base = qp->lmtline.lmt_base;\n-\tfc_addr = qp->lmtline.fc_addr;\n \n-\tconst uint32_t fc_thresh = qp->lmtline.fc_thresh;\n+\tfor (i = 0; i < nb_ops; i++) {\n+\t\tinst = &inst_base[2 * i];\n+\t\tinfl_req = infl_reqs[i];\n+\t\tinfl_req->op_flags = 0;\n \n-\tROC_LMT_BASE_ID_GET(lmt_base, lmt_id);\n-\tinst = (struct cpt_inst_s *)lmt_base;\n+\t\tret = cn10k_cpt_fill_inst(qp, &op[i], inst, infl_req);\n+\t\tif (unlikely(ret != 1)) {\n+\t\t\tplt_dp_err(\"Could not process op: %p\", op[i]);\n+\t\t\tif (i != 0)\n+\t\t\t\tgoto submit;\n+\t\t\telse\n+\t\t\t\tgoto put;\n+\t\t}\n \n-\tret = cn10k_cpt_fill_inst(qp, &op, inst, infl_req);\n-\tif (unlikely(ret != 1)) {\n-\t\tplt_dp_err(\"Could not process op: %p\", op);\n-\t\trte_mempool_put(qp->ca.req_mp, infl_req);\n-\t\treturn 0;\n+\t\tinfl_req->res.cn10k.compcode = CPT_COMP_NOT_DONE;\n+\t\tinfl_req->qp = qp;\n+\t\tinst->w0.u64 = 0;\n+\t\tinst->res_addr = (uint64_t)&infl_req->res;\n+\t\tinst->w2.u64 = w2[i];\n+\t\tinst->w3.u64 = CNXK_CPT_INST_W3(1, infl_req);\n \t}\n \n-\tinfl_req->cop = op;\n-\tinfl_req->res.cn10k.compcode = CPT_COMP_NOT_DONE;\n-\tinfl_req->qp = qp;\n-\tinst->w0.u64 = 0;\n-\tinst->res_addr = (uint64_t)&infl_req->res;\n-\tinst->w2.u64 = w2;\n-\tinst->w3.u64 = CNXK_CPT_INST_W3(1, infl_req);\n-\n \tfc.u64[0] = __atomic_load_n(fc_addr, __ATOMIC_RELAXED);\n \tif (unlikely(fc.s.qsize > fc_thresh)) {\n-\t\trte_mempool_put(qp->ca.req_mp, infl_req);\n \t\trte_errno = EAGAIN;\n-\t\treturn 0;\n+\t\ti = 0;\n+\t\tgoto put;\n \t}\n \n-\tif (inst->w2.s.tt == RTE_SCHED_TYPE_ORDERED)\n-\t\troc_sso_hws_head_wait(base);\n+submit:\n+\tif (CNXK_TT_FROM_TAG(ws->gw_rdata) == SSO_TT_ORDERED)\n+\t\troc_sso_hws_head_wait(ws->base);\n \n-\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (uint64_t)lmt_id;\n-\troc_lmt_submit_steorl(lmt_arg, qp->lmtline.io_addr);\n+\tif (i > PKTS_PER_STEORL) {\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (PKTS_PER_STEORL - 1) << 12 | (uint64_t)lmt_id;\n+\t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - PKTS_PER_STEORL - 1) << 12 |\n+\t\t\t (uint64_t)(lmt_id + PKTS_PER_STEORL);\n+\t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n+\t} else {\n+\t\tlmt_arg = ROC_CN10K_CPT_LMT_ARG | (i - 1) << 12 | (uint64_t)lmt_id;\n+\t\troc_lmt_submit_steorl(lmt_arg, io_addr);\n+\t}\n \n \trte_io_wmb();\n \n-\treturn 1;\n+put:\n+\tif (unlikely(i != nb_ops))\n+\t\trte_mempool_put_bulk(qp->ca.req_mp, (void *)&infl_reqs[i], nb_ops - i);\n+\n+\treturn i;\n+}\n+\n+uint16_t __rte_hot\n+cn10k_cpt_crypto_adapter_enqueue(void *ws, struct rte_event ev[], uint16_t nb_events)\n+{\n+\tstruct rte_crypto_op *ops[PKTS_PER_LOOP], *op;\n+\tstruct cnxk_cpt_qp *qp, *curr_qp = NULL;\n+\tuint64_t w2s[PKTS_PER_LOOP], w2;\n+\tuint16_t submitted, count = 0;\n+\tint ret, i, ops_len = 0;\n+\n+\tfor (i = 0; i < nb_events; i++) {\n+\t\top = ev[i].event_ptr;\n+\t\tret = cn10k_ca_meta_info_extract(op, &qp, &w2);\n+\t\tif (unlikely(ret)) {\n+\t\t\trte_errno = EINVAL;\n+\t\t\treturn count;\n+\t\t}\n+\n+\t\tif (qp != curr_qp) {\n+\t\t\tif (ops_len) {\n+\t\t\t\tsubmitted = ca_lmtst_burst_submit(ws, w2s, curr_qp, ops, ops_len);\n+\t\t\t\tcount += submitted;\n+\t\t\t\tif (unlikely(submitted != ops_len))\n+\t\t\t\t\treturn count;\n+\t\t\t\tops_len = 0;\n+\t\t\t}\n+\t\t\tcurr_qp = qp;\n+\t\t}\n+\t\tw2s[ops_len] = w2;\n+\t\tops[ops_len] = op;\n+\t\tif (++ops_len == PKTS_PER_LOOP) {\n+\t\t\tsubmitted = ca_lmtst_burst_submit(ws, w2s, curr_qp, ops, ops_len);\n+\t\t\tcount += submitted;\n+\t\t\tif (unlikely(submitted != ops_len))\n+\t\t\t\treturn count;\n+\t\t\tops_len = 0;\n+\t\t}\n+\t}\n+\tif (ops_len)\n+\t\tcount += ca_lmtst_burst_submit(ws, w2s, curr_qp, ops, ops_len);\n+\treturn count;\n }\n \n static inline void\n-cn10k_cpt_sec_post_process(struct rte_crypto_op *cop,\n-\t\t\t struct cpt_cn10k_res_s *res)\n+cn10k_cpt_sec_post_process(struct rte_crypto_op *cop, struct cpt_cn10k_res_s *res)\n {\n \tstruct rte_mbuf *mbuf = cop->sym->m_src;\n \tconst uint16_t m_len = res->rlen;\ndiff --git a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h\nindex 1ad4c16873..628d6a567c 100644\n--- a/drivers/crypto/cnxk/cn10k_cryptodev_ops.h\n+++ b/drivers/crypto/cnxk/cn10k_cryptodev_ops.h\n@@ -5,16 +5,17 @@\n #ifndef _CN10K_CRYPTODEV_OPS_H_\n #define _CN10K_CRYPTODEV_OPS_H_\n \n-#include <rte_cryptodev.h>\n #include <cryptodev_pmd.h>\n+#include <rte_cryptodev.h>\n+#include <rte_eventdev.h>\n \n extern struct rte_cryptodev_ops cn10k_cpt_ops;\n \n void cn10k_cpt_set_enqdeq_fns(struct rte_cryptodev *dev);\n \n __rte_internal\n-uint16_t cn10k_cpt_crypto_adapter_enqueue(uintptr_t base,\n-\t\t\t\t\t struct rte_crypto_op *op);\n+uint16_t __rte_hot cn10k_cpt_crypto_adapter_enqueue(void *ws, struct rte_event ev[],\n+\t\tuint16_t nb_events);\n __rte_internal\n uintptr_t cn10k_cpt_crypto_adapter_dequeue(uintptr_t get_work1);\n \ndiff --git a/drivers/crypto/cnxk/meson.build b/drivers/crypto/cnxk/meson.build\nindex 23a1cc3aac..952554ac12 100644\n--- a/drivers/crypto/cnxk/meson.build\n+++ b/drivers/crypto/cnxk/meson.build\n@@ -24,7 +24,7 @@ sources = files(\n \n deps += ['bus_pci', 'common_cnxk', 'security', 'eventdev']\n \n-includes += include_directories('../../../lib/net')\n+includes += include_directories('../../../lib/net', '../../event/cnxk')\n \n if get_option('buildtype').contains('debug')\n cflags += [ '-DLA_IPSEC_DEBUG' ]\ndiff --git a/drivers/event/cnxk/cn10k_eventdev.c b/drivers/event/cnxk/cn10k_eventdev.c\nindex 5a0cab40a9..25c85902d6 100644\n--- a/drivers/event/cnxk/cn10k_eventdev.c\n+++ b/drivers/event/cnxk/cn10k_eventdev.c\n@@ -454,7 +454,7 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)\n \t\t\t\t\t sso_hws_deq_tmo_ca_burst);\n \t\t}\n \t}\n-\tevent_dev->ca_enqueue = cn10k_sso_hws_ca_enq;\n+\tevent_dev->ca_enqueue = cn10k_cpt_crypto_adapter_enqueue;\n \n \tif (dev->tx_offloads & NIX_TX_MULTI_SEG_F)\n \t\tCN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,\ndiff --git a/drivers/event/cnxk/cn10k_worker.c b/drivers/event/cnxk/cn10k_worker.c\nindex f953e19dd0..4581c41233 100644\n--- a/drivers/event/cnxk/cn10k_worker.c\n+++ b/drivers/event/cnxk/cn10k_worker.c\n@@ -64,13 +64,3 @@ cn10k_sso_hws_enq_fwd_burst(void *port, const struct rte_event ev[],\n \n \treturn 1;\n }\n-\n-uint16_t __rte_hot\n-cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[], uint16_t nb_events)\n-{\n-\tstruct cn10k_sso_hws *ws = port;\n-\n-\tRTE_SET_USED(nb_events);\n-\n-\treturn cn10k_cpt_crypto_adapter_enqueue(ws->base, ev->event_ptr);\n-}\ndiff --git a/drivers/event/cnxk/cn10k_worker.h b/drivers/event/cnxk/cn10k_worker.h\nindex 0915f404e0..65bb08c0a1 100644\n--- a/drivers/event/cnxk/cn10k_worker.h\n+++ b/drivers/event/cnxk/cn10k_worker.h\n@@ -353,8 +353,6 @@ uint16_t __rte_hot cn10k_sso_hws_enq_new_burst(void *port,\n uint16_t __rte_hot cn10k_sso_hws_enq_fwd_burst(void *port,\n \t\t\t\t\t const struct rte_event ev[],\n \t\t\t\t\t uint16_t nb_events);\n-uint16_t __rte_hot cn10k_sso_hws_ca_enq(void *port, struct rte_event ev[],\n-\t\t\t\t\tuint16_t nb_events);\n \n #define R(name, flags) \\\n \tuint16_t __rte_hot cn10k_sso_hws_deq_##name( \\\n", "prefixes": [ "v2", "02/18" ] }