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GET /api/patches/113046/?format=api
{ "id": 113046, "url": "http://patches.dpdk.org/api/patches/113046/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220618084805.87315-6-lizh@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220618084805.87315-6-lizh@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220618084805.87315-6-lizh@nvidia.com", "date": "2022-06-18T08:47:55", "name": "[v3,05/15] common/mlx5: extend virtq modifiable fields", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b37f0cf444a6ccc21575e8bb9eef9091c2a4dc3d", "submitter": { "id": 1967, "url": "http://patches.dpdk.org/api/people/1967/?format=api", "name": "Li Zhang", "email": "lizh@nvidia.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220618084805.87315-6-lizh@nvidia.com/mbox/", "series": [ { "id": 23621, "url": "http://patches.dpdk.org/api/series/23621/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23621", "date": "2022-06-18T08:47:50", "name": "mlx5/vdpa: optimize live migration time", "version": 3, "mbox": "http://patches.dpdk.org/series/23621/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/113046/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/113046/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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<maxime.coquelin@redhat.com>", "Subject": "[PATCH v3 05/15] common/mlx5: extend virtq modifiable fields", "Date": "Sat, 18 Jun 2022 11:47:55 +0300", "Message-ID": "<20220618084805.87315-6-lizh@nvidia.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20220618084805.87315-1-lizh@nvidia.com>", "References": "<20220408075606.33056-1-lizh@nvidia.com>\n <20220618084805.87315-1-lizh@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "3752aa02-4ce4-4f4f-1852-08da510756f1", "X-MS-TrafficTypeDiagnostic": "BL3PR12MB6402:EE_", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BL3PR12MB64020E34737DB32117C43138BFAE9@BL3PR12MB6402.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 9R2LjjEahcQyf68wQ5SSBcHTS3y7aljWZwGLLYXMztZ/ev7hEHVBN1IHhqiq8u8K5qe0/7AWiuNBRELJJpgWt4Lw+KUx4HC5GKB5eWetcdy3WkAoNPhCglCGZffEHu/asGXEkdza5dgjYD6MuiLrYLe/XycdGKmE0NctnSW8HR0L3EkUgrrgPpSn4omhJ3Zgp9h9fU/hqoSrmmpRcgk23jUbeLHiH+91oG6Dk9m/dY/Db8zpfMQXt7Am4cOm3wrcinESUtl024isLJkhfyrFOiLkgR/KPXS4BnBs4mLPGdsjZifkCIfju4lmFIJXXROqXnDMbeOG9q6Xyra3HZNL+/boQtJFeiKu4n1FGdzmbYqVu1oxrhq5uoiNr0sChEWPLjsab7azbNBTRMrHN+QT/XEM3aGLa6BZZCaKiLpf/otRQ4aWdt2Q7hL7VlSoQ+Y41MyXACkYeJp12nnIYlXmLhuP8v282nfKL2P+NQUI1mbBX3iPWBBT1KpwxFnzhnxJ94+idRHszFBN1pnyojtFLwxHj+NeiHRgvwAzUHXKkakX6kmjUWSM5ThT8MotWkG1HtE8slpdbj0xmF8SuB3Agqm31YAWXGQuWoLcjIunF6HvVM5Sz1G0lfaMq3Rgz0l7T9bS3F2TN4QSdFnmNBqDfBuAYJp7djGfduy8AlEkmLV9ECcY+stFZRfWzQv7Fs1d8rarNhUkS3dQQaUZqGHDcA==", "X-Forefront-Antispam-Report": "CIP:12.22.5.236; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230016)(4636009)(40470700004)(46966006)(36840700001)(6666004)(55016003)(5660300002)(7696005)(81166007)(8676002)(356005)(82310400005)(70586007)(36860700001)(2906002)(498600001)(8936002)(4326008)(110136005)(2616005)(426003)(1076003)(47076005)(16526019)(70206006)(336012)(6636002)(54906003)(316002)(36756003)(26005)(6286002)(186003)(86362001)(83380400001)(40460700003)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Jun 2022 08:48:39.0202 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3752aa02-4ce4-4f4f-1852-08da510756f1", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.236];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT034.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL3PR12MB6402", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "A virtq configuration can be modified after the virtq creation.\nAdded the following modifiable fields:\n1.address fields: desc_addr/used_addr/available_addr\n2.hw_available_index\n3.hw_used_index\n4.virtio_q_type\n5.version type\n6.queue mkey\n7.feature bit mask: tso_ipv4/tso_ipv6/tx_csum/rx_csum\n8.event mode: event_mode/event_qpn_or_msix\n\nSigned-off-by: Li Zhang <lizh@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 70 +++++++++++++++++++++++-----\n drivers/common/mlx5/mlx5_devx_cmds.h | 6 ++-\n drivers/common/mlx5/mlx5_prm.h | 13 +++++-\n 3 files changed, 76 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 1d6d6578d6..1b68c37092 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -545,6 +545,15 @@ mlx5_devx_cmd_query_hca_vdpa_attr(void *ctx,\n \t\tvdpa_attr->log_doorbell_stride =\n \t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n \t\t\t\t log_doorbell_stride);\n+\t\tvdpa_attr->vnet_modify_ext =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t vnet_modify_ext);\n+\t\tvdpa_attr->virtio_net_q_addr_modify =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t virtio_net_q_addr_modify);\n+\t\tvdpa_attr->virtio_q_index_modify =\n+\t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n+\t\t\t\t virtio_q_index_modify);\n \t\tvdpa_attr->log_doorbell_bar_size =\n \t\t\tMLX5_GET(virtio_emulation_cap, hcattr,\n \t\t\t\t log_doorbell_bar_size);\n@@ -2074,27 +2083,66 @@ mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,\n \tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_type,\n \t\t MLX5_GENERAL_OBJ_TYPE_VIRTQ);\n \tMLX5_SET(general_obj_in_cmd_hdr, hdr, obj_id, virtq_obj->id);\n-\tMLX5_SET64(virtio_net_q, virtq, modify_field_select, attr->type);\n+\tMLX5_SET64(virtio_net_q, virtq, modify_field_select,\n+\t\tattr->mod_fields_bitmap);\n \tMLX5_SET16(virtio_q, virtctx, queue_index, attr->queue_index);\n-\tswitch (attr->type) {\n-\tcase MLX5_VIRTQ_MODIFY_TYPE_STATE:\n+\tif (!attr->mod_fields_bitmap) {\n+\t\tDRV_LOG(ERR, \"Failed to modify VIRTQ for no type set.\");\n+\t\trte_errno = EINVAL;\n+\t\treturn -rte_errno;\n+\t}\n+\tif (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_STATE)\n \t\tMLX5_SET16(virtio_net_q, virtq, state, attr->state);\n-\t\tbreak;\n-\tcase MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS:\n+\tif (attr->mod_fields_bitmap &\n+\t MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS) {\n \t\tMLX5_SET(virtio_net_q, virtq, dirty_bitmap_mkey,\n \t\t\t attr->dirty_bitmap_mkey);\n \t\tMLX5_SET64(virtio_net_q, virtq, dirty_bitmap_addr,\n \t\t\t attr->dirty_bitmap_addr);\n \t\tMLX5_SET(virtio_net_q, virtq, dirty_bitmap_size,\n \t\t\t attr->dirty_bitmap_size);\n-\t\tbreak;\n-\tcase MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE:\n+\t}\n+\tif (attr->mod_fields_bitmap &\n+\t MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE)\n \t\tMLX5_SET(virtio_net_q, virtq, dirty_bitmap_dump_enable,\n \t\t\t attr->dirty_bitmap_dump_enable);\n-\t\tbreak;\n-\tdefault:\n-\t\trte_errno = EINVAL;\n-\t\treturn -rte_errno;\n+\tif (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD) {\n+\t\tMLX5_SET(virtio_q, virtctx, queue_period_mode,\n+\t\t\tattr->hw_latency_mode);\n+\t\tMLX5_SET(virtio_q, virtctx, queue_period_us,\n+\t\t\tattr->hw_max_latency_us);\n+\t\tMLX5_SET(virtio_q, virtctx, queue_max_count,\n+\t\t\tattr->hw_max_pending_comp);\n+\t}\n+\tif (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_ADDR) {\n+\t\tMLX5_SET64(virtio_q, virtctx, desc_addr, attr->desc_addr);\n+\t\tMLX5_SET64(virtio_q, virtctx, used_addr, attr->used_addr);\n+\t\tMLX5_SET64(virtio_q, virtctx, available_addr,\n+\t\t\tattr->available_addr);\n+\t}\n+\tif (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX)\n+\t\tMLX5_SET16(virtio_net_q, virtq, hw_available_index,\n+\t\t attr->hw_available_index);\n+\tif (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX)\n+\t\tMLX5_SET16(virtio_net_q, virtq, hw_used_index,\n+\t\t\tattr->hw_used_index);\n+\tif (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_TYPE)\n+\t\tMLX5_SET16(virtio_q, virtctx, virtio_q_type, attr->q_type);\n+\tif (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0)\n+\t\tMLX5_SET16(virtio_q, virtctx, virtio_version_1_0,\n+\t\t attr->virtio_version_1_0);\n+\tif (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_Q_MKEY)\n+\t\tMLX5_SET(virtio_q, virtctx, virtio_q_mkey, attr->mkey);\n+\tif (attr->mod_fields_bitmap &\n+\t\tMLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK) {\n+\t\tMLX5_SET16(virtio_net_q, virtq, tso_ipv4, attr->tso_ipv4);\n+\t\tMLX5_SET16(virtio_net_q, virtq, tso_ipv6, attr->tso_ipv6);\n+\t\tMLX5_SET16(virtio_net_q, virtq, tx_csum, attr->tx_csum);\n+\t\tMLX5_SET16(virtio_net_q, virtq, rx_csum, attr->rx_csum);\n+\t}\n+\tif (attr->mod_fields_bitmap & MLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE) {\n+\t\tMLX5_SET16(virtio_q, virtctx, event_mode, attr->event_mode);\n+\t\tMLX5_SET(virtio_q, virtctx, event_qpn_or_msix, attr->qp_id);\n \t}\n \tret = mlx5_glue->devx_obj_modify(virtq_obj->obj, in, sizeof(in),\n \t\t\t\t\t out, sizeof(out));\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 3747ef9e33..ec6467d927 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -74,6 +74,9 @@ struct mlx5_hca_vdpa_attr {\n \tuint32_t log_doorbell_stride:5;\n \tuint32_t log_doorbell_bar_size:5;\n \tuint32_t queue_counters_valid:1;\n+\tuint32_t vnet_modify_ext:1;\n+\tuint32_t virtio_net_q_addr_modify:1;\n+\tuint32_t virtio_q_index_modify:1;\n \tuint32_t max_num_virtio_queues;\n \tstruct {\n \t\tuint32_t a;\n@@ -465,7 +468,7 @@ struct mlx5_devx_virtq_attr {\n \tuint32_t tis_id;\n \tuint32_t counters_obj_id;\n \tuint64_t dirty_bitmap_addr;\n-\tuint64_t type;\n+\tuint64_t mod_fields_bitmap;\n \tuint64_t desc_addr;\n \tuint64_t used_addr;\n \tuint64_t available_addr;\n@@ -475,6 +478,7 @@ struct mlx5_devx_virtq_attr {\n \t\tuint64_t offset;\n \t} umems[3];\n \tuint8_t error_type;\n+\tuint8_t q_type;\n };\n \n \ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 8a2f55c33e..5f58a6ee1d 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1802,7 +1802,9 @@ struct mlx5_ifc_virtio_emulation_cap_bits {\n \tu8 virtio_queue_type[0x8];\n \tu8 reserved_at_20[0x13];\n \tu8 log_doorbell_stride[0x5];\n-\tu8 reserved_at_3b[0x3];\n+\tu8 vnet_modify_ext[0x1];\n+\tu8 virtio_net_q_addr_modify[0x1];\n+\tu8 virtio_q_index_modify[0x1];\n \tu8 log_doorbell_bar_size[0x5];\n \tu8 doorbell_bar_offset[0x40];\n \tu8 reserved_at_80[0x8];\n@@ -3024,6 +3026,15 @@ enum {\n \tMLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),\n \tMLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),\n \tMLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),\n+\tMLX5_VIRTQ_MODIFY_TYPE_QUEUE_PERIOD = (1UL << 5),\n+\tMLX5_VIRTQ_MODIFY_TYPE_ADDR = (1UL << 6),\n+\tMLX5_VIRTQ_MODIFY_TYPE_HW_AVAILABLE_INDEX = (1UL << 7),\n+\tMLX5_VIRTQ_MODIFY_TYPE_HW_USED_INDEX = (1UL << 8),\n+\tMLX5_VIRTQ_MODIFY_TYPE_Q_TYPE = (1UL << 9),\n+\tMLX5_VIRTQ_MODIFY_TYPE_VERSION_1_0 = (1UL << 10),\n+\tMLX5_VIRTQ_MODIFY_TYPE_Q_MKEY = (1UL << 11),\n+\tMLX5_VIRTQ_MODIFY_TYPE_QUEUE_FEATURE_BIT_MASK = (1UL << 12),\n+\tMLX5_VIRTQ_MODIFY_TYPE_EVENT_MODE = (1UL << 13),\n };\n \n struct mlx5_ifc_virtio_q_bits {\n", "prefixes": [ "v3", "05/15" ] }