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GET /api/patches/112933/?format=api
{ "id": 112933, "url": "http://patches.dpdk.org/api/patches/112933/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220616195517.344509-3-timothy.mcdaniel@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220616195517.344509-3-timothy.mcdaniel@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220616195517.344509-3-timothy.mcdaniel@intel.com", "date": "2022-06-16T19:55:17", "name": "[v2,2/2] event/dlb2: add ldb port specific COS support", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "49759bbc0e1a4af1dec3c8e494b4799f67d71d51", "submitter": { "id": 826, "url": "http://patches.dpdk.org/api/people/826/?format=api", "name": "Timothy McDaniel", "email": "timothy.mcdaniel@intel.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220616195517.344509-3-timothy.mcdaniel@intel.com/mbox/", "series": [ { "id": 23586, "url": "http://patches.dpdk.org/api/series/23586/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23586", "date": "2022-06-16T19:55:15", "name": "Rebase DLB2 port_cos and cq_weight patches", "version": 2, "mbox": "http://patches.dpdk.org/series/23586/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/112933/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/112933/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 77553A00C2;\n\tThu, 16 Jun 2022 21:55:34 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id EB8F04114F;\n\tThu, 16 Jun 2022 21:55:26 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 967D240F19\n for <dev@dpdk.org>; Thu, 16 Jun 2022 21:55:24 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Jun 2022 12:55:24 -0700", "from txanpdk03.an.intel.com ([10.123.117.78])\n by FMSMGA003.fm.intel.com with ESMTP; 16 Jun 2022 12:55:23 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1655409324; x=1686945324;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=hoWWUWpy/yp14Sf0f9Kwe21xxxGfi2isuBPrWSp7X2E=;\n b=i3lvBg4lq8UNrvxlDtxlegZGiHIok6uUvSKxoKm+Lw95hN+8JTAms/3Q\n 9DtKwipoVrgmrcBRfiG2+azxJ7O9aUUIvDnV07PQrEkLey81JH/9OXTyW\n 0IG6p2sIqTV9xUhhnDQaGZA2VsrJqFQYMlcKN+vzGW+Zabh4Ce4AvuhHW\n b/xXH1wUwXOsyrhPbosyJmUpvfEJWIXCO//ulOl99yurP4YcJ8Rt8Ckoy\n Po4FR4VHDij8oKLUTCjK/il10znntwSq1KNg9XAQcCG2CdnYMKuIM0qdW\n VbOA6lYCxUDGBVi4LJkP+rDT2Z2XrN6uBS7oclsJ16zpNwpK763pfXOnI A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10380\"; a=\"280052464\"", "E=Sophos;i=\"5.92,306,1650956400\"; d=\"scan'208\";a=\"280052464\"", "E=Sophos;i=\"5.92,306,1650956400\"; d=\"scan'208\";a=\"675171587\"" ], "X-ExtLoop1": "1", "From": "Timothy McDaniel <timothy.mcdaniel@intel.com>", "To": "jerinj@marvell.com", "Cc": "dev@dpdk.org", "Subject": "[PATCH v2 2/2] event/dlb2: add ldb port specific COS support", "Date": "Thu, 16 Jun 2022 14:55:17 -0500", "Message-Id": "<20220616195517.344509-3-timothy.mcdaniel@intel.com>", "X-Mailer": "git-send-email 2.23.0", "In-Reply-To": "<20220616195517.344509-1-timothy.mcdaniel@intel.com>", "References": "<20220616142350.322838-3-timothy.mcdaniel@intel.com>\n <20220616195517.344509-1-timothy.mcdaniel@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "DLB supports 4 class of service domains, to aid in managing the\ndevice bandwidth across ldb ports. This commit allows specifying\nwhich ldb ports will participate in the COS scheme, which class\nthey are a part of, and the specific bandwidth percentage\nassociated with each class. The cumulative bandwidth associated\nwith the 4 classes must not exceed 100%. This feature is enabled\non the command line, and will be documented in the DLB2 programmers\nguide.\n\nSigned-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>\n\n---\n\nV3: fixed a typo/bug that caused us to read beyond the end of an array\nV2: Rebased against dpdk-next-eventdev\n---\n drivers/event/dlb2/dlb2.c | 224 +++++++++++++++------\n drivers/event/dlb2/dlb2_iface.c | 3 +\n drivers/event/dlb2/dlb2_iface.h | 3 +\n drivers/event/dlb2/dlb2_priv.h | 19 +-\n drivers/event/dlb2/pf/base/dlb2_resource.c | 66 ++++++\n drivers/event/dlb2/pf/dlb2_pf.c | 21 +-\n 6 files changed, 266 insertions(+), 70 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex e1687e3d63..f3382b5d2a 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -164,6 +164,28 @@ set_cq_weight(const char *key __rte_unused,\n \treturn 0;\n }\n \n+/* override defaults with value(s) provided on command line */\n+static void\n+dlb2_init_port_cos(struct dlb2_eventdev *dlb2, int *port_cos)\n+{\n+\tint q;\n+\n+\tfor (q = 0; q < DLB2_MAX_NUM_PORTS_ALL; q++) {\n+\t\tdlb2->ev_ports[q].cos_id = port_cos[q];\n+\t\tdlb2->cos_ports[port_cos[q]]++;\n+\t}\n+}\n+\n+static void\n+dlb2_init_cos_bw(struct dlb2_eventdev *dlb2,\n+\t\t struct dlb2_cos_bw *cos_bw)\n+{\n+\tint q;\n+\tfor (q = 0; q < DLB2_COS_NUM_VALS; q++)\n+\t\tdlb2->cos_bw[q] = cos_bw->val[q];\n+\n+}\n+\n static int\n dlb2_hw_query_resources(struct dlb2_eventdev *dlb2)\n {\n@@ -379,12 +401,11 @@ set_dev_id(const char *key __rte_unused,\n }\n \n static int\n-set_cos(const char *key __rte_unused,\n+set_poll_interval(const char *key __rte_unused,\n \tconst char *value,\n \tvoid *opaque)\n {\n-\tenum dlb2_cos *cos_id = opaque;\n-\tint x = 0;\n+\tint *poll_interval = opaque;\n \tint ret;\n \n \tif (value == NULL || opaque == NULL) {\n@@ -392,38 +413,83 @@ set_cos(const char *key __rte_unused,\n \t\treturn -EINVAL;\n \t}\n \n-\tret = dlb2_string_to_int(&x, value);\n+\tret = dlb2_string_to_int(poll_interval, value);\n \tif (ret < 0)\n \t\treturn ret;\n \n-\tif (x != DLB2_COS_DEFAULT && (x < DLB2_COS_0 || x > DLB2_COS_3)) {\n-\t\tDLB2_LOG_ERR(\n-\t\t\t\"COS %d out of range, must be DLB2_COS_DEFAULT or 0-3\\n\",\n-\t\t\tx);\n+\treturn 0;\n+}\n+\n+static int\n+set_port_cos(const char *key __rte_unused,\n+\t const char *value,\n+\t void *opaque)\n+{\n+\tstruct dlb2_port_cos *port_cos = opaque;\n+\tint first, last, cos_id, i;\n+\n+\tif (value == NULL || opaque == NULL) {\n+\t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n \t\treturn -EINVAL;\n \t}\n \n-\t*cos_id = x;\n+\t/* command line override may take one of the following 3 forms:\n+\t * port_cos=all:<cos_id> ... all ports\n+\t * port_cos=port-port:<cos_id> ... a range of ports\n+\t * port_cos=port:<cos_id> ... just one port\n+\t */\n+\tif (sscanf(value, \"all:%d\", &cos_id) == 1) {\n+\t\tfirst = 0;\n+\t\tlast = DLB2_MAX_NUM_LDB_PORTS - 1;\n+\t} else if (sscanf(value, \"%d-%d:%d\", &first, &last, &cos_id) == 3) {\n+\t\t/* we have everything we need */\n+\t} else if (sscanf(value, \"%d:%d\", &first, &cos_id) == 2) {\n+\t\tlast = first;\n+\t} else {\n+\t\tDLB2_LOG_ERR(\"Error parsing ldb port port_cos devarg. Should be all:val, port-port:val, or port:val\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (first > last || first < 0 ||\n+\t\tlast >= DLB2_MAX_NUM_LDB_PORTS) {\n+\t\tDLB2_LOG_ERR(\"Error parsing ldb port cos_id arg, invalid port value\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (cos_id < DLB2_COS_0 || cos_id > DLB2_COS_3) {\n+\t\tDLB2_LOG_ERR(\"Error parsing ldb port cos_id devarg, must be between 0 and 4\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tfor (i = first; i <= last; i++)\n+\t\tport_cos->cos_id[i] = cos_id; /* indexed by port */\n \n \treturn 0;\n }\n \n static int\n-set_poll_interval(const char *key __rte_unused,\n-\tconst char *value,\n-\tvoid *opaque)\n+set_cos_bw(const char *key __rte_unused,\n+\t const char *value,\n+\t void *opaque)\n {\n-\tint *poll_interval = opaque;\n-\tint ret;\n+\tstruct dlb2_cos_bw *cos_bw = opaque;\n \n-\tif (value == NULL || opaque == NULL) {\n+\tif (opaque == NULL) {\n \t\tDLB2_LOG_ERR(\"NULL pointer\\n\");\n \t\treturn -EINVAL;\n \t}\n \n-\tret = dlb2_string_to_int(poll_interval, value);\n-\tif (ret < 0)\n-\t\treturn ret;\n+\t/* format must be %d,%d,%d,%d */\n+\n+\tif (sscanf(value, \"%d,%d,%d,%d\", &cos_bw->val[0], &cos_bw->val[1],\n+\t\t &cos_bw->val[2], &cos_bw->val[3]) != 4) {\n+\t\tDLB2_LOG_ERR(\"Error parsing cos bandwidth devarg. Should be bw0,bw1,bw2,bw3 where all values combined are <= 100\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\tif (cos_bw->val[0] + cos_bw->val[1] + cos_bw->val[2] + cos_bw->val[3] > 100) {\n+\t\tDLB2_LOG_ERR(\"Error parsing cos bandwidth devarg. Should be bw0,bw1,bw2,bw3 where all values combined are <= 100\\n\");\n+\t\treturn -EINVAL;\n+\t}\n \n \treturn 0;\n }\n@@ -653,11 +719,13 @@ dlb2_eventdev_info_get(struct rte_eventdev *dev,\n }\n \n static int\n-dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,\n+dlb2_hw_create_sched_domain(struct dlb2_eventdev *dlb2,\n+\t\t\t struct dlb2_hw_dev *handle,\n \t\t\t const struct dlb2_hw_rsrcs *resources_asked,\n \t\t\t uint8_t device_version)\n {\n \tint ret = 0;\n+\tuint32_t cos_ports = 0;\n \tstruct dlb2_create_sched_domain_args *cfg;\n \n \tif (resources_asked == NULL) {\n@@ -683,38 +751,22 @@ dlb2_hw_create_sched_domain(struct dlb2_hw_dev *handle,\n \n \t/* LDB ports */\n \n-\tcfg->cos_strict = 0; /* Best effort */\n-\tcfg->num_cos_ldb_ports[0] = 0;\n-\tcfg->num_cos_ldb_ports[1] = 0;\n-\tcfg->num_cos_ldb_ports[2] = 0;\n-\tcfg->num_cos_ldb_ports[3] = 0;\n-\n-\tswitch (handle->cos_id) {\n-\tcase DLB2_COS_0:\n-\t\tcfg->num_ldb_ports = 0; /* no don't care ports */\n-\t\tcfg->num_cos_ldb_ports[0] =\n-\t\t\tresources_asked->num_ldb_ports;\n-\t\tbreak;\n-\tcase DLB2_COS_1:\n-\t\tcfg->num_ldb_ports = 0; /* no don't care ports */\n-\t\tcfg->num_cos_ldb_ports[1] = resources_asked->num_ldb_ports;\n-\t\tbreak;\n-\tcase DLB2_COS_2:\n-\t\tcfg->num_ldb_ports = 0; /* no don't care ports */\n-\t\tcfg->num_cos_ldb_ports[2] = resources_asked->num_ldb_ports;\n-\t\tbreak;\n-\tcase DLB2_COS_3:\n-\t\tcfg->num_ldb_ports = 0; /* no don't care ports */\n-\t\tcfg->num_cos_ldb_ports[3] =\n-\t\t\tresources_asked->num_ldb_ports;\n-\t\tbreak;\n-\tcase DLB2_COS_DEFAULT:\n-\t\t/* all ldb ports are don't care ports from a cos perspective */\n-\t\tcfg->num_ldb_ports =\n-\t\t\tresources_asked->num_ldb_ports;\n-\t\tbreak;\n+\t/* tally of ports with non default COS */\n+\tcos_ports = dlb2->cos_ports[1] + dlb2->cos_ports[2] +\n+\t\t dlb2->cos_ports[3];\n+\n+\tif (cos_ports > resources_asked->num_ldb_ports) {\n+\t\tDLB2_LOG_ERR(\"dlb2: num_ldb_ports < nonzero cos_ports\\n\");\n+\t\tret = EINVAL;\n+\t\tgoto error_exit;\n \t}\n \n+\tcfg->cos_strict = 0; /* Best effort */\n+\tcfg->num_cos_ldb_ports[0] = resources_asked->num_ldb_ports - cos_ports;\n+\tcfg->num_cos_ldb_ports[1] = dlb2->cos_ports[1];\n+\tcfg->num_cos_ldb_ports[2] = dlb2->cos_ports[2];\n+\tcfg->num_cos_ldb_ports[3] = dlb2->cos_ports[3];\n+\n \tif (device_version == DLB2_HW_V2)\n \t\tcfg->num_ldb_credits = resources_asked->num_ldb_credits;\n \n@@ -892,7 +944,8 @@ dlb2_eventdev_configure(const struct rte_eventdev *dev)\n \t\t\trsrcs->num_dir_credits = dlb2->num_dir_credits_override;\n \t}\n \n-\tif (dlb2_hw_create_sched_domain(handle, rsrcs, dlb2->version) < 0) {\n+\tif (dlb2_hw_create_sched_domain(dlb2, handle, rsrcs,\n+\t\t\t\t\tdlb2->version) < 0) {\n \t\tDLB2_LOG_ERR(\"dlb2_hw_create_sched_domain failed\\n\");\n \t\treturn -ENODEV;\n \t}\n@@ -1449,12 +1502,8 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,\n \n \tcfg.cq_history_list_size = DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;\n \n-\tif (handle->cos_id == DLB2_COS_DEFAULT)\n-\t\tcfg.cos_id = 0;\n-\telse\n-\t\tcfg.cos_id = handle->cos_id;\n-\n-\tcfg.cos_strict = 0;\n+\tcfg.cos_id = ev_port->cos_id;\n+\tcfg.cos_strict = 0;/* best effots */\n \n \t/* User controls the LDB high watermark via enqueue depth. The DIR high\n \t * watermark is equal, unless the directed credit pool is too small.\n@@ -4450,7 +4499,6 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev,\n \n \tdlb2->max_num_events_override = dlb2_args->max_num_events;\n \tdlb2->num_dir_credits_override = dlb2_args->num_dir_credits_override;\n-\tdlb2->qm_instance.cos_id = dlb2_args->cos_id;\n \tdlb2->poll_interval = dlb2_args->poll_interval;\n \tdlb2->sw_credit_quanta = dlb2_args->sw_credit_quanta;\n \tdlb2->hw_credit_quanta = dlb2_args->hw_credit_quanta;\n@@ -4482,6 +4530,27 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev,\n \n \tdlb2_iface_hardware_init(&dlb2->qm_instance);\n \n+\t/* configure class of service */\n+\t{\n+\t\tstruct dlb2_set_cos_bw_args set_cos_bw_args = {0};\n+\t\tint id;\n+\t\tint ret = 0;\n+\n+\t\tfor (id = 0; id < DLB2_COS_NUM_VALS; id++) {\n+\t\t\tset_cos_bw_args.cos_id = id;\n+\t\t\tset_cos_bw_args.cos_id = dlb2->cos_bw[id];\n+\t\t\tret = dlb2_iface_set_cos_bw(&dlb2->qm_instance,\n+\t\t\t\t\t\t &set_cos_bw_args);\n+\t\t\tif (ret != 0)\n+\t\t\t\tbreak;\n+\t\t}\n+\t\tif (ret) {\n+\t\t\tDLB2_LOG_ERR(\"dlb2: failed to configure class of service, err=%d\\n\",\n+\t\t\t\t err);\n+\t\t\treturn err;\n+\t\t}\n+\t}\n+\n \terr = dlb2_iface_get_cq_poll_mode(&dlb2->qm_instance, &dlb2->poll_mode);\n \tif (err < 0) {\n \t\tDLB2_LOG_ERR(\"dlb2: failed to get the poll mode, err=%d\\n\",\n@@ -4512,6 +4581,12 @@ dlb2_primary_eventdev_probe(struct rte_eventdev *dev,\n \tdlb2_init_cq_weight(dlb2,\n \t\t\t dlb2_args->cq_weight.limit);\n \n+\tdlb2_init_port_cos(dlb2,\n+\t\t\t dlb2_args->port_cos.cos_id);\n+\n+\tdlb2_init_cos_bw(dlb2,\n+\t\t\t &dlb2_args->cos_bw);\n+\n \treturn 0;\n }\n \n@@ -4567,6 +4642,8 @@ dlb2_parse_params(const char *params,\n \t\t\t\t\t DLB2_VECTOR_OPTS_ENAB_ARG,\n \t\t\t\t\t DLB2_MAX_CQ_DEPTH,\n \t\t\t\t\t DLB2_CQ_WEIGHT,\n+\t\t\t\t\t DLB2_PORT_COS,\n+\t\t\t\t\t DLB2_COS_BW,\n \t\t\t\t\t NULL };\n \n \tif (params != NULL && params[0] != '\\0') {\n@@ -4639,16 +4716,6 @@ dlb2_parse_params(const char *params,\n \t\t\t\treturn ret;\n \t\t\t}\n \n-\t\t\tret = rte_kvargs_process(kvlist, DLB2_COS_ARG,\n-\t\t\t\t\t\t set_cos,\n-\t\t\t\t\t\t &dlb2_args->cos_id);\n-\t\t\tif (ret != 0) {\n-\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing cos parameter\",\n-\t\t\t\t\t name);\n-\t\t\t\trte_kvargs_free(kvlist);\n-\t\t\t\treturn ret;\n-\t\t\t}\n-\n \t\t\tret = rte_kvargs_process(kvlist, DLB2_POLL_INTERVAL_ARG,\n \t\t\t\t\t\t set_poll_interval,\n \t\t\t\t\t\t &dlb2_args->poll_interval);\n@@ -4724,6 +4791,29 @@ dlb2_parse_params(const char *params,\n \t\t\t\treturn ret;\n \t\t\t}\n \n+\t\t\tret = rte_kvargs_process(kvlist,\n+\t\t\t\t\tDLB2_PORT_COS,\n+\t\t\t\t\tset_port_cos,\n+\t\t\t\t\t&dlb2_args->port_cos);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing port cos\",\n+\t\t\t\t\t name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tret = rte_kvargs_process(kvlist,\n+\t\t\t\t\tDLB2_COS_BW,\n+\t\t\t\t\tset_cos_bw,\n+\t\t\t\t\t&dlb2_args->cos_bw);\n+\t\t\tif (ret != 0) {\n+\t\t\t\tDLB2_LOG_ERR(\"%s: Error parsing cos_bw\",\n+\t\t\t\t\t name);\n+\t\t\t\trte_kvargs_free(kvlist);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\n \t\t\trte_kvargs_free(kvlist);\n \t\t}\n \t}\ndiff --git a/drivers/event/dlb2/dlb2_iface.c b/drivers/event/dlb2/dlb2_iface.c\nindex b77faa967c..100db434d0 100644\n--- a/drivers/event/dlb2/dlb2_iface.c\n+++ b/drivers/event/dlb2/dlb2_iface.c\n@@ -76,3 +76,6 @@ int (*dlb2_iface_get_dir_queue_depth)(struct dlb2_hw_dev *handle,\n \n int (*dlb2_iface_enable_cq_weight)(struct dlb2_hw_dev *handle,\n \t\t\t\t struct dlb2_enable_cq_weight_args *args);\n+\n+int (*dlb2_iface_set_cos_bw)(struct dlb2_hw_dev *handle,\n+\t\t\t struct dlb2_set_cos_bw_args *args);\ndiff --git a/drivers/event/dlb2/dlb2_iface.h b/drivers/event/dlb2/dlb2_iface.h\nindex fef717392f..dc0c446ce8 100644\n--- a/drivers/event/dlb2/dlb2_iface.h\n+++ b/drivers/event/dlb2/dlb2_iface.h\n@@ -76,4 +76,7 @@ extern int (*dlb2_iface_get_dir_queue_depth)(struct dlb2_hw_dev *handle,\n extern int (*dlb2_iface_enable_cq_weight)(struct dlb2_hw_dev *handle,\n \t\t\t\t\t struct dlb2_enable_cq_weight_args *args);\n \n+extern int (*dlb2_iface_set_cos_bw)(struct dlb2_hw_dev *handle,\n+\t\t\t\t struct dlb2_set_cos_bw_args *args);\n+\n #endif /* _DLB2_IFACE_H_ */\ndiff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nindex 63b092fc47..528e2ede61 100644\n--- a/drivers/event/dlb2/dlb2_priv.h\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -45,6 +45,8 @@\n #define DLB2_VECTOR_OPTS_ENAB_ARG \"vector_opts_enable\"\n #define DLB2_MAX_CQ_DEPTH \"max_cq_depth\"\n #define DLB2_CQ_WEIGHT \"cq_weight\"\n+#define DLB2_PORT_COS \"port_cos\"\n+#define DLB2_COS_BW \"cos_bw\"\n \n /* Begin HW related defines and structs */\n \n@@ -416,7 +418,8 @@ enum dlb2_cos {\n \tDLB2_COS_0 = 0,\n \tDLB2_COS_1,\n \tDLB2_COS_2,\n-\tDLB2_COS_3\n+\tDLB2_COS_3,\n+\tDLB2_COS_NUM_VALS\n };\n \n struct dlb2_hw_dev {\n@@ -424,7 +427,6 @@ struct dlb2_hw_dev {\n \tstruct dlb2_hw_resource_info info;\n \tvoid *pf_dev; /* opaque pointer to PF PMD dev (struct dlb2_dev) */\n \tuint32_t domain_id;\n-\tenum dlb2_cos cos_id;\n \trte_spinlock_t resource_lock; /* for MP support */\n } __rte_cache_aligned;\n \n@@ -529,6 +531,7 @@ struct dlb2_eventdev_port {\n \tbool enq_configured;\n \tuint8_t implicit_release; /* release events before dequeuing */\n \tuint32_t cq_weight; /* DLB2.5 and above ldb ports only */\n+\tint cos_id; /*ldb port class of service */\n } __rte_cache_aligned;\n \n struct dlb2_queue {\n@@ -623,6 +626,8 @@ struct dlb2_eventdev {\n \t\t\tuint32_t credit_pool __rte_cache_aligned;\n \t\t};\n \t};\n+\tuint32_t cos_ports[DLB2_COS_NUM_VALS]; /* total ldb ports in each class */\n+\tuint32_t cos_bw[DLB2_COS_NUM_VALS]; /* bandwidth per cos domain */\n };\n \n /* used for collecting and passing around the dev args */\n@@ -634,6 +639,14 @@ struct dlb2_cq_weight {\n \tint limit[DLB2_MAX_NUM_LDB_PORTS];\n };\n \n+struct dlb2_port_cos {\n+\tint cos_id[DLB2_MAX_NUM_LDB_PORTS];\n+};\n+\n+struct dlb2_cos_bw {\n+\tint val[DLB2_COS_NUM_VALS];\n+};\n+\n struct dlb2_devargs {\n \tint socket_id;\n \tint max_num_events;\n@@ -648,6 +661,8 @@ struct dlb2_devargs {\n \tbool vector_opts_enabled;\n \tint max_cq_depth;\n \tstruct dlb2_cq_weight cq_weight;\n+\tstruct dlb2_port_cos port_cos;\n+\tstruct dlb2_cos_bw cos_bw;\n };\n \n /* End Eventdev related defines and structs */\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex e52a896bad..d4471de5a0 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -6493,3 +6493,69 @@ int dlb2_hw_enable_cq_weight(struct dlb2_hw *hw,\n \n \treturn 0;\n }\n+\n+static void dlb2_log_set_cos_bandwidth(struct dlb2_hw *hw, u32 cos_id, u8 bw)\n+{\n+\tDLB2_HW_DBG(hw, \"DLB2 set port CoS bandwidth:\\n\");\n+\tDLB2_HW_DBG(hw, \"\\tCoS ID: %u\\n\", cos_id);\n+\tDLB2_HW_DBG(hw, \"\\tBandwidth: %u\\n\", bw);\n+}\n+\n+#define DLB2_MAX_BW_PCT 100\n+\n+/**\n+ * dlb2_hw_set_cos_bandwidth() - set a bandwidth allocation percentage for a\n+ * port class-of-service.\n+ * @hw: dlb2_hw handle for a particular device.\n+ * @cos_id: class-of-service ID.\n+ * @bandwidth: class-of-service bandwidth.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise.\n+ *\n+ * Errors:\n+ * EINVAL - Invalid cos ID, bandwidth is greater than 100, or bandwidth would\n+ * cause the total bandwidth across all classes of service to exceed\n+ * 100%.\n+ */\n+int dlb2_hw_set_cos_bandwidth(struct dlb2_hw *hw, u32 cos_id, u8 bandwidth)\n+{\n+\tunsigned int i;\n+\tu32 reg;\n+\tu8 total;\n+\n+\tif (cos_id >= DLB2_NUM_COS_DOMAINS)\n+\t\treturn -EINVAL;\n+\n+\tif (bandwidth > DLB2_MAX_BW_PCT)\n+\t\treturn -EINVAL;\n+\n+\ttotal = 0;\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++)\n+\t\ttotal += (i == cos_id) ? bandwidth : hw->cos_reservation[i];\n+\n+\tif (total > DLB2_MAX_BW_PCT)\n+\t\treturn -EINVAL;\n+\n+\treg = DLB2_CSR_RD(hw, DLB2_LSP_CFG_SHDW_RANGE_COS(hw->ver, cos_id));\n+\n+\t/*\n+\t * Normalize the bandwidth to a value in the range 0-255. Integer\n+\t * division may leave unreserved scheduling slots; these will be\n+\t * divided among the 4 classes of service.\n+\t */\n+\tDLB2_BITS_SET(reg, (bandwidth * 256) / 100, DLB2_LSP_CFG_SHDW_RANGE_COS_BW_RANGE);\n+\tDLB2_CSR_WR(hw, DLB2_LSP_CFG_SHDW_RANGE_COS(hw->ver, cos_id), reg);\n+\n+\treg = 0;\n+\tDLB2_BIT_SET(reg, DLB2_LSP_CFG_SHDW_CTRL_TRANSFER);\n+\t/* Atomically transfer the newly configured service weight */\n+\tDLB2_CSR_WR(hw, DLB2_LSP_CFG_SHDW_CTRL(hw->ver), reg);\n+\n+\tdlb2_log_set_cos_bandwidth(hw, cos_id, bandwidth);\n+\n+\thw->cos_reservation[cos_id] = bandwidth;\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c\nindex 1d0415e46f..0627f06a6e 100644\n--- a/drivers/event/dlb2/pf/dlb2_pf.c\n+++ b/drivers/event/dlb2/pf/dlb2_pf.c\n@@ -646,6 +646,25 @@ dlb2_pf_enable_cq_weight(struct dlb2_hw_dev *handle,\n \treturn ret;\n }\n \n+static int\n+dlb2_pf_set_cos_bandwidth(struct dlb2_hw_dev *handle,\n+\t\t\t struct dlb2_set_cos_bw_args *args)\n+{\n+\tstruct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;\n+\tint ret = 0;\n+\n+\tDLB2_INFO(dev->dlb2_device, \"Entering %s()\\n\", __func__);\n+\n+\tret = dlb2_hw_set_cos_bandwidth(&dlb2_dev->hw,\n+\t\t\t\t\targs->cos_id,\n+\t\t\t\t\targs->bandwidth);\n+\n+\tDLB2_INFO(dev->dlb2_device, \"Exiting %s() with ret=%d\\n\",\n+\t\t __func__, ret);\n+\n+\treturn ret;\n+}\n+\n static void\n dlb2_pf_iface_fn_ptrs_init(void)\n {\n@@ -671,6 +690,7 @@ dlb2_pf_iface_fn_ptrs_init(void)\n \tdlb2_iface_set_sn_allocation = dlb2_pf_set_sn_allocation;\n \tdlb2_iface_get_sn_occupancy = dlb2_pf_get_sn_occupancy;\n \tdlb2_iface_enable_cq_weight = dlb2_pf_enable_cq_weight;\n+\tdlb2_iface_set_cos_bw = dlb2_pf_set_cos_bandwidth;\n }\n \n /* PCI DEV HOOKS */\n@@ -684,7 +704,6 @@ dlb2_eventdev_pci_init(struct rte_eventdev *eventdev)\n \t\t.max_num_events = DLB2_MAX_NUM_LDB_CREDITS,\n \t\t.num_dir_credits_override = -1,\n \t\t.qid_depth_thresholds = { {0} },\n-\t\t.cos_id = DLB2_COS_DEFAULT,\n \t\t.poll_interval = DLB2_POLL_INTERVAL_DEFAULT,\n \t\t.sw_credit_quanta = DLB2_SW_CREDIT_QUANTA_DEFAULT,\n \t\t.hw_credit_quanta = DLB2_SW_CREDIT_BATCH_SZ,\n", "prefixes": [ "v2", "2/2" ] }