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GET /api/patches/112843/?format=api
{ "id": 112843, "url": "http://patches.dpdk.org/api/patches/112843/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220616070743.30658-8-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220616070743.30658-8-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220616070743.30658-8-ndabilpuram@marvell.com", "date": "2022-06-16T07:07:39", "name": "[08/12] net/cnxk: remove restriction on VFs for PFC config", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "bd2200fd4f4abf9e4bbb625601bd8837a8681426", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220616070743.30658-8-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 23552, "url": "http://patches.dpdk.org/api/series/23552/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23552", "date": "2022-06-16T07:07:32", "name": "[01/12] common/cnxk: use computed value for wqe skip", "version": 1, "mbox": "http://patches.dpdk.org/series/23552/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/112843/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/112843/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 080C7A00C3;\n\tThu, 16 Jun 2022 09:10:31 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 681D242BFF;\n\tThu, 16 Jun 2022 09:10:14 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id D278A42BF1\n for <dev@dpdk.org>; Thu, 16 Jun 2022 09:10:10 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 25G2AMm3013083\n for <dev@dpdk.org>; Thu, 16 Jun 2022 00:10:10 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3gq83yx522-8\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 16 Jun 2022 00:10:09 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 16 Jun 2022 00:09:52 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Thu, 16 Jun 2022 00:09:52 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 863BF3F709B;\n Thu, 16 Jun 2022 00:09:50 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=FEcRracprF4exZpT4zj0cFqptmsby+O2HlJ4DphCcZE=;\n b=FyBICcXfMfmtslttwRnrD68qDfdkVbhpapQDps8PZbkp75DxGSnufqPJt5dr+nfHpjXH\n rVcnpPXmOcJiBZjTUguOwJKstgkAXE39C5GIiGpoqIgCZAB19rdmG0FHgHOjieLEiPTa\n p/aPIFLL3tWesXx+xSljr/ihwSn7tiX7H6ptXtbyOQ5ljgGCi3/DkW2WhAuvNsYI9XFm\n SltjfA4p2H9TNNz9r5cB5B94hp0Lnl+DL9ccKfGS4utV4V5k5P4RMVKwmsr6EH1C1+hb\n i329Z3FK6KZOdCFos2CL/aWC2p5vSVpvgV2aP8wo6ijoo+TuxKnB2Wf7Yw2zCbdY1AdI mw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 08/12] net/cnxk: remove restriction on VFs for PFC config", "Date": "Thu, 16 Jun 2022 12:37:39 +0530", "Message-ID": "<20220616070743.30658-8-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220616070743.30658-1-ndabilpuram@marvell.com>", "References": "<20220616070743.30658-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "ZMwzLpU3KJ5s5s2FpOhMattl6NJfJ8H9", "X-Proofpoint-GUID": "ZMwzLpU3KJ5s5s2FpOhMattl6NJfJ8H9", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.517,FMLib:17.11.64.514\n definitions=2022-06-16_03,2022-06-15_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Sunil Kumar Kori <skori@marvell.com>\n\nCurrently PFC configuration is not allowed on VFs.\nPatch enables PFC configuration on VFs\n\nSigned-off-by: Sunil Kumar Kori <skori@marvell.com>\n---\n drivers/net/cnxk/cnxk_ethdev.c | 9 +-\n drivers/net/cnxk/cnxk_ethdev.h | 13 +--\n drivers/net/cnxk/cnxk_ethdev_ops.c | 219 +++++++++++++++++++++----------------\n 3 files changed, 137 insertions(+), 104 deletions(-)", "diff": "diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 09e5736..941b270 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -323,7 +323,7 @@ nix_init_flow_ctrl_config(struct rte_eth_dev *eth_dev)\n \tstruct cnxk_fc_cfg *fc = &dev->fc_cfg;\n \tint rc;\n \n-\tif (roc_nix_is_sdp(&dev->nix))\n+\tif (roc_nix_is_vf_or_sdp(&dev->nix))\n \t\treturn 0;\n \n \t/* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */\n@@ -604,6 +604,9 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \trxq_sp->qconf.conf.rx.offloads = dev->rx_offloads;\n \trxq_sp->qconf.nb_desc = nb_desc;\n \trxq_sp->qconf.mp = mp;\n+\trxq_sp->tc = 0;\n+\trxq_sp->tx_pause = (dev->fc_cfg.mode == RTE_ETH_FC_FULL ||\n+\t\t\t dev->fc_cfg.mode == RTE_ETH_FC_TX_PAUSE);\n \n \tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY) {\n \t\t/* Pass a tagmask used to handle error packets in inline device.\n@@ -1795,7 +1798,6 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)\n \t\tif (dev->pfc_tc_sq_map[i] != 0xFFFF) {\n \t\t\tpfc_conf.rx_pause.tx_qid = dev->pfc_tc_sq_map[i];\n \t\t\tpfc_conf.rx_pause.tc = i;\n-\t\t\tpfc_conf.tx_pause.rx_qid = i;\n \t\t\tpfc_conf.tx_pause.tc = i;\n \t\t\trc = cnxk_nix_priority_flow_ctrl_queue_config(eth_dev,\n \t\t\t\t&pfc_conf);\n@@ -1805,9 +1807,6 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool reset)\n \t\t}\n \t}\n \n-\tfc_conf.mode = RTE_ETH_FC_FULL;\n-\trc = cnxk_nix_flow_ctrl_set(eth_dev, &fc_conf);\n-\n \t/* Disable and free rte_meter entries */\n \tnix_meter_fini(dev);\n \ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 0400d73..db2d849 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -156,13 +156,10 @@ struct cnxk_fc_cfg {\n };\n \n struct cnxk_pfc_cfg {\n-\tstruct cnxk_fc_cfg fc_cfg;\n \tuint16_t class_en;\n \tuint16_t pause_time;\n-\tuint8_t rx_tc;\n-\tuint8_t rx_qid;\n-\tuint8_t tx_tc;\n-\tuint8_t tx_qid;\n+\tuint16_t rx_pause_en;\n+\tuint16_t tx_pause_en;\n };\n \n struct cnxk_eth_qconf {\n@@ -669,8 +666,10 @@ int nix_mtr_color_action_validate(struct rte_eth_dev *eth_dev, uint32_t id,\n \t\t\t\t uint32_t *prev_id, uint32_t *next_id,\n \t\t\t\t struct cnxk_mtr_policy_node *policy,\n \t\t\t\t int *tree_level);\n-int nix_priority_flow_ctrl_configure(struct rte_eth_dev *eth_dev,\n-\t\t\t\t struct cnxk_pfc_cfg *conf);\n+int nix_priority_flow_ctrl_rq_conf(struct rte_eth_dev *eth_dev, uint16_t qid,\n+\t\t\t\t uint8_t tx_pause, uint8_t tc);\n+int nix_priority_flow_ctrl_sq_conf(struct rte_eth_dev *eth_dev, uint16_t qid,\n+\t\t\t\t uint8_t rx_pause, uint8_t tc);\n \n /* Inlines */\n static __rte_always_inline uint64_t\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_ops.c b/drivers/net/cnxk/cnxk_ethdev_ops.c\nindex 15d8e8e..caace9d 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_ops.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_ops.c\n@@ -225,15 +225,17 @@ nix_fc_cq_config_set(struct cnxk_eth_dev *dev, uint16_t qid, bool enable)\n \tstruct roc_nix *nix = &dev->nix;\n \tstruct roc_nix_fc_cfg fc_cfg;\n \tstruct roc_nix_cq *cq;\n+\tstruct roc_nix_rq *rq;\n \n \tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n+\trq = &dev->rqs[qid];\n \tcq = &dev->cqs[qid];\n-\tfc_cfg.type = ROC_NIX_FC_CQ_CFG;\n-\tfc_cfg.cq_cfg.enable = enable;\n-\t/* Map all CQs to last channel */\n-\tfc_cfg.cq_cfg.tc = roc_nix_chan_count_get(nix) - 1;\n-\tfc_cfg.cq_cfg.rq = qid;\n-\tfc_cfg.cq_cfg.cq_drop = cq->drop_thresh;\n+\tfc_cfg.type = ROC_NIX_FC_RQ_CFG;\n+\tfc_cfg.rq_cfg.enable = enable;\n+\tfc_cfg.rq_cfg.tc = 0;\n+\tfc_cfg.rq_cfg.rq = qid;\n+\tfc_cfg.rq_cfg.pool = rq->aura_handle;\n+\tfc_cfg.rq_cfg.cq_drop = cq->drop_thresh;\n \n \treturn roc_nix_fc_config_set(nix, &fc_cfg);\n }\n@@ -255,10 +257,8 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n \tuint8_t rx_pause, tx_pause;\n \tint rc, i;\n \n-\tif (roc_nix_is_vf_or_sdp(nix) && !roc_nix_is_lbk(nix)) {\n-\t\tplt_err(\"Flow control configuration is not allowed on VFs\");\n-\t\treturn -ENOTSUP;\n-\t}\n+\tif (roc_nix_is_sdp(nix))\n+\t\treturn 0;\n \n \tif (fc_conf->high_water || fc_conf->low_water || fc_conf->pause_time ||\n \t fc_conf->mac_ctrl_frame_fwd || fc_conf->autoneg) {\n@@ -266,14 +266,18 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n \t\treturn -EINVAL;\n \t}\n \n-\tif (fc_conf->mode == fc->mode)\n-\t\treturn 0;\n \n \trx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) ||\n \t\t (fc_conf->mode == RTE_ETH_FC_RX_PAUSE);\n \ttx_pause = (fc_conf->mode == RTE_ETH_FC_FULL) ||\n \t\t (fc_conf->mode == RTE_ETH_FC_TX_PAUSE);\n \n+\tif (fc_conf->mode == fc->mode) {\n+\t\tfc->rx_pause = rx_pause;\n+\t\tfc->tx_pause = tx_pause;\n+\t\treturn 0;\n+\t}\n+\n \t/* Check if TX pause frame is already enabled or not */\n \tif (fc->tx_pause ^ tx_pause) {\n \t\tif (roc_model_is_cn96_ax() && data->dev_started) {\n@@ -291,6 +295,7 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n \t\t\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n \t\t\trxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[i]) -\n \t\t\t 1;\n+\t\t\trxq->tx_pause = !!tx_pause;\n \t\t\trc = nix_fc_cq_config_set(dev, rxq->qid, !!tx_pause);\n \t\t\tif (rc)\n \t\t\t\treturn rc;\n@@ -321,13 +326,12 @@ cnxk_nix_flow_ctrl_set(struct rte_eth_dev *eth_dev,\n \tfc->rx_pause = rx_pause;\n \tfc->tx_pause = tx_pause;\n \tfc->mode = fc_conf->mode;\n-\n \treturn rc;\n }\n \n int\n cnxk_nix_priority_flow_ctrl_queue_info_get(struct rte_eth_dev *eth_dev,\n-\t\t\t\t\t struct rte_eth_pfc_queue_info *pfc_info)\n+\t\t\t\tstruct rte_eth_pfc_queue_info *pfc_info)\n {\n \tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n \n@@ -338,25 +342,42 @@ cnxk_nix_priority_flow_ctrl_queue_info_get(struct rte_eth_dev *eth_dev,\n \n int\n cnxk_nix_priority_flow_ctrl_queue_config(struct rte_eth_dev *eth_dev,\n-\t\t\t\t\t struct rte_eth_pfc_queue_conf *pfc_conf)\n+\t\t\t\t struct rte_eth_pfc_queue_conf *pfc_conf)\n {\n-\tstruct cnxk_pfc_cfg conf;\n-\tint rc;\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct roc_nix *nix = &dev->nix;\n+\tenum rte_eth_fc_mode mode;\n+\tuint8_t en, tc;\n+\tuint16_t qid;\n+\tint rc = 0;\n \n-\tmemset(&conf, 0, sizeof(struct cnxk_pfc_cfg));\n+\tif (dev->fc_cfg.mode != RTE_ETH_FC_NONE) {\n+\t\tplt_err(\"Disable Flow Control before configuring PFC\");\n+\t\treturn -ENOTSUP;\n+\t}\n \n-\tconf.fc_cfg.mode = pfc_conf->mode;\n+\tif (roc_nix_is_sdp(nix)) {\n+\t\tplt_err(\"Prio flow ctrl config is not allowed on SDP\");\n+\t\treturn -ENOTSUP;\n+\t}\n \n-\tconf.pause_time = pfc_conf->tx_pause.pause_time;\n-\tconf.rx_tc = pfc_conf->tx_pause.tc;\n-\tconf.rx_qid = pfc_conf->tx_pause.rx_qid;\n+\tmode = pfc_conf->mode;\n \n-\tconf.tx_tc = pfc_conf->rx_pause.tc;\n-\tconf.tx_qid = pfc_conf->rx_pause.tx_qid;\n+\t/* Perform Tx pause configuration on RQ */\n+\tqid = pfc_conf->tx_pause.rx_qid;\n+\tif (qid < eth_dev->data->nb_rx_queues) {\n+\t\ten = (mode == RTE_ETH_FC_FULL) || (mode == RTE_ETH_FC_TX_PAUSE);\n+\t\ttc = pfc_conf->tx_pause.tc;\n+\t\trc = nix_priority_flow_ctrl_rq_conf(eth_dev, qid, en, tc);\n+\t}\n \n-\trc = nix_priority_flow_ctrl_configure(eth_dev, &conf);\n-\tif (rc)\n-\t\treturn rc;\n+\t/* Perform Rx pause configuration on SQ */\n+\tqid = pfc_conf->rx_pause.tx_qid;\n+\tif (qid < eth_dev->data->nb_tx_queues) {\n+\t\ten = (mode == RTE_ETH_FC_FULL) || (mode == RTE_ETH_FC_RX_PAUSE);\n+\t\ttc = pfc_conf->rx_pause.tc;\n+\t\trc |= nix_priority_flow_ctrl_sq_conf(eth_dev, qid, en, tc);\n+\t}\n \n \treturn rc;\n }\n@@ -1026,11 +1047,9 @@ cnxk_nix_mc_addr_list_configure(struct rte_eth_dev *eth_dev,\n }\n \n int\n-nix_priority_flow_ctrl_configure(struct rte_eth_dev *eth_dev,\n-\t\t\t\t struct cnxk_pfc_cfg *conf)\n+nix_priority_flow_ctrl_rq_conf(struct rte_eth_dev *eth_dev, uint16_t qid,\n+\t\t\t uint8_t tx_pause, uint8_t tc)\n {\n-\tenum roc_nix_fc_mode mode_map[] = {ROC_NIX_FC_NONE, ROC_NIX_FC_RX,\n-\t\t\t\t\t ROC_NIX_FC_TX, ROC_NIX_FC_FULL};\n \tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n \tstruct rte_eth_dev_data *data = eth_dev->data;\n \tstruct cnxk_pfc_cfg *pfc = &dev->pfc_cfg;\n@@ -1038,18 +1057,11 @@ nix_priority_flow_ctrl_configure(struct rte_eth_dev *eth_dev,\n \tstruct roc_nix_pfc_cfg pfc_cfg;\n \tstruct roc_nix_fc_cfg fc_cfg;\n \tstruct cnxk_eth_rxq_sp *rxq;\n-\tstruct cnxk_eth_txq_sp *txq;\n-\tuint8_t rx_pause, tx_pause;\n-\tenum rte_eth_fc_mode mode;\n+\tenum roc_nix_fc_mode mode;\n+\tstruct roc_nix_rq *rq;\n \tstruct roc_nix_cq *cq;\n-\tstruct roc_nix_sq *sq;\n \tint rc;\n \n-\tif (roc_nix_is_vf_or_sdp(nix)) {\n-\t\tplt_err(\"Prio flow ctrl config is not allowed on VF and SDP\");\n-\t\treturn -ENOTSUP;\n-\t}\n-\n \tif (roc_model_is_cn96_ax() && data->dev_started) {\n \t\t/* On Ax, CQ should be in disabled state\n \t\t * while setting flow control configuration.\n@@ -1059,39 +1071,83 @@ nix_priority_flow_ctrl_configure(struct rte_eth_dev *eth_dev,\n \t\treturn 0;\n \t}\n \n-\tif (dev->pfc_tc_sq_map[conf->tx_tc] != 0xFFFF &&\n-\t dev->pfc_tc_sq_map[conf->tx_tc] != conf->tx_qid) {\n+\tif (data->rx_queues == NULL)\n+\t\treturn -EINVAL;\n+\n+\tif (qid >= eth_dev->data->nb_rx_queues)\n+\t\treturn -ENOTSUP;\n+\n+\t/* Configure RQ */\n+\trxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[qid]) - 1;\n+\trq = &dev->rqs[qid];\n+\tcq = &dev->cqs[qid];\n+\n+\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n+\tfc_cfg.type = ROC_NIX_FC_RQ_CFG;\n+\tfc_cfg.rq_cfg.tc = tc;\n+\tfc_cfg.rq_cfg.enable = !!tx_pause;\n+\tfc_cfg.rq_cfg.rq = rq->qid;\n+\tfc_cfg.rq_cfg.pool = rxq->qconf.mp->pool_id;\n+\tfc_cfg.rq_cfg.cq_drop = cq->drop_thresh;\n+\trc = roc_nix_fc_config_set(nix, &fc_cfg);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (rxq->tx_pause != tx_pause) {\n+\t\tif (tx_pause)\n+\t\t\tpfc->tx_pause_en++;\n+\t\telse\n+\t\t\tpfc->tx_pause_en--;\n+\t}\n+\n+\trxq->tx_pause = !!tx_pause;\n+\trxq->tc = tc;\n+\n+\t/* Skip if PFC already enabled in mac */\n+\tif (pfc->tx_pause_en > 1)\n+\t\treturn 0;\n+\n+\t/* Configure MAC block */\n+\tpfc->class_en = pfc->tx_pause_en ? 0xFF : 0x0;\n+\n+\tif (pfc->rx_pause_en)\n+\t\tmode = pfc->tx_pause_en ? ROC_NIX_FC_FULL : ROC_NIX_FC_RX;\n+\telse\n+\t\tmode = pfc->tx_pause_en ? ROC_NIX_FC_TX : ROC_NIX_FC_NONE;\n+\n+\tmemset(&pfc_cfg, 0, sizeof(struct roc_nix_pfc_cfg));\n+\tpfc_cfg.mode = mode;\n+\tpfc_cfg.tc = pfc->class_en;\n+\treturn roc_nix_pfc_mode_set(nix, &pfc_cfg);\n+}\n+\n+int\n+nix_priority_flow_ctrl_sq_conf(struct rte_eth_dev *eth_dev, uint16_t qid,\n+\t\t\t uint8_t rx_pause, uint8_t tc)\n+{\n+\tstruct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);\n+\tstruct rte_eth_dev_data *data = eth_dev->data;\n+\tstruct cnxk_pfc_cfg *pfc = &dev->pfc_cfg;\n+\tstruct roc_nix *nix = &dev->nix;\n+\tstruct roc_nix_fc_cfg fc_cfg;\n+\tstruct cnxk_eth_txq_sp *txq;\n+\tstruct roc_nix_sq *sq;\n+\tint rc;\n+\n+\tif (data->tx_queues == NULL)\n+\t\treturn -EINVAL;\n+\n+\tif (qid >= eth_dev->data->nb_tx_queues)\n+\t\treturn -ENOTSUP;\n+\n+\tif (dev->pfc_tc_sq_map[tc] != 0xFFFF &&\n+\t dev->pfc_tc_sq_map[tc] != qid) {\n \t\tplt_err(\"Same TC can not be configured on multiple SQs\");\n \t\treturn -ENOTSUP;\n \t}\n \n-\tmode = conf->fc_cfg.mode;\n-\trx_pause = (mode == RTE_ETH_FC_FULL) || (mode == RTE_ETH_FC_RX_PAUSE);\n-\ttx_pause = (mode == RTE_ETH_FC_FULL) || (mode == RTE_ETH_FC_TX_PAUSE);\n-\n-\tif (data->rx_queues == NULL || data->tx_queues == NULL) {\n-\t\trc = 0;\n-\t\tgoto exit;\n-\t}\n-\n-\t/* Configure CQs */\n-\tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n-\trxq = ((struct cnxk_eth_rxq_sp *)data->rx_queues[conf->rx_qid]) - 1;\n-\tcq = &dev->cqs[rxq->qid];\n-\tfc_cfg.type = ROC_NIX_FC_CQ_CFG;\n-\tfc_cfg.cq_cfg.tc = conf->rx_tc;\n-\tfc_cfg.cq_cfg.enable = !!tx_pause;\n-\tfc_cfg.cq_cfg.rq = cq->qid;\n-\tfc_cfg.cq_cfg.cq_drop = cq->drop_thresh;\n-\trc = roc_nix_fc_config_set(nix, &fc_cfg);\n-\tif (rc)\n-\t\tgoto exit;\n-\n \t/* Check if RX pause frame is enabled or not */\n-\tif (pfc->fc_cfg.rx_pause ^ rx_pause) {\n-\t\tif (conf->tx_qid >= eth_dev->data->nb_tx_queues)\n-\t\t\tgoto exit;\n-\n+\tif (!pfc->rx_pause_en) {\n \t\tif ((roc_nix_tm_tree_type_get(nix) == ROC_NIX_TM_DEFAULT) &&\n \t\t eth_dev->data->nb_tx_queues > 1) {\n \t\t\t/*\n@@ -1113,39 +1169,18 @@ nix_priority_flow_ctrl_configure(struct rte_eth_dev *eth_dev,\n \t\t}\n \t}\n \n-\ttxq = ((struct cnxk_eth_txq_sp *)data->tx_queues[conf->tx_qid]) - 1;\n+\ttxq = ((struct cnxk_eth_txq_sp *)data->tx_queues[qid]) - 1;\n \tsq = &dev->sqs[txq->qid];\n \tmemset(&fc_cfg, 0, sizeof(struct roc_nix_fc_cfg));\n \tfc_cfg.type = ROC_NIX_FC_TM_CFG;\n \tfc_cfg.tm_cfg.sq = sq->qid;\n-\tfc_cfg.tm_cfg.tc = conf->tx_tc;\n+\tfc_cfg.tm_cfg.tc = tc;\n \tfc_cfg.tm_cfg.enable = !!rx_pause;\n \trc = roc_nix_fc_config_set(nix, &fc_cfg);\n \tif (rc)\n \t\treturn rc;\n \n-\tdev->pfc_tc_sq_map[conf->tx_tc] = sq->qid;\n-\n-\t/* Configure MAC block */\n-\tif (tx_pause)\n-\t\tpfc->class_en |= BIT(conf->rx_tc);\n-\telse\n-\t\tpfc->class_en &= ~BIT(conf->rx_tc);\n-\n-\tif (pfc->class_en)\n-\t\tmode = RTE_ETH_FC_FULL;\n-\n-\tmemset(&pfc_cfg, 0, sizeof(struct roc_nix_pfc_cfg));\n-\tpfc_cfg.mode = mode_map[mode];\n-\tpfc_cfg.tc = pfc->class_en;\n-\trc = roc_nix_pfc_mode_set(nix, &pfc_cfg);\n-\tif (rc)\n-\t\treturn rc;\n-\n-\tpfc->fc_cfg.rx_pause = rx_pause;\n-\tpfc->fc_cfg.tx_pause = tx_pause;\n-\tpfc->fc_cfg.mode = mode;\n-\n+\tdev->pfc_tc_sq_map[tc] = sq->qid;\n exit:\n \treturn rc;\n }\n", "prefixes": [ "08/12" ] }