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GET /api/patches/112831/?format=api
{ "id": 112831, "url": "http://patches.dpdk.org/api/patches/112831/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1655348434-7096-5-git-send-email-wei.huang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1655348434-7096-5-git-send-email-wei.huang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1655348434-7096-5-git-send-email-wei.huang@intel.com", "date": "2022-06-16T03:00:33", "name": "[v8,4/5] raw/ifpga: add HE-MEM AFU driver", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "8eaae4132c370c7124401de92307150e97df36b6", "submitter": { "id": 2033, "url": "http://patches.dpdk.org/api/people/2033/?format=api", "name": "Wei Huang", "email": "wei.huang@intel.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1655348434-7096-5-git-send-email-wei.huang@intel.com/mbox/", "series": [ { "id": 23549, "url": "http://patches.dpdk.org/api/series/23549/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23549", "date": "2022-06-16T03:00:29", "name": "introduce AFU PMD driver of FPGA", "version": 8, "mbox": "http://patches.dpdk.org/series/23549/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/112831/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/112831/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9A0CAA0547;\n\tThu, 16 Jun 2022 04:53:17 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 913D042BF3;\n\tThu, 16 Jun 2022 04:52:58 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n by mails.dpdk.org (Postfix) with ESMTP id BDD4542BC4;\n Thu, 16 Jun 2022 04:52:56 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 15 Jun 2022 19:52:56 -0700", "from unknown (HELO zj-fpga-amt.sh.intel.com) ([10.238.175.102])\n by FMSMGA003.fm.intel.com with ESMTP; 15 Jun 2022 19:52:54 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1655347977; x=1686883977;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=SStILsGWZ+4U4nkdtDlsHlZXSCcV2r5/CYLx88kDKMQ=;\n b=MpL/oilo+nv6biPen6YzNqMO1hjKfH8CVYj1+Q/3B60urw+5KaF65w42\n LcP8YLJLAZiWhF2y//2KAfTgmr/xNQZLm5ZzP8etbIWhKAmbyMJKnQB1h\n KJTtMBSUyxMvNf+gG59iSBPJOOx5vfAEYWaMYCHewm1AyyNN1uiwoJtlx\n k4D5csSbLGnfRlcnsVKsXpMAg3s9S2bbQEgYDmP3nNPfikqx2+8vE3xZR\n hDLlIcIEJoXRId9CyGsKCwEVeGQKzp15Zm2DGm6BxV7AFbPRePmadmIOO\n ekjRW2BMWAkAUdJkVoI8xhzLGh83FgY9s+6YsxJUxVcwcONqZmiykNYat A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10379\"; a=\"276725743\"", "E=Sophos;i=\"5.91,302,1647327600\"; d=\"scan'208\";a=\"276725743\"", "E=Sophos;i=\"5.91,302,1647327600\"; d=\"scan'208\";a=\"674824709\"" ], "X-ExtLoop1": "1", "From": "Wei Huang <wei.huang@intel.com>", "To": "dev@dpdk.org, thomas@monjalon.net, nipun.gupta@nxp.com,\n hemant.agrawal@nxp.com", "Cc": "stable@dpdk.org, rosen.xu@intel.com, tianfei.zhang@intel.com,\n qi.z.zhang@intel.com, Wei Huang <wei.huang@intel.com>", "Subject": "[PATCH v8 4/5] raw/ifpga: add HE-MEM AFU driver", "Date": "Wed, 15 Jun 2022 23:00:33 -0400", "Message-Id": "<1655348434-7096-5-git-send-email-wei.huang@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1655348434-7096-1-git-send-email-wei.huang@intel.com>", "References": "<1654760242-7832-1-git-send-email-wei.huang@intel.com>\n <1655348434-7096-1-git-send-email-wei.huang@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "HE-MEM is one of the host exerciser modules in OFS FPGA,\nwhich is used to test local memory with built-in traffic\ngenerator.\nThis driver initialize the module and report test result.\n\nSigned-off-by: Wei Huang <wei.huang@intel.com>\nAcked-by: Tianfei Zhang <tianfei.zhang@intel.com>\nReviewed-by: Rosen Xu <rosen.xu@intel.com>\n---\nv2: move source files to ifpga and rename\n---\n drivers/raw/ifpga/afu_pmd_he_mem.c | 183 +++++++++++++++++++++++++++++++++++++\n drivers/raw/ifpga/afu_pmd_he_mem.h | 46 ++++++++++\n drivers/raw/ifpga/meson.build | 2 +-\n drivers/raw/ifpga/rte_pmd_afu.h | 7 ++\n 4 files changed, 237 insertions(+), 1 deletion(-)\n create mode 100644 drivers/raw/ifpga/afu_pmd_he_mem.c\n create mode 100644 drivers/raw/ifpga/afu_pmd_he_mem.h", "diff": "diff --git a/drivers/raw/ifpga/afu_pmd_he_mem.c b/drivers/raw/ifpga/afu_pmd_he_mem.c\nnew file mode 100644\nindex 0000000..0f57a03\n--- /dev/null\n+++ b/drivers/raw/ifpga/afu_pmd_he_mem.c\n@@ -0,0 +1,183 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ */\n+\n+#include <errno.h>\n+#include <stdio.h>\n+#include <stdint.h>\n+#include <stdlib.h>\n+#include <unistd.h>\n+#include <fcntl.h>\n+#include <poll.h>\n+#include <sys/eventfd.h>\n+#include <sys/ioctl.h>\n+\n+#include <rte_eal.h>\n+#include <rte_malloc.h>\n+#include <rte_memcpy.h>\n+#include <rte_io.h>\n+#include <rte_vfio.h>\n+#include <rte_bus_pci.h>\n+#include <rte_bus_ifpga.h>\n+#include <rte_rawdev.h>\n+\n+#include \"afu_pmd_core.h\"\n+#include \"afu_pmd_he_mem.h\"\n+\n+static int he_mem_tg_test(struct afu_rawdev *dev)\n+{\n+\tstruct he_mem_tg_priv *priv = NULL;\n+\tstruct rte_pmd_afu_he_mem_tg_cfg *cfg = NULL;\n+\tstruct he_mem_tg_ctx *ctx = NULL;\n+\tuint64_t value = 0x12345678;\n+\tuint64_t cap = 0;\n+\tuint64_t channel_mask = 0;\n+\tint i, t = 0;\n+\n+\tif (!dev)\n+\t\treturn -EINVAL;\n+\n+\tpriv = (struct he_mem_tg_priv *)dev->priv;\n+\tif (!priv)\n+\t\treturn -ENOENT;\n+\n+\tcfg = &priv->he_mem_tg_cfg;\n+\tctx = &priv->he_mem_tg_ctx;\n+\n+\tIFPGA_RAWDEV_PMD_DEBUG(\"Channel mask: 0x%x\", cfg->channel_mask);\n+\n+\trte_write64(value, ctx->addr + MEM_TG_SCRATCHPAD);\n+\tcap = rte_read64(ctx->addr + MEM_TG_SCRATCHPAD);\n+\tIFPGA_RAWDEV_PMD_DEBUG(\"Scratchpad value: 0x%\"PRIx64, cap);\n+\tif (cap != value) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Test scratchpad register failed\");\n+\t\treturn -EIO;\n+\t}\n+\n+\tcap = rte_read64(ctx->addr + MEM_TG_CTRL);\n+\tIFPGA_RAWDEV_PMD_DEBUG(\"Capability: 0x%\"PRIx64, cap);\n+\n+\tchannel_mask = cfg->channel_mask & cap;\n+\t/* start traffic generators */\n+\trte_write64(channel_mask, ctx->addr + MEM_TG_CTRL);\n+\n+\t/* check test status */\n+\twhile (t < MEM_TG_TIMEOUT_MS) {\n+\t\tvalue = rte_read64(ctx->addr + MEM_TG_STAT);\n+\t\tfor (i = 0; i < NUM_MEM_TG_CHANNELS; i++) {\n+\t\t\tif (channel_mask & (1 << i)) {\n+\t\t\t\tif (TGACTIVE(value, i))\n+\t\t\t\t\tcontinue;\n+\t\t\t\tprintf(\"TG channel %d test %s\\n\", i,\n+\t\t\t\t\tTGPASS(value, i) ? \"pass\" :\n+\t\t\t\t\tTGTIMEOUT(value, i) ? \"timeout\" :\n+\t\t\t\t\tTGFAIL(value, i) ? \"fail\" : \"error\");\n+\t\t\t\tchannel_mask &= ~(1 << i);\n+\t\t\t}\n+\t\t}\n+\t\tif (!channel_mask)\n+\t\t\tbreak;\n+\t\trte_delay_ms(MEM_TG_POLL_INTERVAL_MS);\n+\t\tt += MEM_TG_POLL_INTERVAL_MS;\n+\t}\n+\n+\tif (channel_mask) {\n+\t\tIFPGA_RAWDEV_PMD_ERR(\"Timeout 0x%04lx\", (unsigned long)value);\n+\t\treturn channel_mask;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int he_mem_tg_init(struct afu_rawdev *dev)\n+{\n+\tstruct he_mem_tg_priv *priv = NULL;\n+\tstruct he_mem_tg_ctx *ctx = NULL;\n+\n+\tif (!dev)\n+\t\treturn -EINVAL;\n+\n+\tpriv = (struct he_mem_tg_priv *)dev->priv;\n+\tif (!priv) {\n+\t\tpriv = rte_zmalloc(NULL, sizeof(struct he_mem_tg_priv), 0);\n+\t\tif (!priv)\n+\t\t\treturn -ENOMEM;\n+\t\tdev->priv = priv;\n+\t}\n+\n+\tctx = &priv->he_mem_tg_ctx;\n+\tctx->addr = (uint8_t *)dev->addr;\n+\n+\treturn 0;\n+}\n+\n+static int he_mem_tg_config(struct afu_rawdev *dev, void *config,\n+\tsize_t config_size)\n+{\n+\tstruct he_mem_tg_priv *priv = NULL;\n+\n+\tif (!dev || !config || !config_size)\n+\t\treturn -EINVAL;\n+\n+\tpriv = (struct he_mem_tg_priv *)dev->priv;\n+\tif (!priv)\n+\t\treturn -ENOENT;\n+\n+\tif (config_size != sizeof(struct rte_pmd_afu_he_mem_tg_cfg))\n+\t\treturn -EINVAL;\n+\n+\trte_memcpy(&priv->he_mem_tg_cfg, config, sizeof(priv->he_mem_tg_cfg));\n+\n+\treturn 0;\n+}\n+\n+static int he_mem_tg_close(struct afu_rawdev *dev)\n+{\n+\tif (!dev)\n+\t\treturn -EINVAL;\n+\n+\trte_free(dev->priv);\n+\tdev->priv = NULL;\n+\n+\treturn 0;\n+}\n+\n+static int he_mem_tg_dump(struct afu_rawdev *dev, FILE *f)\n+{\n+\tstruct he_mem_tg_priv *priv = NULL;\n+\tstruct he_mem_tg_ctx *ctx = NULL;\n+\n+\tif (!dev)\n+\t\treturn -EINVAL;\n+\n+\tpriv = (struct he_mem_tg_priv *)dev->priv;\n+\tif (!priv)\n+\t\treturn -ENOENT;\n+\n+\tif (!f)\n+\t\tf = stdout;\n+\n+\tctx = &priv->he_mem_tg_ctx;\n+\n+\tfprintf(f, \"addr:\\t\\t%p\\n\", (void *)ctx->addr);\n+\n+\treturn 0;\n+}\n+\n+static struct afu_ops he_mem_tg_ops = {\n+\t.init = he_mem_tg_init,\n+\t.config = he_mem_tg_config,\n+\t.start = NULL,\n+\t.stop = NULL,\n+\t.test = he_mem_tg_test,\n+\t.close = he_mem_tg_close,\n+\t.dump = he_mem_tg_dump,\n+\t.reset = NULL\n+};\n+\n+struct afu_rawdev_drv he_mem_tg_drv = {\n+\t.uuid = { HE_MEM_TG_UUID_L, HE_MEM_TG_UUID_H },\n+\t.ops = &he_mem_tg_ops\n+};\n+\n+AFU_PMD_REGISTER(he_mem_tg_drv);\ndiff --git a/drivers/raw/ifpga/afu_pmd_he_mem.h b/drivers/raw/ifpga/afu_pmd_he_mem.h\nnew file mode 100644\nindex 0000000..5549687\n--- /dev/null\n+++ b/drivers/raw/ifpga/afu_pmd_he_mem.h\n@@ -0,0 +1,46 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ */\n+\n+#ifndef _AFU_PMD_HE_MEM_H_\n+#define _AFU_PMD_HE_MEM_H_\n+\n+#ifdef __cplusplus\n+extern \"C\" {\n+#endif\n+\n+#include \"afu_pmd_core.h\"\n+#include \"rte_pmd_afu.h\"\n+\n+#define HE_MEM_TG_UUID_L 0xa3dc5b831f5cecbb\n+#define HE_MEM_TG_UUID_H 0x4dadea342c7848cb\n+\n+#define NUM_MEM_TG_CHANNELS 4\n+#define MEM_TG_TIMEOUT_MS 5000\n+#define MEM_TG_POLL_INTERVAL_MS 10\n+\n+/* MEM-TG registers definition */\n+#define MEM_TG_SCRATCHPAD 0x28\n+#define MEM_TG_CTRL 0x30\n+#define TGCONTROL(n) (1 << (n))\n+#define MEM_TG_STAT 0x38\n+#define TGSTATUS(v, n) (((v) >> (n << 2)) & 0xf)\n+#define TGPASS(v, n) (((v) >> ((n << 2) + 3)) & 0x1)\n+#define TGFAIL(v, n) (((v) >> ((n << 2) + 2)) & 0x1)\n+#define TGTIMEOUT(v, n) (((v) >> ((n << 2) + 1)) & 0x1)\n+#define TGACTIVE(v, n) (((v) >> (n << 2)) & 0x1)\n+\n+struct he_mem_tg_ctx {\n+\tuint8_t *addr;\n+};\n+\n+struct he_mem_tg_priv {\n+\tstruct rte_pmd_afu_he_mem_tg_cfg he_mem_tg_cfg;\n+\tstruct he_mem_tg_ctx he_mem_tg_ctx;\n+};\n+\n+#ifdef __cplusplus\n+}\n+#endif\n+\n+#endif /* _AFU_PMD_HE_MEM_H_ */\ndiff --git a/drivers/raw/ifpga/meson.build b/drivers/raw/ifpga/meson.build\nindex 629ff8a..dc6941d 100644\n--- a/drivers/raw/ifpga/meson.build\n+++ b/drivers/raw/ifpga/meson.build\n@@ -14,7 +14,7 @@ deps += ['ethdev', 'rawdev', 'pci', 'bus_pci', 'kvargs',\n 'bus_vdev', 'bus_ifpga', 'net', 'net_i40e', 'net_ipn3ke']\n \n sources = files('ifpga_rawdev.c', 'rte_pmd_ifpga.c', 'afu_pmd_core.c',\n- 'afu_pmd_n3000.c', 'afu_pmd_he_lpbk.c')\n+ 'afu_pmd_n3000.c', 'afu_pmd_he_lpbk.c', 'afu_pmd_he_mem.c')\n \n includes += include_directories('base')\n includes += include_directories('../../net/ipn3ke')\ndiff --git a/drivers/raw/ifpga/rte_pmd_afu.h b/drivers/raw/ifpga/rte_pmd_afu.h\nindex 19b3902..213e854 100644\n--- a/drivers/raw/ifpga/rte_pmd_afu.h\n+++ b/drivers/raw/ifpga/rte_pmd_afu.h\n@@ -104,6 +104,13 @@ struct rte_pmd_afu_he_lpbk_cfg {\n \tuint32_t freq_mhz;\n };\n \n+/**\n+ * HE-MEM-TG AFU configuration data structure.\n+ */\n+struct rte_pmd_afu_he_mem_tg_cfg {\n+\tuint32_t channel_mask; /* mask of traffic generator channel */\n+};\n+\n #ifdef __cplusplus\n }\n #endif\n", "prefixes": [ "v8", "4/5" ] }