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GET /api/patches/112809/?format=api
{ "id": 112809, "url": "http://patches.dpdk.org/api/patches/112809/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220616023012.16013-10-lizh@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220616023012.16013-10-lizh@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220616023012.16013-10-lizh@nvidia.com", "date": "2022-06-16T02:30:06", "name": "[v2,09/15] vdpa/mlx5: add task ring for MT management", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "af012d0f857b48b6bf067fb996191a2a6cae0b90", "submitter": { "id": 1967, "url": "http://patches.dpdk.org/api/people/1967/?format=api", "name": "Li Zhang", "email": "lizh@nvidia.com" }, "delegate": { "id": 2642, "url": "http://patches.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220616023012.16013-10-lizh@nvidia.com/mbox/", "series": [ { "id": 23547, "url": "http://patches.dpdk.org/api/series/23547/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23547", "date": "2022-06-16T02:29:59", "name": "mlx5/vdpa: optimize live migration time", "version": 2, "mbox": "http://patches.dpdk.org/series/23547/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/112809/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/112809/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": 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09/15] vdpa/mlx5: add task ring for MT management", "Date": "Thu, 16 Jun 2022 05:30:06 +0300", "Message-ID": "<20220616023012.16013-10-lizh@nvidia.com>", "X-Mailer": "git-send-email 2.31.1", "In-Reply-To": "<20220616023012.16013-1-lizh@nvidia.com>", "References": "<20220408075606.33056-1-lizh@nvidia.com>\n <20220616023012.16013-1-lizh@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"UTF-8\"", "Content-Transfer-Encoding": "8bit", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "723c8f03-ba43-4be9-7a4b-08da4f405664", "X-MS-TrafficTypeDiagnostic": "CY4PR12MB1895:EE_", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <CY4PR12MB18951A20B4A17AE7CC2CC70CBFAC9@CY4PR12MB1895.namprd12.prod.outlook.com>", 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PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230016)(4636009)(36840700001)(40470700004)(46966006)(8936002)(508600001)(316002)(40460700003)(54906003)(81166007)(110136005)(8676002)(356005)(5660300002)(6636002)(55016003)(4326008)(70586007)(70206006)(336012)(83380400001)(26005)(47076005)(1076003)(107886003)(2616005)(426003)(7696005)(16526019)(6286002)(186003)(2906002)(82310400005)(6666004)(86362001)(36860700001)(36756003)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "16 Jun 2022 02:31:37.1023 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 723c8f03-ba43-4be9-7a4b-08da4f405664", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT059.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CY4PR12MB1895", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "The configuration threads tasks need a container to\nsupport multiple tasks assigned to a thread in parallel.\nUse rte_ring container per thread to manage\nthe thread tasks without locks.\nThe caller thread from the user context opens a task to\na thread and enqueue it to the thread ring.\nThe thread polls its ring and dequeue tasks.\nThat’s why the ring should be in multi-producer\nand single consumer mode.\nAnatomic counter manages the tasks completion notification.\nThe threads report errors to the caller by\na dedicated error counter per task.\n\nSigned-off-by: Li Zhang <lizh@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/vdpa/mlx5/mlx5_vdpa.h | 17 ++++\n drivers/vdpa/mlx5/mlx5_vdpa_cthread.c | 115 +++++++++++++++++++++++++-\n 2 files changed, 130 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h\nindex 4e7c2557b7..2bbb868ec6 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.h\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.h\n@@ -74,10 +74,22 @@ enum {\n };\n \n #define MLX5_VDPA_MAX_C_THRD 256\n+#define MLX5_VDPA_MAX_TASKS_PER_THRD 4096\n+#define MLX5_VDPA_TASKS_PER_DEV 64\n+\n+/* Generic task information and size must be multiple of 4B. */\n+struct mlx5_vdpa_task {\n+\tstruct mlx5_vdpa_priv *priv;\n+\tuint32_t *remaining_cnt;\n+\tuint32_t *err_cnt;\n+\tuint32_t idx;\n+} __rte_packed __rte_aligned(4);\n \n /* Generic mlx5_vdpa_c_thread information. */\n struct mlx5_vdpa_c_thread {\n \tpthread_t tid;\n+\tstruct rte_ring *rng;\n+\tpthread_cond_t c_cond;\n };\n \n struct mlx5_vdpa_conf_thread_mng {\n@@ -532,4 +544,9 @@ mlx5_vdpa_mult_threads_create(int cpu_core);\n */\n void\n mlx5_vdpa_mult_threads_destroy(bool need_unlock);\n+\n+bool\n+mlx5_vdpa_task_add(struct mlx5_vdpa_priv *priv,\n+\t\tuint32_t thrd_idx,\n+\t\tuint32_t num);\n #endif /* RTE_PMD_MLX5_VDPA_H_ */\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c\nindex ba7d8b63b3..1fdc92d3ad 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_cthread.c\n@@ -11,17 +11,103 @@\n #include <rte_alarm.h>\n #include <rte_tailq.h>\n #include <rte_ring_elem.h>\n+#include <rte_ring_peek.h>\n \n #include <mlx5_common.h>\n \n #include \"mlx5_vdpa_utils.h\"\n #include \"mlx5_vdpa.h\"\n \n+static inline uint32_t\n+mlx5_vdpa_c_thrd_ring_dequeue_bulk(struct rte_ring *r,\n+\tvoid **obj, uint32_t n, uint32_t *avail)\n+{\n+\tuint32_t m;\n+\n+\tm = rte_ring_dequeue_bulk_elem_start(r, obj,\n+\t\tsizeof(struct mlx5_vdpa_task), n, avail);\n+\tn = (m == n) ? n : 0;\n+\trte_ring_dequeue_elem_finish(r, n);\n+\treturn n;\n+}\n+\n+static inline uint32_t\n+mlx5_vdpa_c_thrd_ring_enqueue_bulk(struct rte_ring *r,\n+\tvoid * const *obj, uint32_t n, uint32_t *free)\n+{\n+\tuint32_t m;\n+\n+\tm = rte_ring_enqueue_bulk_elem_start(r, n, free);\n+\tn = (m == n) ? n : 0;\n+\trte_ring_enqueue_elem_finish(r, obj,\n+\t\tsizeof(struct mlx5_vdpa_task), n);\n+\treturn n;\n+}\n+\n+bool\n+mlx5_vdpa_task_add(struct mlx5_vdpa_priv *priv,\n+\t\tuint32_t thrd_idx,\n+\t\tuint32_t num)\n+{\n+\tstruct rte_ring *rng = conf_thread_mng.cthrd[thrd_idx].rng;\n+\tstruct mlx5_vdpa_task task[MLX5_VDPA_TASKS_PER_DEV];\n+\tuint32_t i;\n+\n+\tMLX5_ASSERT(num <= MLX5_VDPA_TASKS_PER_DEV);\n+\tfor (i = 0 ; i < num; i++) {\n+\t\ttask[i].priv = priv;\n+\t\t/* To be added later. */\n+\t}\n+\tif (!mlx5_vdpa_c_thrd_ring_enqueue_bulk(rng, (void **)&task, num, NULL))\n+\t\treturn -1;\n+\tfor (i = 0 ; i < num; i++)\n+\t\tif (task[i].remaining_cnt)\n+\t\t\t__atomic_fetch_add(task[i].remaining_cnt, 1,\n+\t\t\t\t__ATOMIC_RELAXED);\n+\t/* wake up conf thread. */\n+\tpthread_mutex_lock(&conf_thread_mng.cthrd_lock);\n+\tpthread_cond_signal(&conf_thread_mng.cthrd[thrd_idx].c_cond);\n+\tpthread_mutex_unlock(&conf_thread_mng.cthrd_lock);\n+\treturn 0;\n+}\n+\n static void *\n mlx5_vdpa_c_thread_handle(void *arg)\n {\n-\t/* To be added later. */\n-\treturn arg;\n+\tstruct mlx5_vdpa_conf_thread_mng *multhrd = arg;\n+\tpthread_t thread_id = pthread_self();\n+\tstruct mlx5_vdpa_priv *priv;\n+\tstruct mlx5_vdpa_task task;\n+\tstruct rte_ring *rng;\n+\tuint32_t thrd_idx;\n+\tuint32_t task_num;\n+\n+\tfor (thrd_idx = 0; thrd_idx < multhrd->max_thrds;\n+\t\tthrd_idx++)\n+\t\tif (multhrd->cthrd[thrd_idx].tid == thread_id)\n+\t\t\tbreak;\n+\tif (thrd_idx >= multhrd->max_thrds)\n+\t\treturn NULL;\n+\trng = multhrd->cthrd[thrd_idx].rng;\n+\twhile (1) {\n+\t\ttask_num = mlx5_vdpa_c_thrd_ring_dequeue_bulk(rng,\n+\t\t\t(void **)&task, 1, NULL);\n+\t\tif (!task_num) {\n+\t\t\t/* No task and condition wait. */\n+\t\t\tpthread_mutex_lock(&multhrd->cthrd_lock);\n+\t\t\tpthread_cond_wait(\n+\t\t\t\t&multhrd->cthrd[thrd_idx].c_cond,\n+\t\t\t\t&multhrd->cthrd_lock);\n+\t\t\tpthread_mutex_unlock(&multhrd->cthrd_lock);\n+\t\t}\n+\t\tpriv = task.priv;\n+\t\tif (priv == NULL)\n+\t\t\tcontinue;\n+\t\t__atomic_fetch_sub(task.remaining_cnt,\n+\t\t\t1, __ATOMIC_RELAXED);\n+\t\t/* To be added later. */\n+\t}\n+\treturn NULL;\n }\n \n static void\n@@ -34,6 +120,10 @@ mlx5_vdpa_c_thread_destroy(uint32_t thrd_idx, bool need_unlock)\n \t\tif (need_unlock)\n \t\t\tpthread_mutex_init(&conf_thread_mng.cthrd_lock, NULL);\n \t}\n+\tif (conf_thread_mng.cthrd[thrd_idx].rng) {\n+\t\trte_ring_free(conf_thread_mng.cthrd[thrd_idx].rng);\n+\t\tconf_thread_mng.cthrd[thrd_idx].rng = NULL;\n+\t}\n }\n \n static int\n@@ -45,6 +135,7 @@ mlx5_vdpa_c_thread_create(int cpu_core)\n \trte_cpuset_t cpuset;\n \tpthread_attr_t attr;\n \tuint32_t thrd_idx;\n+\tuint32_t ring_num;\n \tchar name[32];\n \tint ret;\n \n@@ -60,8 +151,26 @@ mlx5_vdpa_c_thread_create(int cpu_core)\n \t\tDRV_LOG(ERR, \"Failed to set thread priority.\");\n \t\tgoto c_thread_err;\n \t}\n+\tring_num = MLX5_VDPA_MAX_TASKS_PER_THRD / conf_thread_mng.max_thrds;\n+\tif (!ring_num) {\n+\t\tDRV_LOG(ERR, \"Invalid ring number for thread.\");\n+\t\tgoto c_thread_err;\n+\t}\n \tfor (thrd_idx = 0; thrd_idx < conf_thread_mng.max_thrds;\n \t\tthrd_idx++) {\n+\t\tsnprintf(name, sizeof(name), \"vDPA-mthread-ring-%d\",\n+\t\t\tthrd_idx);\n+\t\tconf_thread_mng.cthrd[thrd_idx].rng = rte_ring_create_elem(name,\n+\t\t\tsizeof(struct mlx5_vdpa_task), ring_num,\n+\t\t\trte_socket_id(),\n+\t\t\tRING_F_MP_HTS_ENQ | RING_F_MC_HTS_DEQ |\n+\t\t\tRING_F_EXACT_SZ);\n+\t\tif (!conf_thread_mng.cthrd[thrd_idx].rng) {\n+\t\t\tDRV_LOG(ERR,\n+\t\t\t\"Failed to create vdpa multi-threads %d ring.\",\n+\t\t\tthrd_idx);\n+\t\t\tgoto c_thread_err;\n+\t\t}\n \t\tret = pthread_create(&conf_thread_mng.cthrd[thrd_idx].tid,\n \t\t\t\t&attr, mlx5_vdpa_c_thread_handle,\n \t\t\t\t(void *)&conf_thread_mng);\n@@ -91,6 +200,8 @@ mlx5_vdpa_c_thread_create(int cpu_core)\n \t\t\t\t\tname);\n \t\telse\n \t\t\tDRV_LOG(DEBUG, \"Thread name: %s.\", name);\n+\t\tpthread_cond_init(&conf_thread_mng.cthrd[thrd_idx].c_cond,\n+\t\t\tNULL);\n \t}\n \tpthread_mutex_unlock(&conf_thread_mng.cthrd_lock);\n \treturn 0;\n", "prefixes": [ "v2", "09/15" ] }