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GET /api/patches/112554/?format=api
{ "id": 112554, "url": "http://patches.dpdk.org/api/patches/112554/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220608115826.11783-1-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220608115826.11783-1-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220608115826.11783-1-getelson@nvidia.com", "date": "2022-06-08T11:58:25", "name": "[1/2] common/mlx5: update log format after devx_general_cmd error", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "6e6b77474b367024221a31b431a49b6437f2fce2", "submitter": { "id": 1882, "url": "http://patches.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220608115826.11783-1-getelson@nvidia.com/mbox/", "series": [ { "id": 23416, "url": "http://patches.dpdk.org/api/series/23416/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23416", "date": "2022-06-08T11:58:25", "name": "[1/2] common/mlx5: update log format after devx_general_cmd error", "version": 1, "mbox": "http://patches.dpdk.org/series/23416/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/112554/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/112554/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1E698A04FD;\n\tWed, 8 Jun 2022 13:58:49 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1290040689;\n\tWed, 8 Jun 2022 13:58:49 +0200 (CEST)", "from NAM10-BN7-obe.outbound.protection.outlook.com\n (mail-bn7nam10on2048.outbound.protection.outlook.com [40.107.92.48])\n by mails.dpdk.org (Postfix) with ESMTP id BC67A4021D\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>, <getelson@nvidia.com>", "CC": "<rasland@nvidia.com>, Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "Subject": "[PATCH 1/2] common/mlx5: update log format after devx_general_cmd\n error", "Date": "Wed, 8 Jun 2022 14:58:25 +0300", "Message-ID": "<20220608115826.11783-1-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.35.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "ad2c07a1-0a92-4f75-a79b-08da49463dc5", "X-MS-TrafficTypeDiagnostic": "MWHPR12MB1216:EE_", "X-Microsoft-Antispam-PRVS": "\n <MWHPR12MB1216F1BF7C7F84118F3C1D98A5A49@MWHPR12MB1216.namprd12.prod.outlook.com>", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n 974NryV1ca3UXUEZEtMPPoHynG0vHf8qAJF88h1SgsWcP+hwduullW9COKLmD8EZglbq6QAM63uM31aYKrHP8VzJUKRpJAOl8iARP7iAmrkpxM7hPLBG7wCJ+RwKnzMZiNkJag7hovsEhOaijZIPY3FV0juhQrUopTmZ+OArbK3vSosSh2TwdpjvXpDPjL4jbW6JwImdxK1fFKbpltKW5gajz14WeDxxSFmubET/WskjOzt6xaRiSge7cxuk8r8f8PqRmt6r5JqZl7NzdZTMKf/YQ6NqmCIn90DT/UOJlt6pl0eeAWj4a4j1q77oHL9vuEEKWyNASAawOmvriCcMdsz1IKNxPVk8b/69zNgL3kr8FgSYMLV6mU5kWgL3p5ty163YcUNVul5Qr9PiKrbRI1bcUdAld1Enu+Nt0lt5qhOz0DL6Oui0zX21nj6WJ1wCsLg8GZIjF7DaRumwEeXf62kEcHHv9UjfDYiIQFKiG718SQz6zixswT6HbMSoB4IOUqGtHLHqyKPcQieyE1bvteUbk0mjGWXeCfoV9mi5eeDK5KFLkz4DYkTmws+yJVm2wIgf9AVnva1TJo13RY6CEPgyJoQlDv6y8jsG5UmBcJseKJ0fpYHCZvdDTTn40BJCOfPQ3Ew/zODd45xEzEvqcdj1sJD6OreHSvY9N9WW7PbcK71ALku3eezUYOdxmI8+ggTTZjSzjzK6nK9Mw/xGpA==", "X-Forefront-Antispam-Report": "CIP:12.22.5.238; CTRY:US; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:InfoNoRecords; CAT:NONE;\n SFS:(13230001)(4636009)(46966006)(40470700004)(36840700001)(107886003)(40460700003)(83380400001)(8936002)(36756003)(81166007)(1076003)(336012)(186003)(6666004)(47076005)(356005)(54906003)(508600001)(426003)(26005)(5660300002)(55016003)(2616005)(8676002)(16526019)(4326008)(36860700001)(110136005)(316002)(82310400005)(6286002)(70586007)(7049001)(70206006)(86362001)(2906002)(15650500001)(7696005)(36900700001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Jun 2022 11:58:45.8154 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ad2c07a1-0a92-4f75-a79b-08da49463dc5", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.238];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT053.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR12MB1216", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Application can fetch syndrome value after FW operation failure\nstarting from Mellanox OFED-5.6.\nThe patch updates log data issued after devx_general_cmd error.\n\nSigned-off-by: Gregory Etelson <getelson@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 103 ++++++++++++---------------\n 1 file changed, 44 insertions(+), 59 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex c6bdbc12bb..bc06aeccc7 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -13,39 +13,49 @@\n #include \"mlx5_common_log.h\"\n #include \"mlx5_malloc.h\"\n \n+/* FW writes status value to the OUT buffer at offset 00H */\n+#define MLX5_FW_STATUS(o) MLX5_GET(general_obj_out_cmd_hdr, (o), status)\n+/* FW writes syndrome value to the OUT buffer at offset 04H */\n+#define MLX5_FW_SYNDROME(o) MLX5_GET(general_obj_out_cmd_hdr, (o), syndrome)\n+\n+#define MLX5_DEVX_ERR_RC(x) ((x) > 0 ? -(x) : ((x) < 0 ? (x) : -1))\n+\n+static void\n+mlx5_devx_err_log(void *out, const char *reason,\n+\t\t const char *param, uint32_t value)\n+{\n+\trte_errno = errno;\n+\tif (!param)\n+\t\tDRV_LOG(ERR, \"DevX %s failed errno=%d status=%#x syndrome=%#x\",\n+\t\t\treason, errno, MLX5_FW_STATUS(out),\n+\t\t\tMLX5_FW_SYNDROME(out));\n+\telse\n+\t\tDRV_LOG(ERR, \"DevX %s %s=%#X failed errno=%d status=%#x syndrome=%#x\",\n+\t\t\treason, param, value, errno, MLX5_FW_STATUS(out),\n+\t\t\tMLX5_FW_SYNDROME(out));\n+}\n+\n static void *\n mlx5_devx_get_hca_cap(void *ctx, uint32_t *in, uint32_t *out,\n \t\t int *err, uint32_t flags)\n {\n \tconst size_t size_in = MLX5_ST_SZ_DW(query_hca_cap_in) * sizeof(int);\n \tconst size_t size_out = MLX5_ST_SZ_DW(query_hca_cap_out) * sizeof(int);\n-\tint status, syndrome, rc;\n+\tint rc;\n \n-\tif (err)\n-\t\t*err = 0;\n \tmemset(in, 0, size_in);\n \tmemset(out, 0, size_out);\n \tMLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);\n \tMLX5_SET(query_hca_cap_in, in, op_mod, flags);\n \trc = mlx5_glue->devx_general_cmd(ctx, in, size_in, out, size_out);\n-\tif (rc) {\n-\t\tDRV_LOG(ERR,\n-\t\t\t\"Failed to query devx HCA capabilities func %#02x\",\n-\t\t\tflags >> 1);\n+\tif (rc || MLX5_FW_STATUS(out)) {\n+\t\tmlx5_devx_err_log(out, \"HCA capabilities\", \"func\", flags >> 1);\n \t\tif (err)\n-\t\t\t*err = rc > 0 ? -rc : rc;\n-\t\treturn NULL;\n-\t}\n-\tstatus = MLX5_GET(query_hca_cap_out, out, status);\n-\tsyndrome = MLX5_GET(query_hca_cap_out, out, syndrome);\n-\tif (status) {\n-\t\tDRV_LOG(ERR,\n-\t\t\t\"Failed to query devx HCA capabilities func %#02x status %x, syndrome = %x\",\n-\t\t\tflags >> 1, status, syndrome);\n-\t\tif (err)\n-\t\t\t*err = -1;\n+\t\t\t*err = MLX5_DEVX_ERR_RC(rc);\n \t\treturn NULL;\n \t}\n+\tif (err)\n+\t\t*err = 0;\n \treturn MLX5_ADDR_OF(query_hca_cap_out, out, capability);\n }\n \n@@ -74,7 +84,7 @@ mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,\n \tuint32_t in[MLX5_ST_SZ_DW(access_register_in)] = {0};\n \tuint32_t out[MLX5_ST_SZ_DW(access_register_out) +\n \t\t MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};\n-\tint status, rc;\n+\tint rc;\n \n \tMLX5_ASSERT(data && dw_cnt);\n \tMLX5_ASSERT(dw_cnt <= MLX5_ACCESS_REGISTER_DATA_DWORD_MAX);\n@@ -91,23 +101,13 @@ mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id, uint32_t arg,\n \trc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,\n \t\t\t\t\t MLX5_ST_SZ_BYTES(access_register_out) +\n \t\t\t\t\t sizeof(uint32_t) * dw_cnt);\n-\tif (rc)\n-\t\tgoto error;\n-\tstatus = MLX5_GET(access_register_out, out, status);\n-\tif (status) {\n-\t\tint syndrome = MLX5_GET(access_register_out, out, syndrome);\n-\n-\t\tDRV_LOG(DEBUG, \"Failed to read access NIC register 0x%X, \"\n-\t\t\t \"status %x, syndrome = %x\",\n-\t\t\t reg_id, status, syndrome);\n-\t\treturn -1;\n+\tif (rc || MLX5_FW_STATUS(out)) {\n+\t\tmlx5_devx_err_log(out, \"read access\", \"NIC register\", reg_id);\n+\t\treturn MLX5_DEVX_ERR_RC(rc);\n \t}\n \tmemcpy(data, &out[MLX5_ST_SZ_DW(access_register_out)],\n \t dw_cnt * sizeof(uint32_t));\n \treturn 0;\n-error:\n-\trc = (rc > 0) ? -rc : rc;\n-\treturn rc;\n }\n \n /**\n@@ -134,7 +134,7 @@ mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,\n \tuint32_t in[MLX5_ST_SZ_DW(access_register_in) +\n \t\t MLX5_ACCESS_REGISTER_DATA_DWORD_MAX] = {0};\n \tuint32_t out[MLX5_ST_SZ_DW(access_register_out)] = {0};\n-\tint status, rc;\n+\tint rc;\n \tvoid *ptr;\n \n \tMLX5_ASSERT(data && dw_cnt);\n@@ -152,26 +152,19 @@ mlx5_devx_cmd_register_write(void *ctx, uint16_t reg_id, uint32_t arg,\n \tptr = MLX5_ADDR_OF(access_register_in, in, register_data);\n \tmemcpy(ptr, data, dw_cnt * sizeof(uint32_t));\n \trc = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out, sizeof(out));\n-\n+\tif (rc || MLX5_FW_STATUS(out)) {\n+\t\tmlx5_devx_err_log(out, \"write access\", \"NIC register\", reg_id);\n+\t\treturn MLX5_DEVX_ERR_RC(rc);\n+\t}\n \trc = mlx5_glue->devx_general_cmd(ctx, in,\n \t\t\t\t\t MLX5_ST_SZ_BYTES(access_register_in) +\n \t\t\t\t\t dw_cnt * sizeof(uint32_t),\n \t\t\t\t\t out, sizeof(out));\n-\tif (rc)\n-\t\tgoto error;\n-\tstatus = MLX5_GET(access_register_out, out, status);\n-\tif (status) {\n-\t\tint syndrome = MLX5_GET(access_register_out, out, syndrome);\n-\n-\t\tDRV_LOG(DEBUG, \"Failed to write access NIC register 0x%X, \"\n-\t\t\t \"status %x, syndrome = %x\",\n-\t\t\t reg_id, status, syndrome);\n-\t\treturn -1;\n+\tif (rc || MLX5_FW_STATUS(out)) {\n+\t\tmlx5_devx_err_log(out, \"write access\", \"NIC register\", reg_id);\n+\t\treturn MLX5_DEVX_ERR_RC(rc);\n \t}\n \treturn 0;\n-error:\n-\trc = (rc > 0) ? -rc : rc;\n-\treturn rc;\n }\n \n /**\n@@ -466,7 +459,7 @@ mlx5_devx_cmd_query_nic_vport_context(void *ctx,\n \tuint32_t in[MLX5_ST_SZ_DW(query_nic_vport_context_in)] = {0};\n \tuint32_t out[MLX5_ST_SZ_DW(query_nic_vport_context_out)] = {0};\n \tvoid *vctx;\n-\tint status, syndrome, rc;\n+\tint rc;\n \n \t/* Query NIC vport context to determine inline mode. */\n \tMLX5_SET(query_nic_vport_context_in, in, opcode,\n@@ -477,23 +470,15 @@ mlx5_devx_cmd_query_nic_vport_context(void *ctx,\n \trc = mlx5_glue->devx_general_cmd(ctx,\n \t\t\t\t\t in, sizeof(in),\n \t\t\t\t\t out, sizeof(out));\n-\tif (rc)\n-\t\tgoto error;\n-\tstatus = MLX5_GET(query_nic_vport_context_out, out, status);\n-\tsyndrome = MLX5_GET(query_nic_vport_context_out, out, syndrome);\n-\tif (status) {\n-\t\tDRV_LOG(DEBUG, \"Failed to query NIC vport context, \"\n-\t\t\t\"status %x, syndrome = %x\", status, syndrome);\n-\t\treturn -1;\n+\tif (rc || MLX5_FW_STATUS(out)) {\n+\t\tmlx5_devx_err_log(out, \"query NIC vport context\", NULL, 0);\n+\t\treturn MLX5_DEVX_ERR_RC(rc);\n \t}\n \tvctx = MLX5_ADDR_OF(query_nic_vport_context_out, out,\n \t\t\t nic_vport_context);\n \tattr->vport_inline_mode = MLX5_GET(nic_vport_context, vctx,\n \t\t\t\t\t min_wqe_inline_mode);\n \treturn 0;\n-error:\n-\trc = (rc > 0) ? -rc : rc;\n-\treturn rc;\n }\n \n /**\n", "prefixes": [ "1/2" ] }