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GET /api/patches/11216/?format=api
{ "id": 11216, "url": "http://patches.dpdk.org/api/patches/11216/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1457462311-16349-2-git-send-email-thomas.monjalon@6wind.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1457462311-16349-2-git-send-email-thomas.monjalon@6wind.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1457462311-16349-2-git-send-email-thomas.monjalon@6wind.com", "date": "2016-03-08T18:38:29", "name": "[dpdk-dev,v3,1/3] i40e: enable extended tag", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "71a6105abcad6821270bbddcfd8e8ce9ee4b07fe", "submitter": { "id": 1, "url": "http://patches.dpdk.org/api/people/1/?format=api", "name": "Thomas Monjalon", "email": "thomas.monjalon@6wind.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1457462311-16349-2-git-send-email-thomas.monjalon@6wind.com/mbox/", "series": [], "comments": "http://patches.dpdk.org/api/patches/11216/comments/", "check": "pending", "checks": "http://patches.dpdk.org/api/patches/11216/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 7AB472C66;\n\tTue, 8 Mar 2016 19:40:15 +0100 (CET)", "from mail-wm0-f47.google.com (mail-wm0-f47.google.com\n\t[74.125.82.47]) by dpdk.org (Postfix) with ESMTP id 783E32C22\n\tfor <dev@dpdk.org>; Tue, 8 Mar 2016 19:40:13 +0100 (CET)", "by mail-wm0-f47.google.com with SMTP id n186so145293764wmn.1\n\tfor <dev@dpdk.org>; Tue, 08 Mar 2016 10:40:13 -0800 (PST)", "from XPS13.localdomain (171.36.101.84.rev.sfr.net. [84.101.36.171])\n\tby smtp.gmail.com with ESMTPSA id\n\td2sm2955883wjf.28.2016.03.08.10.40.12\n\t(version=TLSv1/SSLv3 cipher=OTHER);\n\tTue, 08 Mar 2016 10:40:12 -0800 (PST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=6wind-com.20150623.gappssmtp.com; s=20150623;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=WAPTq4HF6t8l2qlcqpq4HzEbO5YtRLCWM6PytfkS+V4=;\n\tb=xFLA0aF3n+U62/2cBL0n4hYi/D48z/7dKyny0adMhqJR749EKbP2160KET/DHOXLua\n\tkmql5o2gqW6hwwwDY1Ob9BfyEXBtrvbhJKHk8HQzfR84Sa9db+F6lsY71Ju87Y8Fbi2H\n\t0atLBPEPzinxkBdMgKrcykKP3Klh53sh28Labi4beQxzgO1O9a8IcVIq4139yYJASWQX\n\tQ8Vs9EwweKEkKc0YizukfCP4LDWxfpO7ICoYHry00hj6YN+4wXs0oUelzhMQ9oosZ4Ow\n\t+08Ctuo53DswSBpn2eAYma8iMHIRDlvWfHlGUbBstLOKFy7/KZodBkf8LCHUpuO2Wd3P\n\tFV7A==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20130820;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=WAPTq4HF6t8l2qlcqpq4HzEbO5YtRLCWM6PytfkS+V4=;\n\tb=jJw9M023VLbLzgIru9ukexeEMf4+p3bDDQQyKXAlzz/aoPmqaT5L7mU95hdhMUr9A2\n\tgT8PebSn9M23mWRK7WdLQ/eeg8oE76v3b9jy6wojXwI8erzCR3eKGrQllayeLQegvdEk\n\th0APsQPmnLVOqs7ps/lId74fzI3YALvMuJnvhlglb2Tpnk056yhLUVKKDZyp8NAdP49y\n\tJ63CijcXjf+Y1gJfqy91DaIslaXnOI+ECnwBh9YZLy3P98MX4loiW/wHJeJt1QHTuFZS\n\tE6grOXcr6D1RgrIcoCIJ9EIdenznRQRLqACCRzcbJfn2Cb1+MWi7uyJia7ViZlQTVHwn\n\ta5AQ==", "X-Gm-Message-State": "AD7BkJJkAQ0ZFZQHONbHmBlkG2XdHmWtxd7InrdJJCXEvetD8QgoBDS/NzTd+6SDOIVxDTqU", "X-Received": "by 10.194.190.6 with SMTP id gm6mr31225678wjc.115.1457462413348; \n\tTue, 08 Mar 2016 10:40:13 -0800 (PST)", "From": "Thomas Monjalon <thomas.monjalon@6wind.com>", "To": "helin.zhang@intel.com", "Date": "Tue, 8 Mar 2016 19:38:29 +0100", "Message-Id": "<1457462311-16349-2-git-send-email-thomas.monjalon@6wind.com>", "X-Mailer": "git-send-email 2.7.0", "In-Reply-To": "<1457462311-16349-1-git-send-email-thomas.monjalon@6wind.com>", "References": "<1456113585-15259-1-git-send-email-helin.zhang@intel.com>\n\t<1457462311-16349-1-git-send-email-thomas.monjalon@6wind.com>", "Cc": "dev@dpdk.org", "Subject": "[dpdk-dev] [PATCH v3 1/3] i40e: enable extended tag", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Helin Zhang <helin.zhang@intel.com>\n\nPCIe feature of 'Extended Tag' is important for 40G performance.\nIt adds its enabling during each port initialization, to ensure\nthe high performance.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\n---\n doc/guides/linux_gsg/enable_func.rst | 3 ++\n doc/guides/rel_notes/release_16_04.rst | 6 ++++\n drivers/net/i40e/i40e_ethdev.c | 65 ++++++++++++++++++++++++++++++++--\n 3 files changed, 71 insertions(+), 3 deletions(-)", "diff": "diff --git a/doc/guides/linux_gsg/enable_func.rst b/doc/guides/linux_gsg/enable_func.rst\nindex c3fa6d3..8cb3d79 100644\n--- a/doc/guides/linux_gsg/enable_func.rst\n+++ b/doc/guides/linux_gsg/enable_func.rst\n@@ -208,6 +208,9 @@ Enabling extended_tag and setting ``max_read_request_size`` to small size such a\n \n ``CONFIG_RTE_PCI_MAX_READ_REQUEST_SIZE``\n \n+* From release 16.04, ``extended_tag`` is enabled by default during port\n+ initialization, users don't need to care about that anymore.\n+\n Use 16 Bytes RX Descriptor Size\n ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n \ndiff --git a/doc/guides/rel_notes/release_16_04.rst b/doc/guides/rel_notes/release_16_04.rst\nindex 24f15bf..96f144e 100644\n--- a/doc/guides/rel_notes/release_16_04.rst\n+++ b/doc/guides/rel_notes/release_16_04.rst\n@@ -57,6 +57,12 @@ This section should contain new features added in this release. Sample format:\n \n * **Added vhost-user live migration support.**\n \n+* **Enabled PCI extended tag for i40e.**\n+\n+ It enabled extended tag by checking and writing corresponding PCI config\n+ space bytes, to boost the performance. In the meanwhile, it deprecated the\n+ legacy way via reading/writing sysfile supported by kernel module igb_uio.\n+\n \n Resolved Issues\n ---------------\ndiff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c\nindex ef24122..7e68c61 100644\n--- a/drivers/net/i40e/i40e_ethdev.c\n+++ b/drivers/net/i40e/i40e_ethdev.c\n@@ -273,6 +273,17 @@\n #define I40E_INSET_IPV6_TC_MASK 0x0009F00FUL\n #define I40E_INSET_IPV6_NEXT_HDR_MASK 0x000C00FFUL\n \n+/* PCI offset for querying capability */\n+#define PCI_DEV_CAP_REG 0xA4\n+/* PCI offset for enabling/disabling Extended Tag */\n+#define PCI_DEV_CTRL_REG 0xA8\n+/* Bit mask of Extended Tag capability */\n+#define PCI_DEV_CAP_EXT_TAG_MASK 0x20\n+/* Bit shift of Extended Tag enable/disable */\n+#define PCI_DEV_CTRL_EXT_TAG_SHIFT 8\n+/* Bit mask of Extended Tag enable/disable */\n+#define PCI_DEV_CTRL_EXT_TAG_MASK (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)\n+\n static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);\n static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);\n static int i40e_dev_configure(struct rte_eth_dev *dev);\n@@ -386,7 +397,7 @@ static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,\n static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,\n \t\t\t\t struct rte_eth_dcb_info *dcb_info);\n static void i40e_configure_registers(struct i40e_hw *hw);\n-static void i40e_hw_init(struct i40e_hw *hw);\n+static void i40e_hw_init(struct rte_eth_dev *dev);\n static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);\n static int i40e_mirror_rule_set(struct rte_eth_dev *dev,\n \t\t\tstruct rte_eth_mirror_conf *mirror_conf,\n@@ -765,7 +776,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)\n \ti40e_clear_hw(hw);\n \n \t/* Initialize the hardware */\n-\ti40e_hw_init(hw);\n+\ti40e_hw_init(dev);\n \n \t/* Reset here to make sure all is clean for each PF */\n \tret = i40e_pf_reset(hw);\n@@ -7262,13 +7273,61 @@ i40e_dev_filter_ctrl(struct rte_eth_dev *dev,\n }\n \n /*\n+ * Check and enable Extended Tag.\n+ * Enabling Extended Tag is important for 40G performance.\n+ */\n+static void\n+i40e_enable_extended_tag(struct rte_eth_dev *dev)\n+{\n+\tuint32_t buf = 0;\n+\tint ret;\n+\n+\tret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),\n+\t\t\t\t PCI_DEV_CAP_REG);\n+\tif (ret < 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to read PCI offset 0x%x\",\n+\t\t\t PCI_DEV_CAP_REG);\n+\t\treturn;\n+\t}\n+\tif (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {\n+\t\tPMD_DRV_LOG(ERR, \"Does not support Extended Tag\");\n+\t\treturn;\n+\t}\n+\n+\tbuf = 0;\n+\tret = rte_eal_pci_read_config(dev->pci_dev, &buf, sizeof(buf),\n+\t\t\t\t PCI_DEV_CTRL_REG);\n+\tif (ret < 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to read PCI offset 0x%x\",\n+\t\t\t PCI_DEV_CTRL_REG);\n+\t\treturn;\n+\t}\n+\tif (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {\n+\t\tPMD_DRV_LOG(DEBUG, \"Extended Tag has already been enabled\");\n+\t\treturn;\n+\t}\n+\tbuf |= PCI_DEV_CTRL_EXT_TAG_MASK;\n+\tret = rte_eal_pci_write_config(dev->pci_dev, &buf, sizeof(buf),\n+\t\t\t\t PCI_DEV_CTRL_REG);\n+\tif (ret < 0) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to write PCI offset 0x%x\",\n+\t\t\t PCI_DEV_CTRL_REG);\n+\t\treturn;\n+\t}\n+}\n+\n+/*\n * As some registers wouldn't be reset unless a global hardware reset,\n * hardware initialization is needed to put those registers into an\n * expected initial state.\n */\n static void\n-i40e_hw_init(struct i40e_hw *hw)\n+i40e_hw_init(struct rte_eth_dev *dev)\n {\n+\tstruct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\n+\ti40e_enable_extended_tag(dev);\n+\n \t/* clear the PF Queue Filter control register */\n \tI40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);\n \n", "prefixes": [ "dpdk-dev", "v3", "1/3" ] }