Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/111655/?format=api
{ "id": 111655, "url": "http://patches.dpdk.org/api/patches/111655/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1653341116-50325-6-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1653341116-50325-6-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1653341116-50325-6-git-send-email-nicolas.chautru@intel.com", "date": "2022-05-23T21:25:16", "name": "[v4,5/5] baseband/acc100: configuration of ACC101 from PF", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "072b2afa130a28040e24f69522758a481c7c2da3", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1653341116-50325-6-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 23103, "url": "http://patches.dpdk.org/api/series/23103/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23103", "date": "2022-05-23T21:25:13", "name": "drivers/baseband: PMD to support ACC100/ACC101 devices", "version": 4, "mbox": "http://patches.dpdk.org/series/23103/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/111655/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/111655/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DCB47A00C2;\n\tMon, 23 May 2022 23:34:35 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DDCFB42B76;\n\tMon, 23 May 2022 23:34:09 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 297A840156\n for <dev@dpdk.org>; Mon, 23 May 2022 23:34:04 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 May 2022 14:33:58 -0700", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by fmsmga008.fm.intel.com with ESMTP; 23 May 2022 14:33:57 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1653341645; x=1684877645;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=Vg4vzBoy1rEEZEVGDIsclar6VVwjrKJfih633Yu+HOI=;\n b=FWbm4yprR0GtJjNyeICHtjslqH+Bbi295pGn3DxChDHb7jp4UTGWIWtC\n qUrxB/7R6C5AunN3fkq9HpPDcE0pzyEQRaOiPCsvyUnc+dgBjN5Qs7spA\n iI7AR/HSXnE03R3Q7+MVa2ogXMguakSuX8fbj3mqtlumXNpCIhnsTq6BP\n FO4zmPSc8XcT/nPCCDcZ3JFCfSCNyB3j90Dt4y/fo1zodX9lnbGUStrmO\n UxUH7jjaiXG+Q2k8m1r03lXG7ub+WVEH8Itlb4riGuTic6tRN970SpMcJ\n 08tgI9zBtKxx9NL4H+rdK/ixhalG4Ssylb+np/2TuDqMYedr8coi2JGIY w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10356\"; a=\"336419947\"", "E=Sophos;i=\"5.91,247,1647327600\"; d=\"scan'208\";a=\"336419947\"", "E=Sophos;i=\"5.91,247,1647327600\"; d=\"scan'208\";a=\"629591645\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,\n maxime.coquelin@redhat.com", "Cc": "thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com,\n hemant.agrawal@nxp.com, hernan.vargas@intel.com, david.marchand@redhat.com,\n Nicolas Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v4 5/5] baseband/acc100: configuration of ACC101 from PF", "Date": "Mon, 23 May 2022 14:25:16 -0700", "Message-Id": "<1653341116-50325-6-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1653341116-50325-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1651083423-33202-1-git-send-email-nicolas.chautru@intel.com>\n <1653341116-50325-1-git-send-email-nicolas.chautru@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adding companion function specific to ACC100 and it\ncan be called from bbdev-test when running from PF.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n app/test-bbdev/test_bbdev_perf.c | 22 ++-\n drivers/baseband/acc100/rte_acc100_cfg.h | 17 ++\n drivers/baseband/acc100/rte_acc100_pmd.c | 302 +++++++++++++++++++++++++++++++\n drivers/baseband/acc100/version.map | 2 +-\n 4 files changed, 336 insertions(+), 7 deletions(-)", "diff": "diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c\nindex 0fa119a..89b1e79 100644\n--- a/app/test-bbdev/test_bbdev_perf.c\n+++ b/app/test-bbdev/test_bbdev_perf.c\n@@ -63,6 +63,8 @@\n #define ACC100_QMGR_INVALID_IDX -1\n #define ACC100_QMGR_RR 1\n #define ACC100_QOS_GBR 0\n+#define ACC101PF_DRIVER_NAME (\"intel_acc101_pf\")\n+#define ACC101VF_DRIVER_NAME (\"intel_acc101_vf\")\n #endif\n \n #define OPS_CACHE_SIZE 256U\n@@ -711,11 +713,12 @@ typedef int (test_case_function)(struct active_device *ad,\n #endif\n #ifdef RTE_BASEBAND_ACC100\n \tif ((get_init_device() == true) &&\n-\t\t(!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME))) {\n+\t\t\t((!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) ||\n+\t\t\t(!strcmp(info->drv.driver_name, ACC101PF_DRIVER_NAME)))) {\n \t\tstruct rte_acc100_conf conf;\n \t\tunsigned int i;\n \n-\t\tprintf(\"Configure ACC100 FEC Driver %s with default values\\n\",\n+\t\tprintf(\"Configure ACC100/ACC101 FEC Driver %s with default values\\n\",\n \t\t\t\tinfo->drv.driver_name);\n \n \t\t/* clear default configuration before initialization */\n@@ -760,10 +763,17 @@ typedef int (test_case_function)(struct active_device *ad,\n \t\tconf.q_dl_5g.aq_depth_log2 = ACC100_QMGR_AQ_DEPTH;\n \n \t\t/* setup PF with configuration information */\n-\t\tret = rte_acc100_configure(info->dev_name, &conf);\n-\t\tTEST_ASSERT_SUCCESS(ret,\n-\t\t\t\t\"Failed to configure ACC100 PF for bbdev %s\",\n-\t\t\t\tinfo->dev_name);\n+\t\tif (!strcmp(info->drv.driver_name, ACC100PF_DRIVER_NAME)) {\n+\t\t\tret = rte_acc100_configure(info->dev_name, &conf);\n+\t\t\tTEST_ASSERT_SUCCESS(ret,\n+\t\t\t\t\t\"Failed to configure ACC100 PF for bbdev %s\",\n+\t\t\t\t\tinfo->dev_name);\n+\t\t} else {\n+\t\t\tret = rte_acc101_configure(info->dev_name, &conf);\n+\t\t\tTEST_ASSERT_SUCCESS(ret,\n+\t\t\t\t\t\"Failed to configure ACC101 PF for bbdev %s\",\n+\t\t\t\t\tinfo->dev_name);\n+\t\t}\n \t}\n #endif\n \t/* Let's refresh this now this is configured */\ndiff --git a/drivers/baseband/acc100/rte_acc100_cfg.h b/drivers/baseband/acc100/rte_acc100_cfg.h\nindex d233e42..2e3c43f 100644\n--- a/drivers/baseband/acc100/rte_acc100_cfg.h\n+++ b/drivers/baseband/acc100/rte_acc100_cfg.h\n@@ -106,6 +106,23 @@ struct rte_acc100_conf {\n int\n rte_acc100_configure(const char *dev_name, struct rte_acc100_conf *conf);\n \n+/**\n+ * Configure a ACC101 device\n+ *\n+ * @param dev_name\n+ * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.\n+ * It can also be retrieved for a bbdev device from the dev_name field in the\n+ * rte_bbdev_info structure returned by rte_bbdev_info_get().\n+ * @param conf\n+ * Configuration to apply to ACC101 HW.\n+ *\n+ * @return\n+ * Zero on success, negative value on failure.\n+ */\n+__rte_experimental\n+int\n+rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf);\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c\nindex 65b8fac..decd01d 100644\n--- a/drivers/baseband/acc100/rte_acc100_pmd.c\n+++ b/drivers/baseband/acc100/rte_acc100_pmd.c\n@@ -5004,3 +5004,305 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n \trte_bbdev_log_debug(\"PF Tip configuration complete for %s\", dev_name);\n \treturn 0;\n }\n+\n+\n+/* Initial configuration of a ACC101 device prior to running configure() */\n+int\n+rte_acc101_configure(const char *dev_name, struct rte_acc100_conf *conf)\n+{\n+\trte_bbdev_log(INFO, \"rte_acc101_configure\");\n+\tuint32_t value, address, status;\n+\tint qg_idx, template_idx, vf_idx, acc, i;\n+\tstruct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);\n+\n+\t/* Compile time checks */\n+\tRTE_BUILD_BUG_ON(sizeof(struct acc100_dma_req_desc) != 256);\n+\tRTE_BUILD_BUG_ON(sizeof(union acc100_dma_desc) != 256);\n+\tRTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_td) != 24);\n+\tRTE_BUILD_BUG_ON(sizeof(struct acc100_fcw_te) != 32);\n+\n+\tif (bbdev == NULL) {\n+\t\trte_bbdev_log(ERR,\n+\t\t\"Invalid dev_name (%s), or device is not yet initialised\",\n+\t\tdev_name);\n+\t\treturn -ENODEV;\n+\t}\n+\tstruct acc100_device *d = bbdev->data->dev_private;\n+\n+\t/* Store configuration */\n+\trte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));\n+\n+\t/* PCIe Bridge configuration */\n+\tacc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC101_CFG_PCI_BRIDGE);\n+\tfor (i = 1; i < ACC101_GPEX_AXIMAP_NUM; i++)\n+\t\tacc100_reg_write(d, HwPfPcieGpexAxiAddrMappingWindowPexBaseHigh + i * 16, 0);\n+\n+\t/* Prevent blocking AXI read on BRESP for AXI Write */\n+\taddress = HwPfPcieGpexAxiPioControl;\n+\tvalue = ACC101_CFG_PCI_AXI;\n+\tacc100_reg_write(d, address, value);\n+\n+\t/* Explicitly releasing AXI including a 2ms delay on ACC101 */\n+\tusleep(2000);\n+\tacc100_reg_write(d, HWPfDmaAxiControl, 1);\n+\n+\t/* Set the default 5GDL DMA configuration */\n+\tacc100_reg_write(d, HWPfDmaInboundDrainDataSize, ACC101_DMA_INBOUND);\n+\n+\t/* Enable granular dynamic clock gating */\n+\taddress = HWPfHiClkGateHystReg;\n+\tvalue = ACC101_CLOCK_GATING_EN;\n+\tacc100_reg_write(d, address, value);\n+\n+\t/* Set default descriptor signature */\n+\taddress = HWPfDmaDescriptorSignatuture;\n+\tvalue = 0;\n+\tacc100_reg_write(d, address, value);\n+\n+\t/* Enable the Error Detection in DMA */\n+\tvalue = ACC101_CFG_DMA_ERROR;\n+\taddress = HWPfDmaErrorDetectionEn;\n+\tacc100_reg_write(d, address, value);\n+\n+\t/* AXI Cache configuration */\n+\tvalue = ACC101_CFG_AXI_CACHE;\n+\taddress = HWPfDmaAxcacheReg;\n+\tacc100_reg_write(d, address, value);\n+\n+\t/* Default DMA Configuration (Qmgr Enabled) */\n+\taddress = HWPfDmaConfig0Reg;\n+\tvalue = 0;\n+\tacc100_reg_write(d, address, value);\n+\taddress = HWPfDmaQmanen;\n+\tvalue = 0;\n+\tacc100_reg_write(d, address, value);\n+\n+\t/* Default RLIM/ALEN configuration */\n+\taddress = HWPfDmaConfig1Reg;\n+\tint alen_r = 0xF;\n+\tint alen_w = 0x7;\n+\tvalue = (1 << 31) + (alen_w << 20) + (1 << 6) + alen_r;\n+\tacc100_reg_write(d, address, value);\n+\n+\t/* Configure DMA Qmanager addresses */\n+\taddress = HWPfDmaQmgrAddrReg;\n+\tvalue = HWPfQmgrEgressQueuesTemplate;\n+\tacc100_reg_write(d, address, value);\n+\n+\t/* ===== Qmgr Configuration ===== */\n+\t/* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */\n+\tint totalQgs = conf->q_ul_4g.num_qgroups +\n+\t\t\tconf->q_ul_5g.num_qgroups +\n+\t\t\tconf->q_dl_4g.num_qgroups +\n+\t\t\tconf->q_dl_5g.num_qgroups;\n+\tfor (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {\n+\t\taddress = HWPfQmgrDepthLog2Grp +\n+\t\tACC101_BYTES_IN_WORD * qg_idx;\n+\t\tvalue = aqDepth(qg_idx, conf);\n+\t\tacc100_reg_write(d, address, value);\n+\t\taddress = HWPfQmgrTholdGrp +\n+\t\tACC101_BYTES_IN_WORD * qg_idx;\n+\t\tvalue = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));\n+\t\tacc100_reg_write(d, address, value);\n+\t}\n+\n+\t/* Template Priority in incremental order */\n+\tfor (template_idx = 0; template_idx < ACC101_NUM_TMPL;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg0Indx + ACC101_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC101_TMPL_PRI_0;\n+\t\tacc100_reg_write(d, address, value);\n+\t\taddress = HWPfQmgrGrpTmplateReg1Indx + ACC101_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC101_TMPL_PRI_1;\n+\t\tacc100_reg_write(d, address, value);\n+\t\taddress = HWPfQmgrGrpTmplateReg2indx + ACC101_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC101_TMPL_PRI_2;\n+\t\tacc100_reg_write(d, address, value);\n+\t\taddress = HWPfQmgrGrpTmplateReg3Indx + ACC101_BYTES_IN_WORD * template_idx;\n+\t\tvalue = ACC101_TMPL_PRI_3;\n+\t\tacc100_reg_write(d, address, value);\n+\t}\n+\n+\taddress = HWPfQmgrGrpPriority;\n+\tvalue = ACC101_CFG_QMGR_HI_P;\n+\tacc100_reg_write(d, address, value);\n+\n+\t/* Template Configuration */\n+\tfor (template_idx = 0; template_idx < ACC101_NUM_TMPL;\n+\t\t\ttemplate_idx++) {\n+\t\tvalue = 0;\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ ACC101_BYTES_IN_WORD * template_idx;\n+\t\tacc100_reg_write(d, address, value);\n+\t}\n+\t/* 4GUL */\n+\tint numQgs = conf->q_ul_4g.num_qgroups;\n+\tint numQqsAcc = 0;\n+\tvalue = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = ACC101_SIG_UL_4G;\n+\t\t\ttemplate_idx <= ACC101_SIG_UL_4G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ ACC101_BYTES_IN_WORD * template_idx;\n+\t\tacc100_reg_write(d, address, value);\n+\t}\n+\t/* 5GUL */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_ul_5g.num_qgroups;\n+\tvalue = 0;\n+\tint numEngines = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = ACC101_SIG_UL_5G;\n+\t\t\ttemplate_idx <= ACC101_SIG_UL_5G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\t/* Check engine power-on status */\n+\t\taddress = HwPfFecUl5gIbDebugReg +\n+\t\t\t\tACC101_ENGINE_OFFSET * template_idx;\n+\t\tstatus = (acc100_reg_read(d, address) >> 4) & 0xF;\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ ACC101_BYTES_IN_WORD * template_idx;\n+\t\tif (status == 1) {\n+\t\t\tacc100_reg_write(d, address, value);\n+\t\t\tnumEngines++;\n+\t\t} else\n+\t\t\tacc100_reg_write(d, address, 0);\n+#if RTE_ACC101_SINGLE_FEC == 1\n+\t\tvalue = 0;\n+#endif\n+\t}\n+\tprintf(\"Number of 5GUL engines %d\\n\", numEngines);\n+\t/* 4GDL */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_dl_4g.num_qgroups;\n+\tvalue = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = ACC101_SIG_DL_4G;\n+\t\t\ttemplate_idx <= ACC101_SIG_DL_4G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ ACC101_BYTES_IN_WORD * template_idx;\n+\t\tacc100_reg_write(d, address, value);\n+#if RTE_ACC101_SINGLE_FEC == 1\n+\t\t\tvalue = 0;\n+#endif\n+\t}\n+\t/* 5GDL */\n+\tnumQqsAcc += numQgs;\n+\tnumQgs\t= conf->q_dl_5g.num_qgroups;\n+\tvalue = 0;\n+\tfor (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)\n+\t\tvalue |= (1 << qg_idx);\n+\tfor (template_idx = ACC101_SIG_DL_5G;\n+\t\t\ttemplate_idx <= ACC101_SIG_DL_5G_LAST;\n+\t\t\ttemplate_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg4Indx\n+\t\t\t\t+ ACC101_BYTES_IN_WORD * template_idx;\n+\t\tacc100_reg_write(d, address, value);\n+#if RTE_ACC101_SINGLE_FEC == 1\n+\t\tvalue = 0;\n+#endif\n+\t}\n+\n+\t/* Queue Group Function mapping */\n+\tint qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};\n+\taddress = HWPfQmgrGrpFunction0;\n+\tvalue = 0;\n+\tfor (qg_idx = 0; qg_idx < 8; qg_idx++) {\n+\t\tacc = accFromQgid(qg_idx, conf);\n+\t\tvalue |= qman_func_id[acc]<<(qg_idx * 4);\n+\t}\n+\tacc100_reg_write(d, address, value);\n+\n+\t/* Configuration of the Arbitration QGroup depth to 1 */\n+\tfor (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {\n+\t\taddress = HWPfQmgrArbQDepthGrp +\n+\t\tACC101_BYTES_IN_WORD * qg_idx;\n+\t\tvalue = 0;\n+\t\tacc100_reg_write(d, address, value);\n+\t}\n+\n+\t/* Enabling AQueues through the Queue hierarchy*/\n+\tfor (vf_idx = 0; vf_idx < ACC101_NUM_VFS; vf_idx++) {\n+\t\tfor (qg_idx = 0; qg_idx < ACC101_NUM_QGRPS; qg_idx++) {\n+\t\t\tvalue = 0;\n+\t\t\tif (vf_idx < conf->num_vf_bundles &&\n+\t\t\t\t\tqg_idx < totalQgs)\n+\t\t\t\tvalue = (1 << aqNum(qg_idx, conf)) - 1;\n+\t\t\taddress = HWPfQmgrAqEnableVf\n+\t\t\t\t\t+ vf_idx * ACC101_BYTES_IN_WORD;\n+\t\t\tvalue += (qg_idx << 16);\n+\t\t\tacc100_reg_write(d, address, value);\n+\t\t}\n+\t}\n+\n+\t/* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */\n+\tuint32_t aram_address = 0;\n+\tfor (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {\n+\t\tfor (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {\n+\t\t\taddress = HWPfQmgrVfBaseAddr + vf_idx\n+\t\t\t\t\t* ACC101_BYTES_IN_WORD + qg_idx\n+\t\t\t\t\t* ACC101_BYTES_IN_WORD * 64;\n+\t\t\tvalue = aram_address;\n+\t\t\tacc100_reg_write(d, address, value);\n+\t\t\t/* Offset ARAM Address for next memory bank\n+\t\t\t * - increment of 4B\n+\t\t\t */\n+\t\t\taram_address += aqNum(qg_idx, conf) *\n+\t\t\t\t\t(1 << aqDepth(qg_idx, conf));\n+\t\t}\n+\t}\n+\n+\tif (aram_address > ACC101_WORDS_IN_ARAM_SIZE) {\n+\t\trte_bbdev_log(ERR, \"ARAM Configuration not fitting %d %d\\n\",\n+\t\t\t\taram_address, ACC101_WORDS_IN_ARAM_SIZE);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* ==== HI Configuration ==== */\n+\n+\t/* No Info Ring/MSI by default */\n+\tacc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);\n+\tacc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);\n+\tacc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);\n+\tacc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);\n+\t/* Prevent Block on Transmit Error */\n+\taddress = HWPfHiBlockTransmitOnErrorEn;\n+\tvalue = 0;\n+\tacc100_reg_write(d, address, value);\n+\t/* Prevents to drop MSI */\n+\taddress = HWPfHiMsiDropEnableReg;\n+\tvalue = 0;\n+\tacc100_reg_write(d, address, value);\n+\t/* Set the PF Mode register */\n+\taddress = HWPfHiPfMode;\n+\tvalue = (conf->pf_mode_en) ? ACC101_PF_VAL : 0;\n+\tacc100_reg_write(d, address, value);\n+\t/* Explicitly releasing AXI after PF Mode and 2 ms */\n+\tusleep(2000);\n+\tacc100_reg_write(d, HWPfDmaAxiControl, 1);\n+\n+\t/* QoS overflow init */\n+\tvalue = 1;\n+\taddress = HWPfQosmonAEvalOverflow0;\n+\tacc100_reg_write(d, address, value);\n+\taddress = HWPfQosmonBEvalOverflow0;\n+\tacc100_reg_write(d, address, value);\n+\n+\t/* HARQ DDR Configuration */\n+\tunsigned int ddrSizeInMb = ACC101_HARQ_DDR;\n+\tfor (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {\n+\t\taddress = HWPfDmaVfDdrBaseRw + vf_idx\n+\t\t\t\t* 0x10;\n+\t\tvalue = ((vf_idx * (ddrSizeInMb / 64)) << 16) +\n+\t\t\t\t(ddrSizeInMb - 1);\n+\t\tacc100_reg_write(d, address, value);\n+\t}\n+\tusleep(ACC101_LONG_WAIT);\n+\n+\trte_bbdev_log_debug(\"PF TIP configuration complete for %s\", dev_name);\n+\treturn 0;\n+}\ndiff --git a/drivers/baseband/acc100/version.map b/drivers/baseband/acc100/version.map\nindex 40604c7..37b850f 100644\n--- a/drivers/baseband/acc100/version.map\n+++ b/drivers/baseband/acc100/version.map\n@@ -6,5 +6,5 @@ EXPERIMENTAL {\n \tglobal:\n \n \trte_acc100_configure;\n-\n+\trte_acc101_configure;\n };\n", "prefixes": [ "v4", "5/5" ] }