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GET /api/patches/111653/?format=api
{ "id": 111653, "url": "http://patches.dpdk.org/api/patches/111653/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1653341116-50325-2-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1653341116-50325-2-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1653341116-50325-2-git-send-email-nicolas.chautru@intel.com", "date": "2022-05-23T21:25:12", "name": "[v4,1/5] baseband/acc100: update companion PF configure function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "340e5f453c4da66b9fe9c6c9aea829e97dfe74a0", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1653341116-50325-2-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 23103, "url": "http://patches.dpdk.org/api/series/23103/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23103", "date": "2022-05-23T21:25:13", "name": "drivers/baseband: PMD to support ACC100/ACC101 devices", "version": 4, "mbox": "http://patches.dpdk.org/series/23103/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/111653/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/111653/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 01A5FA00C2;\n\tMon, 23 May 2022 23:34:25 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 297D142B6C;\n\tMon, 23 May 2022 23:34:08 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by mails.dpdk.org (Postfix) with ESMTP id 8BFD94067B;\n Mon, 23 May 2022 23:34:04 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 May 2022 14:33:58 -0700", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by fmsmga008.fm.intel.com with ESMTP; 23 May 2022 14:33:56 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1653341644; x=1684877644;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=kbK4Q1BQ6WkHndgLrdzVnCfWf4jFzb8itFrx1CEfqrI=;\n b=f82YYHuYeP2n7y3dlD2MkH6LsDlA1IoahI8uJMZfQ8w5jF/Ru1RHOsZ3\n T/6S1nuQMHNdUxnJGccLg+0j59868EouTvSzc1XsB8NpKJteVVzVodlDM\n jtI2wFuWqWgrgm4yxTDo/o0zy3yhSa8NvxJwXC23G8OKpWm0CxFOtZAlj\n 8MTq/GzwihXHBlh2/zbIDzqgzCyTkBw3DliH+nOq9Gki5+t6BzSDqBGUJ\n rrdVDfeQ34JFKivpVqwiHbNn/EchX2ro2DnZ3wL+7Out6MoZHMI8qSEWe\n uHQvlu4MUWZuN5u7yHs6itSU99btgbnI1wtMdJvUPwQYA08cXJiTydW9x A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10356\"; a=\"336419939\"", "E=Sophos;i=\"5.91,247,1647327600\"; d=\"scan'208\";a=\"336419939\"", "E=Sophos;i=\"5.91,247,1647327600\"; d=\"scan'208\";a=\"629591631\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,\n maxime.coquelin@redhat.com", "Cc": "thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com,\n hemant.agrawal@nxp.com, hernan.vargas@intel.com, david.marchand@redhat.com,\n Nicolas Chautru <nicolas.chautru@intel.com>, stable@dpdk.org", "Subject": "[PATCH v4 1/5] baseband/acc100: update companion PF configure\n function", "Date": "Mon, 23 May 2022 14:25:12 -0700", "Message-Id": "<1653341116-50325-2-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1653341116-50325-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1651083423-33202-1-git-send-email-nicolas.chautru@intel.com>\n <1653341116-50325-1-git-send-email-nicolas.chautru@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Update of the device configuration function from PF used for bbdev-test\nto latest sequence for ACC199 PRQ device and matching version in\npf_bb_config 22.03.\n\nFixes: b17d70922d5d (\"baseband/acc100: add configure function\")\nCc: stable@dpdk.org\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n drivers/baseband/acc100/acc100_pf_enum.h | 18 ++++\n drivers/baseband/acc100/rte_acc100_pmd.c | 150 ++++++++++++++++++++++++-------\n drivers/baseband/acc100/rte_acc100_pmd.h | 15 ++++\n 3 files changed, 151 insertions(+), 32 deletions(-)", "diff": "diff --git a/drivers/baseband/acc100/acc100_pf_enum.h b/drivers/baseband/acc100/acc100_pf_enum.h\nindex a1ee416..2fba667 100644\n--- a/drivers/baseband/acc100/acc100_pf_enum.h\n+++ b/drivers/baseband/acc100/acc100_pf_enum.h\n@@ -238,6 +238,24 @@ enum {\n \tHWPfPermonBTotalLatLowBusMon = 0x00BAC504,\n \tHWPfPermonBTotalLatUpperBusMon = 0x00BAC508,\n \tHWPfPermonBTotalReqCntBusMon = 0x00BAC50C,\n+\tHwPfFabI2MArbCntrlReg = 0x00BB0000,\n+\tHWPfFabricMode = 0x00BB1000,\n+\tHwPfFabI2MGrp0DebugReg = 0x00BBF000,\n+\tHwPfFabI2MGrp1DebugReg = 0x00BBF004,\n+\tHwPfFabI2MGrp2DebugReg = 0x00BBF008,\n+\tHwPfFabI2MGrp3DebugReg = 0x00BBF00C,\n+\tHwPfFabI2MBuf0DebugReg = 0x00BBF010,\n+\tHwPfFabI2MBuf1DebugReg = 0x00BBF014,\n+\tHwPfFabI2MBuf2DebugReg = 0x00BBF018,\n+\tHwPfFabI2MBuf3DebugReg = 0x00BBF01C,\n+\tHwPfFabM2IBuf0Grp0DebugReg = 0x00BBF020,\n+\tHwPfFabM2IBuf1Grp0DebugReg = 0x00BBF024,\n+\tHwPfFabM2IBuf0Grp1DebugReg = 0x00BBF028,\n+\tHwPfFabM2IBuf1Grp1DebugReg = 0x00BBF02C,\n+\tHwPfFabM2IBuf0Grp2DebugReg = 0x00BBF030,\n+\tHwPfFabM2IBuf1Grp2DebugReg = 0x00BBF034,\n+\tHwPfFabM2IBuf0Grp3DebugReg = 0x00BBF038,\n+\tHwPfFabM2IBuf1Grp3DebugReg = 0x00BBF03C,\n \tHWPfFecUl5gCntrlReg = 0x00BC0000,\n \tHWPfFecUl5gI2MThreshReg = 0x00BC0004,\n \tHWPfFecUl5gVersionReg = 0x00BC0100,\ndiff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c\nindex de7e4bc..9135c0e 100644\n--- a/drivers/baseband/acc100/rte_acc100_pmd.c\n+++ b/drivers/baseband/acc100/rte_acc100_pmd.c\n@@ -4411,7 +4411,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n {\n \trte_bbdev_log(INFO, \"rte_acc100_configure\");\n \tuint32_t value, address, status;\n-\tint qg_idx, template_idx, vf_idx, acc, i;\n+\tint qg_idx, template_idx, vf_idx, acc, i, j;\n \tstruct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);\n \n \t/* Compile time checks */\n@@ -4431,6 +4431,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n \t/* Store configuration */\n \trte_memcpy(&d->acc100_conf, conf, sizeof(d->acc100_conf));\n \n+\tvalue = acc100_reg_read(d, HwPfPcieGpexBridgeControl);\n+\tbool firstCfg = (value != ACC100_CFG_PCI_BRIDGE);\n+\n \t/* PCIe Bridge configuration */\n \tacc100_reg_write(d, HwPfPcieGpexBridgeControl, ACC100_CFG_PCI_BRIDGE);\n \tfor (i = 1; i < ACC100_GPEX_AXIMAP_NUM; i++)\n@@ -4451,20 +4454,9 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n \tvalue = 1;\n \tacc100_reg_write(d, address, value);\n \n-\t/* DDR Configuration */\n-\taddress = HWPfDdrBcTim6;\n-\tvalue = acc100_reg_read(d, address);\n-\tvalue &= 0xFFFFFFFB; /* Bit 2 */\n-#ifdef ACC100_DDR_ECC_ENABLE\n-\tvalue |= 0x4;\n-#endif\n-\tacc100_reg_write(d, address, value);\n-\taddress = HWPfDdrPhyDqsCountNum;\n-#ifdef ACC100_DDR_ECC_ENABLE\n-\tvalue = 9;\n-#else\n-\tvalue = 8;\n-#endif\n+\t/* Enable granular dynamic clock gating */\n+\taddress = HWPfHiClkGateHystReg;\n+\tvalue = ACC100_CLOCK_GATING_EN;\n \tacc100_reg_write(d, address, value);\n \n \t/* Set default descriptor signature */\n@@ -4482,6 +4474,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n \taddress = HWPfDmaAxcacheReg;\n \tacc100_reg_write(d, address, value);\n \n+\t/* Adjust PCIe Lane adaptation */\n+\tfor (i = 0; i < ACC100_QUAD_NUMS; i++)\n+\t\tfor (j = 0; j < ACC100_LANES_PER_QUAD; j++)\n+\t\t\tacc100_reg_write(d, HwPfPcieLnAdaptctrl + i * ACC100_PCIE_QUAD_OFFSET\n+\t\t\t\t\t+ j * ACC100_PCIE_LANE_OFFSET, ACC100_ADAPT);\n+\n+\t/* Enable PCIe live adaptation */\n+\tfor (i = 0; i < ACC100_QUAD_NUMS; i++)\n+\t\tacc100_reg_write(d, HwPfPciePcsEqControl +\n+\t\t\t\ti * ACC100_PCIE_QUAD_OFFSET, ACC100_PCS_EQ);\n+\n \t/* Default DMA Configuration (Qmgr Enabled) */\n \taddress = HWPfDmaConfig0Reg;\n \tvalue = 0;\n@@ -4500,6 +4503,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n \tvalue = HWPfQmgrEgressQueuesTemplate;\n \tacc100_reg_write(d, address, value);\n \n+\t/* Default Fabric Mode */\n+\taddress = HWPfFabricMode;\n+\tvalue = ACC100_FABRIC_MODE;\n+\tacc100_reg_write(d, address, value);\n+\n \t/* ===== Qmgr Configuration ===== */\n \t/* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */\n \tint totalQgs = conf->q_ul_4g.num_qgroups +\n@@ -4518,22 +4526,17 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n \t}\n \n \t/* Template Priority in incremental order */\n-\tfor (template_idx = 0; template_idx < ACC100_NUM_TMPL;\n-\t\t\ttemplate_idx++) {\n-\t\taddress = HWPfQmgrGrpTmplateReg0Indx +\n-\t\tACC100_BYTES_IN_WORD * (template_idx % 8);\n+\tfor (template_idx = 0; template_idx < ACC100_NUM_TMPL; template_idx++) {\n+\t\taddress = HWPfQmgrGrpTmplateReg0Indx + ACC100_BYTES_IN_WORD * template_idx;\n \t\tvalue = ACC100_TMPL_PRI_0;\n \t\tacc100_reg_write(d, address, value);\n-\t\taddress = HWPfQmgrGrpTmplateReg1Indx +\n-\t\tACC100_BYTES_IN_WORD * (template_idx % 8);\n+\t\taddress = HWPfQmgrGrpTmplateReg1Indx + ACC100_BYTES_IN_WORD * template_idx;\n \t\tvalue = ACC100_TMPL_PRI_1;\n \t\tacc100_reg_write(d, address, value);\n-\t\taddress = HWPfQmgrGrpTmplateReg2indx +\n-\t\tACC100_BYTES_IN_WORD * (template_idx % 8);\n+\t\taddress = HWPfQmgrGrpTmplateReg2indx + ACC100_BYTES_IN_WORD * template_idx;\n \t\tvalue = ACC100_TMPL_PRI_2;\n \t\tacc100_reg_write(d, address, value);\n-\t\taddress = HWPfQmgrGrpTmplateReg3Indx +\n-\t\tACC100_BYTES_IN_WORD * (template_idx % 8);\n+\t\taddress = HWPfQmgrGrpTmplateReg3Indx + ACC100_BYTES_IN_WORD * template_idx;\n \t\tvalue = ACC100_TMPL_PRI_3;\n \t\tacc100_reg_write(d, address, value);\n \t}\n@@ -4623,7 +4626,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n \t}\n \n \t/* Queue Group Function mapping */\n-\tint qman_func_id[5] = {0, 2, 1, 3, 4};\n+\tint qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};\n \taddress = HWPfQmgrGrpFunction0;\n \tvalue = 0;\n \tfor (qg_idx = 0; qg_idx < 8; qg_idx++) {\n@@ -4654,7 +4657,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n \t\t}\n \t}\n \n-\t/* This pointer to ARAM (256kB) is shifted by 2 (4B per register) */\n+\t/* This pointer to ARAM (128kB) is shifted by 2 (4B per register) */\n \tuint32_t aram_address = 0;\n \tfor (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {\n \t\tfor (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {\n@@ -4679,6 +4682,11 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n \n \t/* ==== HI Configuration ==== */\n \n+\t/* No Info Ring/MSI by default */\n+\tacc100_reg_write(d, HWPfHiInfoRingIntWrEnRegPf, 0);\n+\tacc100_reg_write(d, HWPfHiInfoRingVf2pfLoWrEnReg, 0);\n+\tacc100_reg_write(d, HWPfHiCfgMsiIntWrEnRegPf, 0xFFFFFFFF);\n+\tacc100_reg_write(d, HWPfHiCfgMsiVf2pfLoWrEnReg, 0xFFFFFFFF);\n \t/* Prevent Block on Transmit Error */\n \taddress = HWPfHiBlockTransmitOnErrorEn;\n \tvalue = 0;\n@@ -4691,10 +4699,6 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n \taddress = HWPfHiPfMode;\n \tvalue = (conf->pf_mode_en) ? ACC100_PF_VAL : 0;\n \tacc100_reg_write(d, address, value);\n-\t/* Enable Error Detection in HW */\n-\taddress = HWPfDmaErrorDetectionEn;\n-\tvalue = 0x3D7;\n-\tacc100_reg_write(d, address, value);\n \n \t/* QoS overflow init */\n \tvalue = 1;\n@@ -4704,7 +4708,7 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n \tacc100_reg_write(d, address, value);\n \n \t/* HARQ DDR Configuration */\n-\tunsigned int ddrSizeInMb = 512; /* Fixed to 512 MB per VF for now */\n+\tunsigned int ddrSizeInMb = ACC100_HARQ_DDR;\n \tfor (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {\n \t\taddress = HWPfDmaVfDdrBaseRw + vf_idx\n \t\t\t\t* 0x10;\n@@ -4718,6 +4722,88 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n \tif (numEngines < (ACC100_SIG_UL_5G_LAST + 1))\n \t\tpoweron_cleanup(bbdev, d, conf);\n \n+\tuint32_t version = 0;\n+\tfor (i = 0; i < 4; i++)\n+\t\tversion += acc100_reg_read(d,\n+\t\t\t\tHWPfDdrPhyIdtmFwVersion + 4 * i) << (8 * i);\n+\tif (version != ACC100_PRQ_DDR_VER) {\n+\t\tprintf(\"* Note: Not on DDR PRQ version %8x != %08x\\n\",\n+\t\t\t\tversion, ACC100_PRQ_DDR_VER);\n+\t} else if (firstCfg) {\n+\t\t/* ---- DDR configuration at boot up --- */\n+\t\t/* Read Clear Ddr training status */\n+\t\tacc100_reg_read(d, HWPfChaDdrStDoneStatus);\n+\t\t/* Reset PHY/IDTM/UMMC */\n+\t\tacc100_reg_write(d, HWPfChaDdrWbRstCfg, 3);\n+\t\tacc100_reg_write(d, HWPfChaDdrApbRstCfg, 2);\n+\t\tacc100_reg_write(d, HWPfChaDdrPhyRstCfg, 2);\n+\t\tacc100_reg_write(d, HWPfChaDdrCpuRstCfg, 3);\n+\t\tacc100_reg_write(d, HWPfChaDdrSifRstCfg, 2);\n+\t\tusleep(ACC100_MS_IN_US);\n+\t\t/* Reset WB and APB resets */\n+\t\tacc100_reg_write(d, HWPfChaDdrWbRstCfg, 2);\n+\t\tacc100_reg_write(d, HWPfChaDdrApbRstCfg, 3);\n+\t\t/* Configure PHY-IDTM */\n+\t\tacc100_reg_write(d, HWPfDdrPhyIdletimeout, 0x3e8);\n+\t\t/* IDTM timing registers */\n+\t\tacc100_reg_write(d, HWPfDdrPhyRdLatency, 0x13);\n+\t\tacc100_reg_write(d, HWPfDdrPhyRdLatencyDbi, 0x15);\n+\t\tacc100_reg_write(d, HWPfDdrPhyWrLatency, 0x10011);\n+\t\t/* Configure SDRAM MRS registers */\n+\t\tacc100_reg_write(d, HWPfDdrPhyMr01Dimm, 0x3030b70);\n+\t\tacc100_reg_write(d, HWPfDdrPhyMr01DimmDbi, 0x3030b50);\n+\t\tacc100_reg_write(d, HWPfDdrPhyMr23Dimm, 0x30);\n+\t\tacc100_reg_write(d, HWPfDdrPhyMr67Dimm, 0xc00);\n+\t\tacc100_reg_write(d, HWPfDdrPhyMr45Dimm, 0x4000000);\n+\t\t/* Configure active lanes */\n+\t\tacc100_reg_write(d, HWPfDdrPhyDqsCountMax, 0x9);\n+\t\tacc100_reg_write(d, HWPfDdrPhyDqsCountNum, 0x9);\n+\t\t/* Configure WR/RD leveling timing registers */\n+\t\tacc100_reg_write(d, HWPfDdrPhyWrlvlWwRdlvlRr, 0x101212);\n+\t\t/* Configure what trainings to execute */\n+\t\tacc100_reg_write(d, HWPfDdrPhyTrngType, 0x2d3c);\n+\t\t/* Releasing PHY reset */\n+\t\tacc100_reg_write(d, HWPfChaDdrPhyRstCfg, 3);\n+\t\t/* Configure Memory Controller registers */\n+\t\tacc100_reg_write(d, HWPfDdrMemInitPhyTrng0, 0x3);\n+\t\tacc100_reg_write(d, HWPfDdrBcDram, 0x3c232003);\n+\t\tacc100_reg_write(d, HWPfDdrBcAddrMap, 0x31);\n+\t\t/* Configure UMMC BC timing registers */\n+\t\tacc100_reg_write(d, HWPfDdrBcRef, 0xa22);\n+\t\tacc100_reg_write(d, HWPfDdrBcTim0, 0x4050501);\n+\t\tacc100_reg_write(d, HWPfDdrBcTim1, 0xf0b0476);\n+\t\tacc100_reg_write(d, HWPfDdrBcTim2, 0x103);\n+\t\tacc100_reg_write(d, HWPfDdrBcTim3, 0x144050a1);\n+\t\tacc100_reg_write(d, HWPfDdrBcTim4, 0x23300);\n+\t\tacc100_reg_write(d, HWPfDdrBcTim5, 0x4230276);\n+\t\tacc100_reg_write(d, HWPfDdrBcTim6, 0x857914);\n+\t\tacc100_reg_write(d, HWPfDdrBcTim7, 0x79100232);\n+\t\tacc100_reg_write(d, HWPfDdrBcTim8, 0x100007ce);\n+\t\tacc100_reg_write(d, HWPfDdrBcTim9, 0x50020);\n+\t\tacc100_reg_write(d, HWPfDdrBcTim10, 0x40ee);\n+\t\t/* Configure UMMC DFI timing registers */\n+\t\tacc100_reg_write(d, HWPfDdrDfiInit, 0x5000);\n+\t\tacc100_reg_write(d, HWPfDdrDfiTim0, 0x15030006);\n+\t\tacc100_reg_write(d, HWPfDdrDfiTim1, 0x11305);\n+\t\tacc100_reg_write(d, HWPfDdrDfiPhyUpdEn, 0x1);\n+\t\tacc100_reg_write(d, HWPfDdrUmmcIntEn, 0x1f);\n+\t\t/* Release IDTM CPU out of reset */\n+\t\tacc100_reg_write(d, HWPfChaDdrCpuRstCfg, 0x2);\n+\t\t/* Wait PHY-IDTM to finish static training */\n+\t\tfor (i = 0; i < ACC100_DDR_TRAINING_MAX; i++) {\n+\t\t\tusleep(ACC100_MS_IN_US);\n+\t\t\tvalue = acc100_reg_read(d,\n+\t\t\t\t\tHWPfChaDdrStDoneStatus);\n+\t\t\tif (value & 1)\n+\t\t\t\tbreak;\n+\t\t}\n+\t\tprintf(\"DDR Training completed in %d ms\", i);\n+\t\t/* Enable Memory Controller */\n+\t\tacc100_reg_write(d, HWPfDdrUmmcCtrl, 0x401);\n+\t\t/* Release AXI interface reset */\n+\t\tacc100_reg_write(d, HWPfChaDdrSifRstCfg, 3);\n+\t}\n+\n \trte_bbdev_log_debug(\"PF Tip configuration complete for %s\", dev_name);\n \treturn 0;\n }\ndiff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h\nindex cbcece2..8fea322 100644\n--- a/drivers/baseband/acc100/rte_acc100_pmd.h\n+++ b/drivers/baseband/acc100/rte_acc100_pmd.h\n@@ -153,6 +153,12 @@\n #define ACC100_CFG_QMGR_HI_P 0x0F0F\n #define ACC100_CFG_PCI_AXI 0xC003\n #define ACC100_CFG_PCI_BRIDGE 0x40006033\n+#define ACC100_QUAD_NUMS 4\n+#define ACC100_LANES_PER_QUAD 4\n+#define ACC100_PCIE_LANE_OFFSET 0x200\n+#define ACC100_PCIE_QUAD_OFFSET 0x2000\n+#define ACC100_PCS_EQ 0x6007\n+#define ACC100_ADAPT 0x8400\n #define ACC100_ENGINE_OFFSET 0x1000\n #define ACC100_RESET_HI 0x20100\n #define ACC100_RESET_LO 0x20000\n@@ -160,6 +166,15 @@\n #define ACC100_ENGINES_MAX 9\n #define ACC100_LONG_WAIT 1000\n #define ACC100_GPEX_AXIMAP_NUM 17\n+#define ACC100_CLOCK_GATING_EN 0x30000\n+#define ACC100_FABRIC_MODE 0xB\n+/* DDR Size per VF - 512MB by default\n+ * Can be increased up to 4 GB with single PF/VF\n+ */\n+#define ACC100_HARQ_DDR (512 * 1)\n+#define ACC100_PRQ_DDR_VER 0x10092020\n+#define ACC100_MS_IN_US (1000)\n+#define ACC100_DDR_TRAINING_MAX (5000)\n \n /* ACC100 DMA Descriptor triplet */\n struct acc100_dma_triplet {\n", "prefixes": [ "v4", "1/5" ] }