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GET /api/patches/111652/?format=api
{ "id": 111652, "url": "http://patches.dpdk.org/api/patches/111652/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/1653341116-50325-4-git-send-email-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1653341116-50325-4-git-send-email-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1653341116-50325-4-git-send-email-nicolas.chautru@intel.com", "date": "2022-05-23T21:25:14", "name": "[v4,3/5] baseband/acc100: introduce PMD for ACC101", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "114c77e0cca95e3eaf185122324ec6fa5d4b90a6", "submitter": { "id": 1314, "url": "http://patches.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 6690, "url": "http://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/1653341116-50325-4-git-send-email-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 23103, "url": "http://patches.dpdk.org/api/series/23103/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23103", "date": "2022-05-23T21:25:13", "name": "drivers/baseband: PMD to support ACC100/ACC101 devices", "version": 4, "mbox": "http://patches.dpdk.org/series/23103/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/111652/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/111652/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 54CF4A00C2;\n\tMon, 23 May 2022 23:34:18 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 268F64280B;\n\tMon, 23 May 2022 23:34:07 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id 30F3240156\n for <dev@dpdk.org>; Mon, 23 May 2022 23:34:04 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 23 May 2022 14:33:58 -0700", "from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210])\n by fmsmga008.fm.intel.com with ESMTP; 23 May 2022 14:33:56 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1653341644; x=1684877644;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=S+bkexHiwHXf1AB2qFD0rDbuPS5O2zMbgdoz84TqsCo=;\n b=Gmt2z50YgGQ4LZgqg7fqRVmNXgmQNaLPt/GhNJAm0qR4XGg16DiWSYcj\n z68XL6o7+7yoyRhoYBt1QiwoiSlXxcxmfbZgr/WCNNJN6+4xS1SvnGfg2\n h7qXXPLvmW4mMqAn5OAFuHzFGvSxRXFpPIKvB/vCLta5QldhcEfKoS0MO\n AGsGPp5OS6t0NBlrOJ2J3yQCzJ/wSGY0j+2/nYSxRwq7ij+cT/Xz16zLA\n 2Hji4JmTfqH20nIF2ITxF5hskmz2ahYcP7uyGhJfA1eSnbe3nwoewE9o6\n I6i3ygZR6reyzanq652lv2CjroVBzUL8yYnK48Wh58Qig74qc1Pt3O3QJ g==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10356\"; a=\"272183539\"", "E=Sophos;i=\"5.91,247,1647327600\"; d=\"scan'208\";a=\"272183539\"", "E=Sophos;i=\"5.91,247,1647327600\"; d=\"scan'208\";a=\"629591638\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org, gakhil@marvell.com, trix@redhat.com,\n maxime.coquelin@redhat.com", "Cc": "thomas@monjalon.net, ray.kinsella@intel.com, bruce.richardson@intel.com,\n hemant.agrawal@nxp.com, hernan.vargas@intel.com, david.marchand@redhat.com,\n Nicolas Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v4 3/5] baseband/acc100: introduce PMD for ACC101", "Date": "Mon, 23 May 2022 14:25:14 -0700", "Message-Id": "<1653341116-50325-4-git-send-email-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1653341116-50325-1-git-send-email-nicolas.chautru@intel.com>", "References": "<1651083423-33202-1-git-send-email-nicolas.chautru@intel.com>\n <1653341116-50325-1-git-send-email-nicolas.chautru@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Support for ACC101 as a derivative of ACC100.\nReusing existing code when possible.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\n---\n MAINTAINERS | 1 +\n doc/guides/bbdevs/acc100.rst | 37 ++++--\n doc/guides/bbdevs/features/acc101.ini | 13 +++\n doc/guides/bbdevs/index.rst | 1 +\n doc/guides/rel_notes/release_22_07.rst | 3 +\n drivers/baseband/acc100/rte_acc100_pmd.c | 187 ++++++++++++++++++++++++++++++-\n drivers/baseband/acc100/rte_acc100_pmd.h | 11 ++\n drivers/baseband/acc100/rte_acc101_pmd.h | 59 ++++++++++\n 8 files changed, 294 insertions(+), 18 deletions(-)\n create mode 100644 doc/guides/bbdevs/features/acc101.ini\n create mode 100644 drivers/baseband/acc100/rte_acc101_pmd.h", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 17a0559..0610128 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1318,6 +1318,7 @@ F: doc/guides/bbdevs/features/fpga_5gnr_fec.ini\n F: drivers/baseband/acc100/\n F: doc/guides/bbdevs/acc100.rst\n F: doc/guides/bbdevs/features/acc100.ini\n+F: doc/guides/bbdevs/features/acc101.ini\n \n Null baseband\n M: Nicolas Chautru <nicolas.chautru@intel.com>\ndiff --git a/doc/guides/bbdevs/acc100.rst b/doc/guides/bbdevs/acc100.rst\nindex 9fff6ab..ff07ed9 100644\n--- a/doc/guides/bbdevs/acc100.rst\n+++ b/doc/guides/bbdevs/acc100.rst\n@@ -1,17 +1,19 @@\n .. SPDX-License-Identifier: BSD-3-Clause\n Copyright(c) 2020 Intel Corporation\n \n-Intel(R) ACC100 5G/4G FEC Poll Mode Driver\n-==========================================\n+Intel(R) ACC100 and ACC101 5G/4G FEC Poll Mode Drivers\n+======================================================\n \n The BBDEV ACC100 5G/4G FEC poll mode driver (PMD) supports an\n implementation of a VRAN FEC wireless acceleration function.\n This device is also known as Mount Bryce.\n+The BBDEV ACC101, also known as Mount Cirrus, is a derivative device from Mount Bryce\n+with functional and capacity improvements but still with the same exposed BBDEV capabilities.\n \n Features\n --------\n \n-ACC100 5G/4G FEC PMD supports the following features:\n+ACC100 and ACC101 5G/4G FEC PMDs support the following features:\n \n - LDPC Encode in the DL (5GNR)\n - LDPC Decode in the UL (5GNR)\n@@ -23,7 +25,7 @@ ACC100 5G/4G FEC PMD supports the following features:\n - MSI\n - SR-IOV\n \n-ACC100 5G/4G FEC PMD supports the following BBDEV capabilities:\n+ACC100 and ACC101 5G/4G FEC PMDs support the following BBDEV capabilities:\n \n * For the LDPC encode operation:\n - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH`` : set to attach CRC24B to CB(s)\n@@ -80,14 +82,16 @@ hugepage configuration of a server may be examined using:\n Initialization\n --------------\n \n-When the device first powers up, its PCI Physical Functions (PF) can be listed through this command:\n+When the device first powers up, its PCI Physical Functions (PF) can be listed through these\n+commands for ACC100 and ACC101 respectively:\n \n .. code-block:: console\n \n sudo lspci -vd8086:0d5c\n+ sudo lspci -vd8086:57c4\n \n The physical and virtual functions are compatible with Linux UIO drivers:\n-``vfio`` and ``igb_uio``. However, in order to work the ACC100 5G/4G\n+``vfio`` and ``igb_uio``. However, in order to work the 5G/4G\n FEC device first needs to be bound to one of these linux drivers through DPDK.\n \n \n@@ -97,7 +101,8 @@ Bind PF UIO driver(s)\n Install the DPDK igb_uio driver, bind it with the PF PCI device ID and use\n ``lspci`` to confirm the PF device is under use by ``igb_uio`` DPDK UIO driver.\n \n-The igb_uio driver may be bound to the PF PCI device using one of two methods:\n+The igb_uio driver may be bound to the PF PCI device using one of two methods for ACC100\n+(for ACC101 the device id ``57c4`` should be used in lieu of ``0d5c``):\n \n \n 1. PCI functions (physical or virtual, depending on the use case) can be bound to\n@@ -121,7 +126,7 @@ the UIO driver by repeating this command for every function.\n where the PCI device ID (example: 0000:06:00.0) is obtained using lspci -vd8086:0d5c\n \n \n-In a similar way the ACC100 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.\n+In a similar way the 5G/4G FEC PF may be bound with vfio-pci as any PCIe device.\n \n \n Enable Virtual Functions\n@@ -167,14 +172,14 @@ queues, priorities, load balance, bandwidth and other settings necessary for the\n device to perform FEC functions.\n \n This configuration needs to be executed at least once after reboot or PCI FLR and can\n-be achieved by using the function ``acc100_configure()``, which sets up the\n-parameters defined in ``acc100_conf`` structure.\n+be achieved by using the functions ``acc100_configure()`` or ``acc101_configure()``,\n+which sets up the parameters defined in the compatible ``acc100_conf`` structure.\n \n Test Application\n ----------------\n \n BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing\n-the functionality of ACC100 5G/4G FEC encode and decode, depending on the device's\n+the functionality of the device 5G/4G FEC encode and decode, depending on the device's\n capabilities. The test application is located under app->test-bbdev folder and has the\n following options:\n \n@@ -212,7 +217,7 @@ Test Vectors\n \n In addition to the simple LDPC decoder and LDPC encoder tests, bbdev also provides\n a range of additional tests under the test_vectors folder, which may be useful. The results\n-of these tests will depend on the ACC100 5G/4G FEC capabilities which may cause some\n+of these tests will depend on the device 5G/4G FEC capabilities which may cause some\n testcases to be skipped, but no failure should be reported.\n \n \n@@ -233,3 +238,11 @@ Specifically for the BBDEV ACC100 PMD, the command below can be used:\n \n ./pf_bb_config ACC100 -c acc100/acc100_config_vf_5g.cfg\n ./test-bbdev.py -e=\"-c 0xff0 -a${VF_PCI_ADDR}\" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data\n+\n+Specifically for the BBDEV ACC101 PMD, the command below can be used:\n+\n+.. code-block:: console\n+\n+ ./pf_bb_config ACC101 -c acc101/acc101_config_2vf_4g5g.cfg\n+ ./test-bbdev.py -e=\"-c 0xff0 -a${VF_PCI_ADDR}\" -c validation -n 64 -b 32 -l 1 -v ./ldpc_dec_default.data\n+\ndiff --git a/doc/guides/bbdevs/features/acc101.ini b/doc/guides/bbdevs/features/acc101.ini\nnew file mode 100644\nindex 0000000..0e2c21a\n--- /dev/null\n+++ b/doc/guides/bbdevs/features/acc101.ini\n@@ -0,0 +1,13 @@\n+;\n+; Supported features of the 'acc101' bbdev driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Turbo Decoder (4G) = Y\n+Turbo Encoder (4G) = Y\n+LDPC Decoder (5G) = Y\n+LDPC Encoder (5G) = Y\n+LLR/HARQ Compression = Y\n+External DDR Access = Y\n+HW Accelerated = Y\ndiff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst\nindex cedd706..e76883c 100644\n--- a/doc/guides/bbdevs/index.rst\n+++ b/doc/guides/bbdevs/index.rst\n@@ -14,4 +14,5 @@ Baseband Device Drivers\n fpga_lte_fec\n fpga_5gnr_fec\n acc100\n+ acc101\n la12xx\ndiff --git a/doc/guides/rel_notes/release_22_07.rst b/doc/guides/rel_notes/release_22_07.rst\nindex e49cace..1803947 100644\n--- a/doc/guides/rel_notes/release_22_07.rst\n+++ b/doc/guides/rel_notes/release_22_07.rst\n@@ -104,6 +104,9 @@ New Features\n * ``RTE_EVENT_QUEUE_ATTR_WEIGHT``\n * ``RTE_EVENT_QUEUE_ATTR_AFFINITY``\n \n+* **Added Intel ACC101 baseband PMD.**\n+\n+ * Added a new baseband PMD for Intel ACC101 device.\n \n Removed Items\n -------------\ndiff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c\nindex 3fdf17d..5f422da 100644\n--- a/drivers/baseband/acc100/rte_acc100_pmd.c\n+++ b/drivers/baseband/acc100/rte_acc100_pmd.c\n@@ -22,6 +22,7 @@\n #include <rte_bbdev.h>\n #include <rte_bbdev_pmd.h>\n #include \"rte_acc100_pmd.h\"\n+#include \"rte_acc101_pmd.h\"\n \n #ifdef RTE_LIBRTE_BBDEV_DEBUG\n RTE_LOG_REGISTER_DEFAULT(acc100_logtype, DEBUG);\n@@ -1288,9 +1289,15 @@\n \t\t\tRTE_BBDEV_TURBO_HALF_ITERATION_EVEN);\n }\n \n+static inline bool\n+is_acc100(struct acc100_queue *q)\n+{\n+\treturn (q->d->device_variant == ACC100_VARIANT);\n+}\n+\n /* Fill in a frame control word for LDPC decoding. */\n static inline void\n-acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,\n+acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,\n \t\tunion acc100_harq_layout_data *harq_layout)\n {\n \tuint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;\n@@ -1414,6 +1421,128 @@\n \t}\n }\n \n+/* Convert offset to harq index for harq_layout structure */\n+static inline uint32_t hq_index(uint32_t offset)\n+{\n+\treturn (offset >> ACC100_HARQ_OFFSET_SHIFT) & ACC100_HARQ_OFFSET_MASK;\n+}\n+\n+/* Fill in a frame control word for LDPC decoding for ACC101 */\n+static inline void\n+acc101_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw,\n+\t\tunion acc100_harq_layout_data *harq_layout)\n+{\n+\tuint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset;\n+\tuint32_t harq_index;\n+\tuint32_t l;\n+\n+\tfcw->qm = op->ldpc_dec.q_m;\n+\tfcw->nfiller = op->ldpc_dec.n_filler;\n+\tfcw->BG = (op->ldpc_dec.basegraph - 1);\n+\tfcw->Zc = op->ldpc_dec.z_c;\n+\tfcw->ncb = op->ldpc_dec.n_cb;\n+\tfcw->k0 = get_k0(fcw->ncb, fcw->Zc, op->ldpc_dec.basegraph,\n+\t\t\top->ldpc_dec.rv_index);\n+\tif (op->ldpc_dec.code_block_mode == RTE_BBDEV_CODE_BLOCK)\n+\t\tfcw->rm_e = op->ldpc_dec.cb_params.e;\n+\telse\n+\t\tfcw->rm_e = (op->ldpc_dec.tb_params.r <\n+\t\t\t\top->ldpc_dec.tb_params.cab) ?\n+\t\t\t\t\t\top->ldpc_dec.tb_params.ea :\n+\t\t\t\t\t\top->ldpc_dec.tb_params.eb;\n+\n+\tif (unlikely(check_bit(op->ldpc_dec.op_flags,\n+\t\t\tRTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE) &&\n+\t\t\t(op->ldpc_dec.harq_combined_input.length == 0))) {\n+\t\trte_bbdev_log(WARNING, \"Null HARQ input size provided\");\n+\t\t/* Disable HARQ input in that case to carry forward */\n+\t\top->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE;\n+\t}\n+\n+\tfcw->hcin_en = check_bit(op->ldpc_dec.op_flags,\n+\t\t\tRTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE);\n+\tfcw->hcout_en = check_bit(op->ldpc_dec.op_flags,\n+\t\t\tRTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE);\n+\tfcw->crc_select = check_bit(op->ldpc_dec.op_flags,\n+\t\t\tRTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK);\n+\tfcw->bypass_dec = check_bit(op->ldpc_dec.op_flags,\n+\t\t\tRTE_BBDEV_LDPC_DECODE_BYPASS);\n+\tfcw->bypass_intlv = check_bit(op->ldpc_dec.op_flags,\n+\t\t\tRTE_BBDEV_LDPC_DEINTERLEAVER_BYPASS);\n+\tif (op->ldpc_dec.q_m == 1) {\n+\t\tfcw->bypass_intlv = 1;\n+\t\tfcw->qm = 2;\n+\t}\n+\tfcw->hcin_decomp_mode = check_bit(op->ldpc_dec.op_flags,\n+\t\t\tRTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);\n+\tfcw->hcout_comp_mode = check_bit(op->ldpc_dec.op_flags,\n+\t\t\tRTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION);\n+\tfcw->llr_pack_mode = check_bit(op->ldpc_dec.op_flags,\n+\t\t\tRTE_BBDEV_LDPC_LLR_COMPRESSION);\n+\tharq_index = hq_index(op->ldpc_dec.harq_combined_output.offset);\n+\tif (fcw->hcin_en > 0) {\n+\t\tharq_in_length = op->ldpc_dec.harq_combined_input.length;\n+\t\tif (fcw->hcin_decomp_mode > 0)\n+\t\t\tharq_in_length = harq_in_length * 8 / 6;\n+\t\tharq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb\n+\t\t\t\t- op->ldpc_dec.n_filler);\n+\t\t/* Alignment on next 64B - Already enforced from HC output */\n+\t\tharq_in_length = RTE_ALIGN_FLOOR(harq_in_length, 64);\n+\t\tfcw->hcin_size0 = harq_in_length;\n+\t\tfcw->hcin_offset = 0;\n+\t\tfcw->hcin_size1 = 0;\n+\t} else {\n+\t\tfcw->hcin_size0 = 0;\n+\t\tfcw->hcin_offset = 0;\n+\t\tfcw->hcin_size1 = 0;\n+\t}\n+\n+\tfcw->itmax = op->ldpc_dec.iter_max;\n+\tfcw->itstop = check_bit(op->ldpc_dec.op_flags,\n+\t\t\tRTE_BBDEV_LDPC_ITERATION_STOP_ENABLE);\n+\tfcw->synd_precoder = fcw->itstop;\n+\t/*\n+\t * These are all implicitly set\n+\t * fcw->synd_post = 0;\n+\t * fcw->so_en = 0;\n+\t * fcw->so_bypass_rm = 0;\n+\t * fcw->so_bypass_intlv = 0;\n+\t * fcw->dec_convllr = 0;\n+\t * fcw->hcout_convllr = 0;\n+\t * fcw->hcout_size1 = 0;\n+\t * fcw->so_it = 0;\n+\t * fcw->hcout_offset = 0;\n+\t * fcw->negstop_th = 0;\n+\t * fcw->negstop_it = 0;\n+\t * fcw->negstop_en = 0;\n+\t * fcw->gain_i = 1;\n+\t * fcw->gain_h = 1;\n+\t */\n+\tif (fcw->hcout_en > 0) {\n+\t\tparity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8)\n+\t\t\t* op->ldpc_dec.z_c - op->ldpc_dec.n_filler;\n+\t\tk0_p = (fcw->k0 > parity_offset) ?\n+\t\t\t\tfcw->k0 - op->ldpc_dec.n_filler : fcw->k0;\n+\t\tncb_p = fcw->ncb - op->ldpc_dec.n_filler;\n+\t\tl = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX);\n+\t\tharq_out_length = (uint16_t) fcw->hcin_size0;\n+\t\tharq_out_length = RTE_MAX(harq_out_length, l);\n+\t\t/* Cannot exceed the pruned Ncb circular buffer */\n+\t\tharq_out_length = RTE_MIN(harq_out_length, ncb_p);\n+\t\t/* Alignment on next 64B */\n+\t\tharq_out_length = RTE_ALIGN_CEIL(harq_out_length, 64);\n+\t\tfcw->hcout_size0 = harq_out_length;\n+\t\tfcw->hcout_size1 = 0;\n+\t\tfcw->hcout_offset = 0;\n+\t\tharq_layout[harq_index].offset = fcw->hcout_offset;\n+\t\tharq_layout[harq_index].size0 = fcw->hcout_size0;\n+\t} else {\n+\t\tfcw->hcout_size0 = 0;\n+\t\tfcw->hcout_size1 = 0;\n+\t\tfcw->hcout_offset = 0;\n+\t}\n+}\n+\n /**\n * Fills descriptor with data pointers of one block type.\n *\n@@ -2966,7 +3095,7 @@\n \t\tstruct acc100_fcw_ld *fcw;\n \t\tuint32_t seg_total_left;\n \t\tfcw = &desc->req.fcw_ld;\n-\t\tacc100_fcw_ld_fill(op, fcw, harq_layout);\n+\t\tq->d->fcw_ld_fill(op, fcw, harq_layout);\n \n \t\t/* Special handling when overusing mbuf */\n \t\tif (fcw->rm_e < ACC100_MAX_E_MBUF)\n@@ -3033,7 +3162,7 @@\n \tdesc = q->ring_addr + desc_idx;\n \tuint64_t fcw_offset = (desc_idx << 8) + ACC100_DESC_FCW_OFFSET;\n \tunion acc100_harq_layout_data *harq_layout = q->d->harq_layout;\n-\tacc100_fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);\n+\tq->d->fcw_ld_fill(op, &desc->req.fcw_ld, harq_layout);\n \n \tinput = op->ldpc_dec.input.data;\n \th_output_head = h_output = op->ldpc_dec.hard_output.data;\n@@ -4145,9 +4274,19 @@\n \tdev->dequeue_ldpc_enc_ops = acc100_dequeue_ldpc_enc;\n \tdev->dequeue_ldpc_dec_ops = acc100_dequeue_ldpc_dec;\n \n-\t((struct acc100_device *) dev->data->dev_private)->pf_device =\n-\t\t\t!strcmp(drv->driver.name,\n-\t\t\t\t\tRTE_STR(ACC100PF_DRIVER_NAME));\n+\tif ((!strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME))) ||\n+\t\t\t(!strcmp(drv->driver.name, RTE_STR(ACC100VF_DRIVER_NAME)))) {\n+\t\t((struct acc100_device *) dev->data->dev_private)->pf_device =\n+\t\t\t\t!strcmp(drv->driver.name, RTE_STR(ACC100PF_DRIVER_NAME));\n+\t\t((struct acc100_device *) dev->data->dev_private)->device_variant = ACC100_VARIANT;\n+\t\t((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill = acc100_fcw_ld_fill;\n+\t} else {\n+\t\t((struct acc100_device *) dev->data->dev_private)->pf_device =\n+\t\t\t\t!strcmp(drv->driver.name, RTE_STR(ACC101PF_DRIVER_NAME));\n+\t\t((struct acc100_device *) dev->data->dev_private)->device_variant = ACC101_VARIANT;\n+\t\t((struct acc100_device *) dev->data->dev_private)->fcw_ld_fill = acc101_fcw_ld_fill;\n+\t}\n+\n \t((struct acc100_device *) dev->data->dev_private)->mmio_base =\n \t\t\tpci_dev->mem_resource[0].addr;\n \n@@ -4257,6 +4396,42 @@ static int acc100_pci_remove(struct rte_pci_device *pci_dev)\n RTE_PMD_REGISTER_PCI(ACC100VF_DRIVER_NAME, acc100_pci_vf_driver);\n RTE_PMD_REGISTER_PCI_TABLE(ACC100VF_DRIVER_NAME, pci_id_acc100_vf_map);\n \n+/* ACC101 PCI PF address map */\n+static struct rte_pci_id pci_id_acc101_pf_map[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_PF_DEVICE_ID)\n+\t},\n+\t{.device_id = 0},\n+};\n+\n+/* ACC101 PCI VF address map */\n+static struct rte_pci_id pci_id_acc101_vf_map[] = {\n+\t{\n+\t\tRTE_PCI_DEVICE(RTE_ACC101_VENDOR_ID, RTE_ACC101_VF_DEVICE_ID)\n+\t},\n+\t{.device_id = 0},\n+};\n+\n+\n+static struct rte_pci_driver acc101_pci_pf_driver = {\n+\t\t.probe = acc100_pci_probe,\n+\t\t.remove = acc100_pci_remove,\n+\t\t.id_table = pci_id_acc101_pf_map,\n+\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING\n+};\n+\n+static struct rte_pci_driver acc101_pci_vf_driver = {\n+\t\t.probe = acc100_pci_probe,\n+\t\t.remove = acc100_pci_remove,\n+\t\t.id_table = pci_id_acc101_vf_map,\n+\t\t.drv_flags = RTE_PCI_DRV_NEED_MAPPING\n+};\n+\n+RTE_PMD_REGISTER_PCI(ACC101PF_DRIVER_NAME, acc101_pci_pf_driver);\n+RTE_PMD_REGISTER_PCI_TABLE(ACC101PF_DRIVER_NAME, pci_id_acc101_pf_map);\n+RTE_PMD_REGISTER_PCI(ACC101VF_DRIVER_NAME, acc101_pci_vf_driver);\n+RTE_PMD_REGISTER_PCI_TABLE(ACC101VF_DRIVER_NAME, pci_id_acc101_vf_map);\n+\n /*\n * Workaround implementation to fix the power on status of some 5GUL engines\n * This requires DMA permission if ported outside DPDK\ndiff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h\nindex 8fea322..39d5f22 100644\n--- a/drivers/baseband/acc100/rte_acc100_pmd.h\n+++ b/drivers/baseband/acc100/rte_acc100_pmd.h\n@@ -22,6 +22,9 @@\n #define rte_bbdev_log_debug(fmt, ...)\n #endif\n \n+#define ACC100_VARIANT 0\n+#define ACC101_VARIANT 1\n+\n /* ACC100 PF and VF driver names */\n #define ACC100PF_DRIVER_NAME intel_acc100_pf\n #define ACC100VF_DRIVER_NAME intel_acc100_vf\n@@ -67,6 +70,8 @@\n #define ACC100_HARQ_LAYOUT (64*1024*1024)\n /* Assume offset for HARQ in memory */\n #define ACC100_HARQ_OFFSET (32*1024)\n+#define ACC100_HARQ_OFFSET_SHIFT 15\n+#define ACC100_HARQ_OFFSET_MASK 0x7ffffff\n /* Mask used to calculate an index in an Info Ring array (not a byte offset) */\n #define ACC100_INFO_RING_MASK (ACC100_INFO_RING_NUM_ENTRIES-1)\n /* Number of Virtual Functions ACC100 supports */\n@@ -574,6 +579,10 @@ struct __rte_cache_aligned acc100_queue {\n \tstruct acc100_device *d;\n };\n \n+typedef void (*acc10x_fcw_ld_fill_fun_t)(struct rte_bbdev_dec_op *op,\n+\t\tstruct acc100_fcw_ld *fcw,\n+\t\tunion acc100_harq_layout_data *harq_layout);\n+\n /* Private data structure for each ACC100 device */\n struct acc100_device {\n \tvoid *mmio_base; /**< Base address of MMIO registers (BAR0) */\n@@ -605,6 +614,8 @@ struct acc100_device {\n \tuint16_t q_assigned_bit_map[ACC100_NUM_QGRPS];\n \tbool pf_device; /**< True if this is a PF ACC100 device */\n \tbool configured; /**< True if this ACC100 device is configured */\n+\tuint16_t device_variant; /**< Device variant */\n+\tacc10x_fcw_ld_fill_fun_t fcw_ld_fill; /**< 5GUL FCW generation function */\n };\n \n /**\ndiff --git a/drivers/baseband/acc100/rte_acc101_pmd.h b/drivers/baseband/acc100/rte_acc101_pmd.h\nnew file mode 100644\nindex 0000000..3e419cb\n--- /dev/null\n+++ b/drivers/baseband/acc100/rte_acc101_pmd.h\n@@ -0,0 +1,59 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2022 Intel Corporation\n+ */\n+\n+/* ACC101 PF and VF driver names */\n+#define ACC101PF_DRIVER_NAME intel_acc101_pf\n+#define ACC101VF_DRIVER_NAME intel_acc101_vf\n+\n+/* ACC101 PCI vendor & device IDs */\n+#define RTE_ACC101_VENDOR_ID (0x8086)\n+#define RTE_ACC101_PF_DEVICE_ID (0x57c4)\n+#define RTE_ACC101_VF_DEVICE_ID (0x57c5)\n+\n+/* Define as 1 to use only a single FEC engine */\n+#ifndef RTE_ACC101_SINGLE_FEC\n+#define RTE_ACC101_SINGLE_FEC 0\n+#endif\n+\n+/* Number of Virtual Functions ACC101 supports */\n+#define ACC101_NUM_VFS 16\n+#define ACC101_NUM_QGRPS 8\n+#define ACC101_NUM_AQS 16\n+/* All ACC101 Registers alignment are 32bits = 4B */\n+#define ACC101_BYTES_IN_WORD 4\n+\n+#define ACC101_TMPL_PRI_0 0x03020100\n+#define ACC101_TMPL_PRI_1 0x07060504\n+#define ACC101_TMPL_PRI_2 0x0b0a0908\n+#define ACC101_TMPL_PRI_3 0x0f0e0d0c\n+#define ACC101_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)\n+\n+#define ACC101_NUM_TMPL 32\n+/* Mapping of signals for the available engines */\n+#define ACC101_SIG_UL_5G 0\n+#define ACC101_SIG_UL_5G_LAST 8\n+#define ACC101_SIG_DL_5G 13\n+#define ACC101_SIG_DL_5G_LAST 15\n+#define ACC101_SIG_UL_4G 16\n+#define ACC101_SIG_UL_4G_LAST 19\n+#define ACC101_SIG_DL_4G 27\n+#define ACC101_SIG_DL_4G_LAST 31\n+#define ACC101_NUM_ACCS 5\n+#define ACC101_PF_VAL 2\n+\n+/* ACC101 Configuration */\n+#define ACC101_CFG_DMA_ERROR 0x3D7\n+#define ACC101_CFG_AXI_CACHE 0x11\n+#define ACC101_CFG_QMGR_HI_P 0x0F0F\n+#define ACC101_CFG_PCI_AXI 0xC003\n+#define ACC101_CFG_PCI_BRIDGE 0x40006033\n+#define ACC101_ENGINE_OFFSET 0x1000\n+#define ACC101_LONG_WAIT 1000\n+#define ACC101_GPEX_AXIMAP_NUM 17\n+#define ACC101_CLOCK_GATING_EN 0x30000\n+#define ACC101_DMA_INBOUND 0x104\n+/* DDR Size per VF - 512MB by default\n+ * Can be increased up to 4 GB with single PF/VF\n+ */\n+#define ACC101_HARQ_DDR (512 * 1)\n", "prefixes": [ "v4", "3/5" ] }