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GET /api/patches/111458/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 111458,
    "url": "http://patches.dpdk.org/api/patches/111458/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220520023936.259286-2-ke1x.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20220520023936.259286-2-ke1x.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20220520023936.259286-2-ke1x.zhang@intel.com",
    "date": "2022-05-20T02:39:36",
    "name": "[v2,1/1] net/iavf: fix Rx queue interrupt setting",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "e1c2023e039b3700b99d1dfe8ebb82989df53a60",
    "submitter": {
        "id": 2503,
        "url": "http://patches.dpdk.org/api/people/2503/?format=api",
        "name": "Zhang, Ke1X",
        "email": "ke1x.zhang@intel.com"
    },
    "delegate": null,
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220520023936.259286-2-ke1x.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 23051,
            "url": "http://patches.dpdk.org/api/series/23051/?format=api",
            "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=23051",
            "date": "2022-05-20T02:39:35",
            "name": "fix Rx queue interrupt setting",
            "version": 2,
            "mbox": "http://patches.dpdk.org/series/23051/mbox/"
        }
    ],
    "comments": "http://patches.dpdk.org/api/patches/111458/comments/",
    "check": "success",
    "checks": "http://patches.dpdk.org/api/patches/111458/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
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            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 0B244427F0;\n\tFri, 20 May 2022 04:47:05 +0200 (CEST)",
            "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by mails.dpdk.org (Postfix) with ESMTP id BB62B427EB;\n Fri, 20 May 2022 04:47:02 +0200 (CEST)",
            "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 19 May 2022 19:47:01 -0700",
            "from unknown (HELO localhost.localdomain) ([10.239.251.104])\n by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 19 May 2022 19:46:59 -0700"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1653014823; x=1684550823;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=VliCtTAZwEcrdskEvnCggM5MM2M2vsJgI76rGN+bpk4=;\n b=lsRhzrooolIMuhLI8zOYJox+UpVJsLCAMIWgRWhKtVjqtkQLM5mdzs69\n GSSzrEFFS/il21JePMhVIpWHvNvsc4voxPtkf+4dlbZkELv0uT5HtWPBh\n YTfe47quKt4Ru3RUGbr97yNxAJusmRCQWQ+BOZgkmRb7i1VZSjP8juYrf\n lUrwcB7Lcwwe0A0UlJk8eqUDuydKwooxiz2OKtA4676q+VGyZrv5ns0mA\n 9R+GQtydJ/MduzDP+LgaxyFc9TqCTx1Y3RjdHpcXWi/8JuAUAmD2KQQFo\n se507zMuyLy8WfyvXuX9QdIlDwvctd4f3xPTS9phEeSSUHqiaCy93kJ4+ A==;",
        "X-IronPort-AV": [
            "E=McAfee;i=\"6400,9594,10352\"; a=\"272589615\"",
            "E=Sophos;i=\"5.91,238,1647327600\"; d=\"scan'208\";a=\"272589615\"",
            "E=Sophos;i=\"5.91,238,1647327600\"; d=\"scan'208\";a=\"743269062\""
        ],
        "From": "Ke Zhang <ke1x.zhang@intel.com>",
        "To": "xiaoyun.li@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com,\n dev@dpdk.org",
        "Cc": "Ke Zhang <ke1x.zhang@intel.com>,\n\tstable@dpdk.org",
        "Subject": "[PATCH v2 1/1] net/iavf: fix Rx queue interrupt setting",
        "Date": "Fri, 20 May 2022 02:39:36 +0000",
        "Message-Id": "<20220520023936.259286-2-ke1x.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.25.1",
        "In-Reply-To": "<20220520023936.259286-1-ke1x.zhang@intel.com>",
        "References": "<20220425083628.81133-1-ke1x.zhang@intel.com>\n <20220520023936.259286-1-ke1x.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org"
    },
    "content": "For Rx-Queue Interrupt Setting, when vf rx interrupt\ndisable(INTENA=0), there are two ways to write back\ndescriptor to host memory:\n\n1)Set WB_ON_ITR bit 0 to Interrupt Dynamic Control Register:\nCompleted descriptors are posted to host memory according to\nthe internal descriptor cache policy (in other words when a\nfull cache line is available for write-back).\n\nA internal descriptor size is 16 bytes or 32 bytes, a cache\nline size is 64 bytes or 128 bytes from datasheet :\nPCIe Global Config 2 - GLPCI_CNF2 (0x000BE004; RO)\nso the full cache line could contains 4 packets, it means\nNetwork card will send 4 packets to host when a full cache line\nis available.\n\n2)Set WB_ON_ITR bit 1 to Interrupt Dynamic Control Register:\nCompleted descriptors also trigger the ITR. Following ITR\nexpiration, all leftover completed descriptors are posted to\nhost memory.\n\nNetwork card will send packet to host even if only one\ndescriptor is completed.\n\nChanging 1) to 2) to make sure VF send the packet to host even\nif there is only one rx packet is ready in hardware.\n\nFixes: d6bde6b5eae9 (\"net/avf: enable Rx interrupt\")\nCc: stable@dpdk.org\n\nSigned-off-by: Ke Zhang <ke1x.zhang@intel.com>\n---\n drivers/net/iavf/iavf_ethdev.c | 2 +-\n 1 file changed, 1 insertion(+), 1 deletion(-)",
    "diff": "diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c\nindex d6190ac24a..17c7720600 100644\n--- a/drivers/net/iavf/iavf_ethdev.c\n+++ b/drivers/net/iavf/iavf_ethdev.c\n@@ -1833,7 +1833,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)\n \n \tIAVF_WRITE_REG(hw,\n \t\t      IAVF_VFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),\n-\t\t      0);\n+\t\t      IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);\n \n \tIAVF_WRITE_FLUSH(hw);\n \treturn 0;\n",
    "prefixes": [
        "v2",
        "1/1"
    ]
}