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GET /api/patches/111246/?format=api
{ "id": 111246, "url": "http://patches.dpdk.org/api/patches/111246/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220517173941.189330-4-hkalra@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220517173941.189330-4-hkalra@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220517173941.189330-4-hkalra@marvell.com", "date": "2022-05-17T17:39:33", "name": "[04/12] net/octeontx: setting link attributes", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "736afa00fab92019c8e6355ef767e615c769b230", "submitter": { "id": 1182, "url": "http://patches.dpdk.org/api/people/1182/?format=api", "name": "Harman Kalra", "email": "hkalra@marvell.com" }, "delegate": { "id": 1, "url": "http://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220517173941.189330-4-hkalra@marvell.com/mbox/", "series": [ { "id": 22975, "url": "http://patches.dpdk.org/api/series/22975/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22975", "date": "2022-05-17T17:39:30", "name": "[01/12] config: add thundert83 config", "version": 1, "mbox": "http://patches.dpdk.org/series/22975/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/111246/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/111246/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 83ED2A0503;\n\tTue, 17 May 2022 19:40:08 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 42F524282E;\n\tTue, 17 May 2022 19:40:03 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 7772D4282E\n for <dev@dpdk.org>; Tue, 17 May 2022 19:40:02 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 24H9qMSm017700\n for <dev@dpdk.org>; Tue, 17 May 2022 10:40:00 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3g2bxsw8xg-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Tue, 17 May 2022 10:40:00 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Tue, 17 May 2022 10:39:58 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Tue, 17 May 2022 10:39:58 -0700", "from localhost.localdomain (unknown [10.29.52.211])\n by maili.marvell.com (Postfix) with ESMTP id 92A5B3F70A7;\n Tue, 17 May 2022 10:39:57 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : subject\n : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=r49QqWDG9tuMlxHgGDujMnx2/mZ90RYBguqJDtbvli4=;\n b=i1q5JNVranWIwGX+h1byPjjIeU43WmhyysTEEbg9r7r33B52y5WUdKc9QwBV6Py/CJeH\n zfo4N6kBtQXZeG8y2m7LT59sUBg15HkE4Hh0O88kYTf4nqHDMVNqH7tC+9LxRefYmYiY\n W3b0Wj2DaMKi34CrYsttNZEsUl3LyJLPNrBaX0tTWzv7p+oVpC6x/EpUlsdQoVKdWOrp\n E61Ori/sK+U6jMNffY44R9lmph2FY5YiDVnII1QTUokLXkdnXyL7597aWNOaLxM81imc\n 6iNsGbZX3qhb2qxv+b79YFe/3cJc8m3CZW6K15E/t6zyb26ZIphlMOJk78Cv6To8glT7 /w==", "From": "Harman Kalra <hkalra@marvell.com>", "To": "<dev@dpdk.org>, Harman Kalra <hkalra@marvell.com>", "Subject": "[PATCH 04/12] net/octeontx: setting link attributes", "Date": "Tue, 17 May 2022 23:09:33 +0530", "Message-ID": "<20220517173941.189330-4-hkalra@marvell.com>", "X-Mailer": "git-send-email 2.18.0", "In-Reply-To": "<20220517173941.189330-1-hkalra@marvell.com>", "References": "<20220517173941.189330-1-hkalra@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "VH0dwNzLC7DBKyX3SHODtFcQMO4JgCg6", "X-Proofpoint-GUID": "VH0dwNzLC7DBKyX3SHODtFcQMO4JgCg6", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.874,Hydra:6.0.486,FMLib:17.11.64.514\n definitions=2022-05-17_03,2022-05-17_02,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adding support to configure link attributes like speed,\nduplex, negotiation.\n\nSigned-off-by: Harman Kalra <hkalra@marvell.com>\n---\n drivers/net/octeontx/base/octeontx_bgx.c | 19 ++++++\n drivers/net/octeontx/base/octeontx_bgx.h | 12 ++++\n drivers/net/octeontx/octeontx_ethdev.c | 80 ++++++++++++++++++++++--\n 3 files changed, 105 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/net/octeontx/base/octeontx_bgx.c b/drivers/net/octeontx/base/octeontx_bgx.c\nindex ac856ff86d..1c6fa05ebc 100644\n--- a/drivers/net/octeontx/base/octeontx_bgx.c\n+++ b/drivers/net/octeontx/base/octeontx_bgx.c\n@@ -376,3 +376,22 @@ int octeontx_bgx_port_flow_ctrl_cfg(int port,\n done:\n \treturn 0;\n }\n+\n+int octeontx_bgx_port_change_mode(int port,\n+\t\t\t\t octeontx_mbox_bgx_port_change_mode_t *cfg)\n+{\n+\tint len = sizeof(octeontx_mbox_bgx_port_change_mode_t), res;\n+\tocteontx_mbox_bgx_port_change_mode_t conf;\n+\tstruct octeontx_mbox_hdr hdr;\n+\n+\thdr.coproc = OCTEONTX_BGX_COPROC;\n+\thdr.msg = MBOX_BGX_PORT_CHANGE_MODE;\n+\thdr.vfid = port;\n+\n+\tmemcpy(&conf, cfg, len);\n+\tres = octeontx_mbox_send(&hdr, &conf, len, NULL, 0);\n+\tif (res < 0)\n+\t\treturn -EACCES;\n+\n+\treturn res;\n+}\ndiff --git a/drivers/net/octeontx/base/octeontx_bgx.h b/drivers/net/octeontx/base/octeontx_bgx.h\nindex d126a0b7fc..e4cfa3e73a 100644\n--- a/drivers/net/octeontx/base/octeontx_bgx.h\n+++ b/drivers/net/octeontx/base/octeontx_bgx.h\n@@ -37,6 +37,7 @@\n #define MBOX_BGX_PORT_GET_FIFO_CFG\t18\n #define MBOX_BGX_PORT_FLOW_CTRL_CFG\t19\n #define MBOX_BGX_PORT_SET_LINK_STATE\t20\n+#define MBOX_BGX_PORT_CHANGE_MODE\t21\n \n /* BGX port configuration parameters: */\n typedef struct octeontx_mbox_bgx_port_conf {\n@@ -143,6 +144,15 @@ typedef struct octeontx_mbox_bgx_port_fc_cfg {\n \tbgx_port_fc_t fc_cfg;\n } octeontx_mbox_bgx_port_fc_cfg_t;\n \n+/* BGX change mode */\n+typedef struct octeontx_mbox_bgx_port_change_mode {\n+\tuint16_t padding;\n+\tuint8_t qlm_mode;\n+\tbool\t autoneg;\n+\tuint8_t duplex;\n+\tuint32_t speed;\n+} octeontx_mbox_bgx_port_change_mode_t;\n+\n int octeontx_bgx_port_open(int port, octeontx_mbox_bgx_port_conf_t *conf);\n int octeontx_bgx_port_close(int port);\n int octeontx_bgx_port_start(int port);\n@@ -163,6 +173,8 @@ int octeontx_bgx_port_get_fifo_cfg(int port,\n \t\t\t\t octeontx_mbox_bgx_port_fifo_cfg_t *cfg);\n int octeontx_bgx_port_flow_ctrl_cfg(int port,\n \t\t\t\t octeontx_mbox_bgx_port_fc_cfg_t *cfg);\n+int octeontx_bgx_port_change_mode(int port,\n+\t\t\t\t octeontx_mbox_bgx_port_change_mode_t *cfg);\n \n #endif\t/* __OCTEONTX_BGX_H__ */\n \ndiff --git a/drivers/net/octeontx/octeontx_ethdev.c b/drivers/net/octeontx/octeontx_ethdev.c\nindex 6469fd0a96..9b13e22089 100644\n--- a/drivers/net/octeontx/octeontx_ethdev.c\n+++ b/drivers/net/octeontx/octeontx_ethdev.c\n@@ -31,6 +31,9 @@\n */\n uint16_t evdev_refcnt;\n \n+#define OCTEONTX_QLM_MODE_SGMII 7\n+#define OCTEONTX_QLM_MODE_XFI 12\n+\n struct evdev_priv_data {\n \tOFFLOAD_FLAGS; /*Sequence should not be changed */\n } __rte_cache_aligned;\n@@ -50,7 +53,8 @@ enum octeontx_link_speed {\n \tOCTEONTX_LINK_SPEED_40G_R,\n \tOCTEONTX_LINK_SPEED_RESERVE1,\n \tOCTEONTX_LINK_SPEED_QSGMII,\n-\tOCTEONTX_LINK_SPEED_RESERVE2\n+\tOCTEONTX_LINK_SPEED_RESERVE2,\n+\tOCTEONTX_LINK_SPEED_UNKNOWN = 255\n };\n \n RTE_LOG_REGISTER_SUFFIX(otx_net_logtype_mbox, mbox, NOTICE);\n@@ -139,6 +143,7 @@ octeontx_port_open(struct octeontx_nic *nic)\n \tnic->mcast_mode = bgx_port_conf.mcast_mode;\n \tnic->speed\t= bgx_port_conf.mode;\n \n+\tnic->duplex = RTE_ETH_LINK_FULL_DUPLEX;\n \tmemset(&fifo_cfg, 0x0, sizeof(fifo_cfg));\n \n \tres = octeontx_bgx_port_get_fifo_cfg(nic->port_id, &fifo_cfg);\n@@ -171,6 +176,67 @@ octeontx_link_status_print(struct rte_eth_dev *eth_dev,\n \t\t\t\t (int)(eth_dev->data->port_id));\n }\n \n+static inline uint32_t\n+octeontx_parse_link_speeds(uint32_t link_speeds)\n+{\n+\tuint32_t link_speed = OCTEONTX_LINK_SPEED_UNKNOWN;\n+\n+\tif (link_speeds & RTE_ETH_LINK_SPEED_40G)\n+\t\tlink_speed = OCTEONTX_LINK_SPEED_40G_R;\n+\n+\tif (link_speeds & RTE_ETH_LINK_SPEED_10G) {\n+\t\tlink_speed = OCTEONTX_LINK_SPEED_XAUI;\n+\t\tlink_speed |= OCTEONTX_LINK_SPEED_RXAUI;\n+\t\tlink_speed |= OCTEONTX_LINK_SPEED_10G_R;\n+\t}\n+\n+\tif (link_speeds & RTE_ETH_LINK_SPEED_5G)\n+\t\tlink_speed = OCTEONTX_LINK_SPEED_QSGMII;\n+\n+\tif (link_speeds & RTE_ETH_LINK_SPEED_1G)\n+\t\tlink_speed = OCTEONTX_LINK_SPEED_SGMII;\n+\n+\treturn link_speed;\n+}\n+\n+static inline uint8_t\n+octeontx_parse_eth_link_duplex(uint32_t link_speeds)\n+{\n+\tif ((link_speeds & RTE_ETH_LINK_SPEED_10M_HD) ||\n+\t\t\t(link_speeds & RTE_ETH_LINK_SPEED_100M_HD))\n+\t\treturn RTE_ETH_LINK_HALF_DUPLEX;\n+\telse\n+\t\treturn RTE_ETH_LINK_FULL_DUPLEX;\n+}\n+\n+static int\n+octeontx_apply_link_speed(struct rte_eth_dev *dev)\n+{\n+\tstruct octeontx_nic *nic = octeontx_pmd_priv(dev);\n+\tstruct rte_eth_conf *conf = &dev->data->dev_conf;\n+\tocteontx_mbox_bgx_port_change_mode_t cfg;\n+\n+\tif (conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG)\n+\t\treturn 0;\n+\n+\tcfg.speed = octeontx_parse_link_speeds(conf->link_speeds);\n+\tcfg.autoneg = (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) ? 1 : 0;\n+\tcfg.duplex = octeontx_parse_eth_link_duplex(conf->link_speeds);\n+\tcfg.qlm_mode = ((conf->link_speeds & RTE_ETH_LINK_SPEED_1G) ?\n+\t\t\tOCTEONTX_QLM_MODE_SGMII :\n+\t\t\t(conf->link_speeds & RTE_ETH_LINK_SPEED_10G) ?\n+\t\t\tOCTEONTX_QLM_MODE_XFI : 0);\n+\n+\tif (cfg.speed != OCTEONTX_LINK_SPEED_UNKNOWN &&\n+\t (cfg.speed != nic->speed || cfg.duplex != nic->duplex)) {\n+\t\tnic->speed = cfg.speed;\n+\t\tnic->duplex = cfg.duplex;\n+\t\treturn octeontx_bgx_port_change_mode(nic->port_id, &cfg);\n+\t} else {\n+\t\treturn 0;\n+\t}\n+}\n+\n static void\n octeontx_link_status_update(struct octeontx_nic *nic,\n \t\t\t struct rte_eth_link *link)\n@@ -440,11 +506,6 @@ octeontx_dev_configure(struct rte_eth_dev *dev)\n \t\ttxmode->offloads |= RTE_ETH_TX_OFFLOAD_MT_LOCKFREE;\n \t}\n \n-\tif (conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) {\n-\t\tocteontx_log_err(\"setting link speed/duplex not supported\");\n-\t\treturn -EINVAL;\n-\t}\n-\n \tif (conf->dcb_capability_en) {\n \t\tocteontx_log_err(\"DCB enable not supported\");\n \t\treturn -EINVAL;\n@@ -621,6 +682,13 @@ octeontx_dev_start(struct rte_eth_dev *dev)\n \t\tgoto error;\n \t}\n \n+\t/* Apply new link configurations if changed */\n+\tret = octeontx_apply_link_speed(dev);\n+\tif (ret) {\n+\t\tocteontx_log_err(\"Failed to set link configuration: %d\", ret);\n+\t\tgoto error;\n+\t}\n+\n \t/*\n \t * Tx start\n \t */\n", "prefixes": [ "04/12" ] }