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GET /api/patches/111192/?format=api
{ "id": 111192, "url": "http://patches.dpdk.org/api/patches/111192/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/a9f5244c8171226cfb37db4a8dbe2ea164937c7b.1652722314.git.sthotton@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<a9f5244c8171226cfb37db4a8dbe2ea164937c7b.1652722314.git.sthotton@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/a9f5244c8171226cfb37db4a8dbe2ea164937c7b.1652722314.git.sthotton@marvell.com", "date": "2022-05-16T17:35:50", "name": "[v4,4/5] common/cnxk: use lock when accessing mbox of SSO", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "300a027c469aaa33915420b5b90b901bba852bb8", "submitter": { "id": 2049, "url": "http://patches.dpdk.org/api/people/2049/?format=api", "name": "Shijith Thotton", "email": "sthotton@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/a9f5244c8171226cfb37db4a8dbe2ea164937c7b.1652722314.git.sthotton@marvell.com/mbox/", "series": [ { "id": 22956, "url": "http://patches.dpdk.org/api/series/22956/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22956", "date": "2022-05-16T17:35:46", "name": "Extend and set event queue attributes at runtime", "version": 4, "mbox": "http://patches.dpdk.org/series/22956/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/111192/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/111192/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 58396A00BE;\n\tMon, 16 May 2022 19:39:41 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1AA3C42B6B;\n\tMon, 16 May 2022 19:39:36 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 38F4A42B5B\n for <dev@dpdk.org>; Mon, 16 May 2022 19:39:35 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id\n 24GEt30Y004590;\n Mon, 16 May 2022 10:37:31 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3g3rsqrnxr-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Mon, 16 May 2022 10:37:31 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Mon, 16 May 2022 10:37:29 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Mon, 16 May 2022 10:37:29 -0700", "from localhost.localdomain (unknown [10.28.34.29])\n by maili.marvell.com (Postfix) with ESMTP id AAD253F70CD;\n Mon, 16 May 2022 10:37:26 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=m+AvGG7Vl1oTIXMOQAdtxgkai5PvzhqpLzPGp354N8c=;\n b=kwwXFFOqprWcWGBBkaqNTRdXfOCqb8CxBSHwkrgRSh5qPLE1I+RPs+olKrm4pzz/RWnn\n utng2dv4KotYMewBqFeFd8aBM57ci23Z8neshri+le1wdDK0f4R4yS3VxralhC3tDGsK\n XdxagVcvtLS63ZIemYRtoaOeU33Wlt56+YmfajL/wZD9QNaOa2PD+dhpajwDohaCCi4p\n Db4T4souFbLQAUe6G7EHj2FNl1i3sW2QWajdr3rS45jh3fETttrmLMPIZsMgXQ+ATta0\n dW4f/EkazIIjjcARyRb/Gd83OJUz4X8FusI8S1MAoJ8hlmdMdPCp5UU6x9YX89BbHRV7 vw==", "From": "Shijith Thotton <sthotton@marvell.com>", "To": "<dev@dpdk.org>, <jerinj@marvell.com>", "CC": "Pavan Nikhilesh <pbhagavatula@marvell.com>, <harry.van.haaren@intel.com>,\n <mattias.ronnblom@ericsson.com>, <mdr@ashroe.eu>, Shijith Thotton\n <sthotton@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "Subject": "[PATCH v4 4/5] common/cnxk: use lock when accessing mbox of SSO", "Date": "Mon, 16 May 2022 23:05:50 +0530", "Message-ID": "\n <a9f5244c8171226cfb37db4a8dbe2ea164937c7b.1652722314.git.sthotton@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<cover.1652722314.git.sthotton@marvell.com>", "References": "<cover.1652607951.git.sthotton@marvell.com>\n <cover.1652722314.git.sthotton@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "P0277cQDDcIHcMXy5wBhT4PEEkq8FmfA", "X-Proofpoint-GUID": "P0277cQDDcIHcMXy5wBhT4PEEkq8FmfA", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514\n definitions=2022-05-16_15,2022-05-16_02,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Pavan Nikhilesh <pbhagavatula@marvell.com>\n\nSince mbox is now accessed from multiple threads, use lock to\nsynchronize access.\n\nSigned-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>\nSigned-off-by: Shijith Thotton <sthotton@marvell.com>\n---\n drivers/common/cnxk/roc_sso.c | 174 +++++++++++++++++++++--------\n drivers/common/cnxk/roc_sso_priv.h | 1 +\n drivers/common/cnxk/roc_tim.c | 134 ++++++++++++++--------\n 3 files changed, 215 insertions(+), 94 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_sso.c b/drivers/common/cnxk/roc_sso.c\nindex f8a0a96533..358d37a9f2 100644\n--- a/drivers/common/cnxk/roc_sso.c\n+++ b/drivers/common/cnxk/roc_sso.c\n@@ -36,8 +36,8 @@ sso_lf_alloc(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf,\n \t}\n \n \trc = mbox_process_msg(dev->mbox, rsp);\n-\tif (rc < 0)\n-\t\treturn rc;\n+\tif (rc)\n+\t\treturn -EIO;\n \n \treturn 0;\n }\n@@ -69,8 +69,8 @@ sso_lf_free(struct dev *dev, enum sso_lf_type lf_type, uint16_t nb_lf)\n \t}\n \n \trc = mbox_process(dev->mbox);\n-\tif (rc < 0)\n-\t\treturn rc;\n+\tif (rc)\n+\t\treturn -EIO;\n \n \treturn 0;\n }\n@@ -98,7 +98,7 @@ sso_rsrc_attach(struct roc_sso *roc_sso, enum sso_lf_type lf_type,\n \t}\n \n \treq->modify = true;\n-\tif (mbox_process(dev->mbox) < 0)\n+\tif (mbox_process(dev->mbox))\n \t\treturn -EIO;\n \n \treturn 0;\n@@ -126,7 +126,7 @@ sso_rsrc_detach(struct roc_sso *roc_sso, enum sso_lf_type lf_type)\n \t}\n \n \treq->partial = true;\n-\tif (mbox_process(dev->mbox) < 0)\n+\tif (mbox_process(dev->mbox))\n \t\treturn -EIO;\n \n \treturn 0;\n@@ -141,9 +141,9 @@ sso_rsrc_get(struct roc_sso *roc_sso)\n \n \tmbox_alloc_msg_free_rsrc_cnt(dev->mbox);\n \trc = mbox_process_msg(dev->mbox, (void **)&rsrc_cnt);\n-\tif (rc < 0) {\n+\tif (rc) {\n \t\tplt_err(\"Failed to get free resource count\\n\");\n-\t\treturn rc;\n+\t\treturn -EIO;\n \t}\n \n \troc_sso->max_hwgrp = rsrc_cnt->sso;\n@@ -197,8 +197,8 @@ sso_msix_fill(struct roc_sso *roc_sso, uint16_t nb_hws, uint16_t nb_hwgrp)\n \n \tmbox_alloc_msg_msix_offset(dev->mbox);\n \trc = mbox_process_msg(dev->mbox, (void **)&rsp);\n-\tif (rc < 0)\n-\t\treturn rc;\n+\tif (rc)\n+\t\treturn -EIO;\n \n \tfor (i = 0; i < nb_hws; i++)\n \t\tsso->hws_msix_offset[i] = rsp->ssow_msixoff[i];\n@@ -285,53 +285,71 @@ int\n roc_sso_hws_stats_get(struct roc_sso *roc_sso, uint8_t hws,\n \t\t struct roc_sso_hws_stats *stats)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n \tstruct sso_hws_stats *req_rsp;\n+\tstruct dev *dev = &sso->dev;\n \tint rc;\n \n+\tplt_spinlock_lock(&sso->mbox_lock);\n \treq_rsp = (struct sso_hws_stats *)mbox_alloc_msg_sso_hws_get_stats(\n \t\tdev->mbox);\n \tif (req_rsp == NULL) {\n \t\trc = mbox_process(dev->mbox);\n-\t\tif (rc < 0)\n-\t\t\treturn rc;\n+\t\tif (rc) {\n+\t\t\trc = -EIO;\n+\t\t\tgoto fail;\n+\t\t}\n \t\treq_rsp = (struct sso_hws_stats *)\n \t\t\tmbox_alloc_msg_sso_hws_get_stats(dev->mbox);\n-\t\tif (req_rsp == NULL)\n-\t\t\treturn -ENOSPC;\n+\t\tif (req_rsp == NULL) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto fail;\n+\t\t}\n \t}\n \treq_rsp->hws = hws;\n \trc = mbox_process_msg(dev->mbox, (void **)&req_rsp);\n-\tif (rc)\n-\t\treturn rc;\n+\tif (rc) {\n+\t\trc = -EIO;\n+\t\tgoto fail;\n+\t}\n \n \tstats->arbitration = req_rsp->arbitration;\n-\treturn 0;\n+fail:\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n+\treturn rc;\n }\n \n int\n roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint8_t hwgrp,\n \t\t\tstruct roc_sso_hwgrp_stats *stats)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n \tstruct sso_grp_stats *req_rsp;\n+\tstruct dev *dev = &sso->dev;\n \tint rc;\n \n+\tplt_spinlock_lock(&sso->mbox_lock);\n \treq_rsp = (struct sso_grp_stats *)mbox_alloc_msg_sso_grp_get_stats(\n \t\tdev->mbox);\n \tif (req_rsp == NULL) {\n \t\trc = mbox_process(dev->mbox);\n-\t\tif (rc < 0)\n-\t\t\treturn rc;\n+\t\tif (rc) {\n+\t\t\trc = -EIO;\n+\t\t\tgoto fail;\n+\t\t}\n \t\treq_rsp = (struct sso_grp_stats *)\n \t\t\tmbox_alloc_msg_sso_grp_get_stats(dev->mbox);\n-\t\tif (req_rsp == NULL)\n-\t\t\treturn -ENOSPC;\n+\t\tif (req_rsp == NULL) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto fail;\n+\t\t}\n \t}\n \treq_rsp->grp = hwgrp;\n \trc = mbox_process_msg(dev->mbox, (void **)&req_rsp);\n-\tif (rc)\n-\t\treturn rc;\n+\tif (rc) {\n+\t\trc = -EIO;\n+\t\tgoto fail;\n+\t}\n \n \tstats->aw_status = req_rsp->aw_status;\n \tstats->dq_pc = req_rsp->dq_pc;\n@@ -341,7 +359,10 @@ roc_sso_hwgrp_stats_get(struct roc_sso *roc_sso, uint8_t hwgrp,\n \tstats->ts_pc = req_rsp->ts_pc;\n \tstats->wa_pc = req_rsp->wa_pc;\n \tstats->ws_pc = req_rsp->ws_pc;\n-\treturn 0;\n+\n+fail:\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n+\treturn rc;\n }\n \n int\n@@ -358,10 +379,12 @@ int\n roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso, struct roc_sso_hwgrp_qos *qos,\n \t\t\t uint8_t nb_qos, uint32_t nb_xaq)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n+\tstruct dev *dev = &sso->dev;\n \tstruct sso_grp_qos_cfg *req;\n \tint i, rc;\n \n+\tplt_spinlock_lock(&sso->mbox_lock);\n \tfor (i = 0; i < nb_qos; i++) {\n \t\tuint8_t xaq_prcnt = qos[i].xaq_prcnt;\n \t\tuint8_t iaq_prcnt = qos[i].iaq_prcnt;\n@@ -370,11 +393,16 @@ roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso, struct roc_sso_hwgrp_qos *qos,\n \t\treq = mbox_alloc_msg_sso_grp_qos_config(dev->mbox);\n \t\tif (req == NULL) {\n \t\t\trc = mbox_process(dev->mbox);\n-\t\t\tif (rc < 0)\n-\t\t\t\treturn rc;\n+\t\t\tif (rc) {\n+\t\t\t\trc = -EIO;\n+\t\t\t\tgoto fail;\n+\t\t\t}\n+\n \t\t\treq = mbox_alloc_msg_sso_grp_qos_config(dev->mbox);\n-\t\t\tif (req == NULL)\n-\t\t\t\treturn -ENOSPC;\n+\t\t\tif (req == NULL) {\n+\t\t\t\trc = -ENOSPC;\n+\t\t\t\tgoto fail;\n+\t\t\t}\n \t\t}\n \t\treq->grp = qos[i].hwgrp;\n \t\treq->xaq_limit = (nb_xaq * (xaq_prcnt ? xaq_prcnt : 100)) / 100;\n@@ -386,7 +414,12 @@ roc_sso_hwgrp_qos_config(struct roc_sso *roc_sso, struct roc_sso_hwgrp_qos *qos,\n \t\t\t 100;\n \t}\n \n-\treturn mbox_process(dev->mbox);\n+\trc = mbox_process(dev->mbox);\n+\tif (rc)\n+\t\trc = -EIO;\n+fail:\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n+\treturn rc;\n }\n \n int\n@@ -482,11 +515,16 @@ sso_hwgrp_init_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq,\n int\n roc_sso_hwgrp_init_xaq_aura(struct roc_sso *roc_sso, uint32_t nb_xae)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n+\tstruct dev *dev = &sso->dev;\n+\tint rc;\n \n-\treturn sso_hwgrp_init_xaq_aura(dev, &roc_sso->xaq, nb_xae,\n-\t\t\t\t roc_sso->xae_waes, roc_sso->xaq_buf_size,\n-\t\t\t\t roc_sso->nb_hwgrp);\n+\tplt_spinlock_lock(&sso->mbox_lock);\n+\trc = sso_hwgrp_init_xaq_aura(dev, &roc_sso->xaq, nb_xae,\n+\t\t\t\t roc_sso->xae_waes, roc_sso->xaq_buf_size,\n+\t\t\t\t roc_sso->nb_hwgrp);\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n+\treturn rc;\n }\n \n int\n@@ -515,9 +553,14 @@ sso_hwgrp_free_xaq_aura(struct dev *dev, struct roc_sso_xaq_data *xaq,\n int\n roc_sso_hwgrp_free_xaq_aura(struct roc_sso *roc_sso, uint16_t nb_hwgrp)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n+\tstruct dev *dev = &sso->dev;\n+\tint rc;\n \n-\treturn sso_hwgrp_free_xaq_aura(dev, &roc_sso->xaq, nb_hwgrp);\n+\tplt_spinlock_lock(&sso->mbox_lock);\n+\trc = sso_hwgrp_free_xaq_aura(dev, &roc_sso->xaq, nb_hwgrp);\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n+\treturn rc;\n }\n \n int\n@@ -533,16 +576,24 @@ sso_hwgrp_alloc_xaq(struct dev *dev, uint32_t npa_aura_id, uint16_t hwgrps)\n \treq->npa_aura_id = npa_aura_id;\n \treq->hwgrps = hwgrps;\n \n-\treturn mbox_process(dev->mbox);\n+\tif (mbox_process(dev->mbox))\n+\t\treturn -EIO;\n+\n+\treturn 0;\n }\n \n int\n roc_sso_hwgrp_alloc_xaq(struct roc_sso *roc_sso, uint32_t npa_aura_id,\n \t\t\tuint16_t hwgrps)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n+\tstruct dev *dev = &sso->dev;\n+\tint rc;\n \n-\treturn sso_hwgrp_alloc_xaq(dev, npa_aura_id, hwgrps);\n+\tplt_spinlock_lock(&sso->mbox_lock);\n+\trc = sso_hwgrp_alloc_xaq(dev, npa_aura_id, hwgrps);\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n+\treturn rc;\n }\n \n int\n@@ -555,40 +606,56 @@ sso_hwgrp_release_xaq(struct dev *dev, uint16_t hwgrps)\n \t\treturn -EINVAL;\n \treq->hwgrps = hwgrps;\n \n-\treturn mbox_process(dev->mbox);\n+\tif (mbox_process(dev->mbox))\n+\t\treturn -EIO;\n+\n+\treturn 0;\n }\n \n int\n roc_sso_hwgrp_release_xaq(struct roc_sso *roc_sso, uint16_t hwgrps)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n+\tstruct dev *dev = &sso->dev;\n+\tint rc;\n \n-\treturn sso_hwgrp_release_xaq(dev, hwgrps);\n+\tplt_spinlock_lock(&sso->mbox_lock);\n+\trc = sso_hwgrp_release_xaq(dev, hwgrps);\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n+\treturn rc;\n }\n \n int\n roc_sso_hwgrp_set_priority(struct roc_sso *roc_sso, uint16_t hwgrp,\n \t\t\t uint8_t weight, uint8_t affinity, uint8_t priority)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_sso);\n+\tstruct dev *dev = &sso->dev;\n \tstruct sso_grp_priority *req;\n \tint rc = -ENOSPC;\n \n+\tplt_spinlock_lock(&sso->mbox_lock);\n \treq = mbox_alloc_msg_sso_grp_set_priority(dev->mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto fail;\n \treq->grp = hwgrp;\n \treq->weight = weight;\n \treq->affinity = affinity;\n \treq->priority = priority;\n \n \trc = mbox_process(dev->mbox);\n-\tif (rc < 0)\n-\t\treturn rc;\n+\tif (rc) {\n+\t\trc = -EIO;\n+\t\tgoto fail;\n+\t}\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n \tplt_sso_dbg(\"HWGRP %d weight %d affinity %d priority %d\", hwgrp, weight,\n \t\t affinity, priority);\n \n \treturn 0;\n+fail:\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n+\treturn rc;\n }\n \n int\n@@ -603,10 +670,11 @@ roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp)\n \tif (roc_sso->max_hws < nb_hws)\n \t\treturn -ENOENT;\n \n+\tplt_spinlock_lock(&sso->mbox_lock);\n \trc = sso_rsrc_attach(roc_sso, SSO_LF_TYPE_HWS, nb_hws);\n \tif (rc < 0) {\n \t\tplt_err(\"Unable to attach SSO HWS LFs\");\n-\t\treturn rc;\n+\t\tgoto fail;\n \t}\n \n \trc = sso_rsrc_attach(roc_sso, SSO_LF_TYPE_HWGRP, nb_hwgrp);\n@@ -645,6 +713,7 @@ roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp)\n \t\tgoto sso_msix_fail;\n \t}\n \n+\tplt_spinlock_unlock(&sso->mbox_lock);\n \troc_sso->nb_hwgrp = nb_hwgrp;\n \troc_sso->nb_hws = nb_hws;\n \n@@ -657,6 +726,8 @@ roc_sso_rsrc_init(struct roc_sso *roc_sso, uint8_t nb_hws, uint16_t nb_hwgrp)\n \tsso_rsrc_detach(roc_sso, SSO_LF_TYPE_HWGRP);\n hwgrp_atch_fail:\n \tsso_rsrc_detach(roc_sso, SSO_LF_TYPE_HWS);\n+fail:\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n \treturn rc;\n }\n \n@@ -678,6 +749,7 @@ roc_sso_rsrc_fini(struct roc_sso *roc_sso)\n \n \troc_sso->nb_hwgrp = 0;\n \troc_sso->nb_hws = 0;\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n }\n \n int\n@@ -696,6 +768,7 @@ roc_sso_dev_init(struct roc_sso *roc_sso)\n \tsso = roc_sso_to_sso_priv(roc_sso);\n \tmemset(sso, 0, sizeof(*sso));\n \tpci_dev = roc_sso->pci_dev;\n+\tplt_spinlock_init(&sso->mbox_lock);\n \n \trc = dev_init(&sso->dev, pci_dev);\n \tif (rc < 0) {\n@@ -703,6 +776,7 @@ roc_sso_dev_init(struct roc_sso *roc_sso)\n \t\tgoto fail;\n \t}\n \n+\tplt_spinlock_lock(&sso->mbox_lock);\n \trc = sso_rsrc_get(roc_sso);\n \tif (rc < 0) {\n \t\tplt_err(\"Failed to get SSO resources\");\n@@ -739,6 +813,7 @@ roc_sso_dev_init(struct roc_sso *roc_sso)\n \tsso->pci_dev = pci_dev;\n \tsso->dev.drv_inited = true;\n \troc_sso->lmt_base = sso->dev.lmt_base;\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n \n \treturn 0;\n link_mem_free:\n@@ -746,6 +821,7 @@ roc_sso_dev_init(struct roc_sso *roc_sso)\n rsrc_fail:\n \trc |= dev_fini(&sso->dev, pci_dev);\n fail:\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n \treturn rc;\n }\n \ndiff --git a/drivers/common/cnxk/roc_sso_priv.h b/drivers/common/cnxk/roc_sso_priv.h\nindex 09729d4f62..674e4e0a39 100644\n--- a/drivers/common/cnxk/roc_sso_priv.h\n+++ b/drivers/common/cnxk/roc_sso_priv.h\n@@ -22,6 +22,7 @@ struct sso {\n \t/* SSO link mapping. */\n \tstruct plt_bitmap **link_map;\n \tvoid *link_map_mem;\n+\tplt_spinlock_t mbox_lock;\n } __plt_cache_aligned;\n \n enum sso_err_status {\ndiff --git a/drivers/common/cnxk/roc_tim.c b/drivers/common/cnxk/roc_tim.c\nindex cefd9bc89d..0f9209937b 100644\n--- a/drivers/common/cnxk/roc_tim.c\n+++ b/drivers/common/cnxk/roc_tim.c\n@@ -8,15 +8,16 @@\n static int\n tim_fill_msix(struct roc_tim *roc_tim, uint16_t nb_ring)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n \tstruct tim *tim = roc_tim_to_tim_priv(roc_tim);\n+\tstruct dev *dev = &sso->dev;\n \tstruct msix_offset_rsp *rsp;\n \tint i, rc;\n \n \tmbox_alloc_msg_msix_offset(dev->mbox);\n \trc = mbox_process_msg(dev->mbox, (void **)&rsp);\n-\tif (rc < 0)\n-\t\treturn rc;\n+\tif (rc)\n+\t\treturn -EIO;\n \n \tfor (i = 0; i < nb_ring; i++)\n \t\ttim->tim_msix_offsets[i] = rsp->timlf_msixoff[i];\n@@ -88,20 +89,23 @@ int\n roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *start_tsc,\n \t\t uint32_t *cur_bkt)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n+\tstruct dev *dev = &sso->dev;\n \tstruct tim_enable_rsp *rsp;\n \tstruct tim_ring_req *req;\n \tint rc = -ENOSPC;\n \n+\tplt_spinlock_lock(&sso->mbox_lock);\n \treq = mbox_alloc_msg_tim_enable_ring(dev->mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto fail;\n \treq->ring = ring_id;\n \n \trc = mbox_process_msg(dev->mbox, (void **)&rsp);\n-\tif (rc < 0) {\n+\tif (rc) {\n \t\ttim_err_desc(rc);\n-\t\treturn rc;\n+\t\trc = -EIO;\n+\t\tgoto fail;\n \t}\n \n \tif (cur_bkt)\n@@ -109,28 +113,34 @@ roc_tim_lf_enable(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *start_tsc,\n \tif (start_tsc)\n \t\t*start_tsc = rsp->timestarted;\n \n-\treturn 0;\n+fail:\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n+\treturn rc;\n }\n \n int\n roc_tim_lf_disable(struct roc_tim *roc_tim, uint8_t ring_id)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n+\tstruct dev *dev = &sso->dev;\n \tstruct tim_ring_req *req;\n \tint rc = -ENOSPC;\n \n+\tplt_spinlock_lock(&sso->mbox_lock);\n \treq = mbox_alloc_msg_tim_disable_ring(dev->mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto fail;\n \treq->ring = ring_id;\n \n \trc = mbox_process(dev->mbox);\n-\tif (rc < 0) {\n+\tif (rc) {\n \t\ttim_err_desc(rc);\n-\t\treturn rc;\n+\t\trc = -EIO;\n \t}\n \n-\treturn 0;\n+fail:\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n+\treturn rc;\n }\n \n uintptr_t\n@@ -147,13 +157,15 @@ roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id,\n \t\t uint8_t ena_dfb, uint32_t bucket_sz, uint32_t chunk_sz,\n \t\t uint32_t interval, uint64_t intervalns, uint64_t clockfreq)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n+\tstruct dev *dev = &sso->dev;\n \tstruct tim_config_req *req;\n \tint rc = -ENOSPC;\n \n+\tplt_spinlock_lock(&sso->mbox_lock);\n \treq = mbox_alloc_msg_tim_config_ring(dev->mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto fail;\n \treq->ring = ring_id;\n \treq->bigendian = false;\n \treq->bucketsize = bucket_sz;\n@@ -167,12 +179,14 @@ roc_tim_lf_config(struct roc_tim *roc_tim, uint8_t ring_id,\n \treq->gpioedge = TIM_GPIO_LTOH_TRANS;\n \n \trc = mbox_process(dev->mbox);\n-\tif (rc < 0) {\n+\tif (rc) {\n \t\ttim_err_desc(rc);\n-\t\treturn rc;\n+\t\trc = -EIO;\n \t}\n \n-\treturn 0;\n+fail:\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n+\treturn rc;\n }\n \n int\n@@ -180,27 +194,32 @@ roc_tim_lf_interval(struct roc_tim *roc_tim, enum roc_tim_clk_src clk_src,\n \t\t uint64_t clockfreq, uint64_t *intervalns,\n \t\t uint64_t *interval)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n+\tstruct dev *dev = &sso->dev;\n \tstruct tim_intvl_req *req;\n \tstruct tim_intvl_rsp *rsp;\n \tint rc = -ENOSPC;\n \n+\tplt_spinlock_lock(&sso->mbox_lock);\n \treq = mbox_alloc_msg_tim_get_min_intvl(dev->mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto fail;\n \n \treq->clockfreq = clockfreq;\n \treq->clocksource = clk_src;\n \trc = mbox_process_msg(dev->mbox, (void **)&rsp);\n-\tif (rc < 0) {\n+\tif (rc) {\n \t\ttim_err_desc(rc);\n-\t\treturn rc;\n+\t\trc = -EIO;\n+\t\tgoto fail;\n \t}\n \n \t*intervalns = rsp->intvl_ns;\n \t*interval = rsp->intvl_cyc;\n \n-\treturn 0;\n+fail:\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n+\treturn rc;\n }\n \n int\n@@ -214,17 +233,19 @@ roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *clk)\n \tstruct dev *dev = &sso->dev;\n \tint rc = -ENOSPC;\n \n+\tplt_spinlock_lock(&sso->mbox_lock);\n \treq = mbox_alloc_msg_tim_lf_alloc(dev->mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto fail;\n \treq->npa_pf_func = idev_npa_pffunc_get();\n \treq->sso_pf_func = idev_sso_pffunc_get();\n \treq->ring = ring_id;\n \n \trc = mbox_process_msg(dev->mbox, (void **)&rsp);\n-\tif (rc < 0) {\n+\tif (rc) {\n \t\ttim_err_desc(rc);\n-\t\treturn rc;\n+\t\trc = -EIO;\n+\t\tgoto fail;\n \t}\n \n \tif (clk)\n@@ -235,12 +256,18 @@ roc_tim_lf_alloc(struct roc_tim *roc_tim, uint8_t ring_id, uint64_t *clk)\n \tif (rc < 0) {\n \t\tplt_tim_dbg(\"Failed to register Ring[%d] IRQ\", ring_id);\n \t\tfree_req = mbox_alloc_msg_tim_lf_free(dev->mbox);\n-\t\tif (free_req == NULL)\n-\t\t\treturn -ENOSPC;\n+\t\tif (free_req == NULL) {\n+\t\t\trc = -ENOSPC;\n+\t\t\tgoto fail;\n+\t\t}\n \t\tfree_req->ring = ring_id;\n-\t\tmbox_process(dev->mbox);\n+\t\trc = mbox_process(dev->mbox);\n+\t\tif (rc)\n+\t\t\trc = -EIO;\n \t}\n \n+fail:\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n \treturn rc;\n }\n \n@@ -256,17 +283,20 @@ roc_tim_lf_free(struct roc_tim *roc_tim, uint8_t ring_id)\n \ttim_unregister_irq_priv(roc_tim, sso->pci_dev->intr_handle, ring_id,\n \t\t\t\ttim->tim_msix_offsets[ring_id]);\n \n+\tplt_spinlock_lock(&sso->mbox_lock);\n \treq = mbox_alloc_msg_tim_lf_free(dev->mbox);\n \tif (req == NULL)\n-\t\treturn rc;\n+\t\tgoto fail;\n \treq->ring = ring_id;\n \n \trc = mbox_process(dev->mbox);\n \tif (rc < 0) {\n \t\ttim_err_desc(rc);\n-\t\treturn rc;\n+\t\trc = -EIO;\n \t}\n \n+fail:\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n \treturn 0;\n }\n \n@@ -276,40 +306,48 @@ roc_tim_init(struct roc_tim *roc_tim)\n \tstruct rsrc_attach_req *attach_req;\n \tstruct rsrc_detach_req *detach_req;\n \tstruct free_rsrcs_rsp *free_rsrc;\n-\tstruct dev *dev;\n+\tstruct sso *sso;\n \tuint16_t nb_lfs;\n+\tstruct dev *dev;\n \tint rc;\n \n \tif (roc_tim == NULL || roc_tim->roc_sso == NULL)\n \t\treturn TIM_ERR_PARAM;\n \n+\tsso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n+\tdev = &sso->dev;\n \tPLT_STATIC_ASSERT(sizeof(struct tim) <= TIM_MEM_SZ);\n-\tdev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n \tnb_lfs = roc_tim->nb_lfs;\n+\tplt_spinlock_lock(&sso->mbox_lock);\n \tmbox_alloc_msg_free_rsrc_cnt(dev->mbox);\n \trc = mbox_process_msg(dev->mbox, (void *)&free_rsrc);\n-\tif (rc < 0) {\n+\tif (rc) {\n \t\tplt_err(\"Unable to get free rsrc count.\");\n-\t\treturn 0;\n+\t\tnb_lfs = 0;\n+\t\tgoto fail;\n \t}\n \n \tif (nb_lfs && (free_rsrc->tim < nb_lfs)) {\n \t\tplt_tim_dbg(\"Requested LFs : %d Available LFs : %d\", nb_lfs,\n \t\t\t free_rsrc->tim);\n-\t\treturn 0;\n+\t\tnb_lfs = 0;\n+\t\tgoto fail;\n \t}\n \n \tattach_req = mbox_alloc_msg_attach_resources(dev->mbox);\n-\tif (attach_req == NULL)\n-\t\treturn -ENOSPC;\n+\tif (attach_req == NULL) {\n+\t\tnb_lfs = 0;\n+\t\tgoto fail;\n+\t}\n \tattach_req->modify = true;\n \tattach_req->timlfs = nb_lfs ? nb_lfs : free_rsrc->tim;\n \tnb_lfs = attach_req->timlfs;\n \n \trc = mbox_process(dev->mbox);\n-\tif (rc < 0) {\n+\tif (rc) {\n \t\tplt_err(\"Unable to attach TIM LFs.\");\n-\t\treturn 0;\n+\t\tnb_lfs = 0;\n+\t\tgoto fail;\n \t}\n \n \trc = tim_fill_msix(roc_tim, nb_lfs);\n@@ -317,28 +355,34 @@ roc_tim_init(struct roc_tim *roc_tim)\n \t\tplt_err(\"Unable to get TIM MSIX vectors\");\n \n \t\tdetach_req = mbox_alloc_msg_detach_resources(dev->mbox);\n-\t\tif (detach_req == NULL)\n-\t\t\treturn -ENOSPC;\n+\t\tif (detach_req == NULL) {\n+\t\t\tnb_lfs = 0;\n+\t\t\tgoto fail;\n+\t\t}\n \t\tdetach_req->partial = true;\n \t\tdetach_req->timlfs = true;\n \t\tmbox_process(dev->mbox);\n-\n-\t\treturn 0;\n+\t\tnb_lfs = 0;\n \t}\n \n+fail:\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n \treturn nb_lfs;\n }\n \n void\n roc_tim_fini(struct roc_tim *roc_tim)\n {\n-\tstruct dev *dev = &roc_sso_to_sso_priv(roc_tim->roc_sso)->dev;\n+\tstruct sso *sso = roc_sso_to_sso_priv(roc_tim->roc_sso);\n \tstruct rsrc_detach_req *detach_req;\n+\tstruct dev *dev = &sso->dev;\n \n+\tplt_spinlock_lock(&sso->mbox_lock);\n \tdetach_req = mbox_alloc_msg_detach_resources(dev->mbox);\n \tPLT_ASSERT(detach_req);\n \tdetach_req->partial = true;\n \tdetach_req->timlfs = true;\n \n \tmbox_process(dev->mbox);\n+\tplt_spinlock_unlock(&sso->mbox_lock);\n }\n", "prefixes": [ "v4", "4/5" ] }