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{
    "id": 11108,
    "url": "http://patches.dpdk.org/api/patches/11108/?format=api",
    "web_url": "http://patches.dpdk.org/project/dpdk/patch/1457278919-30800-13-git-send-email-helin.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<1457278919-30800-13-git-send-email-helin.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/1457278919-30800-13-git-send-email-helin.zhang@intel.com",
    "date": "2016-03-06T15:41:42",
    "name": "[dpdk-dev,v4,12/29] i40e/base: unify the capability function",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "2f991adeb033a3ca32da117f93b4091b6aa7bc08",
    "submitter": {
        "id": 14,
        "url": "http://patches.dpdk.org/api/people/14/?format=api",
        "name": "Zhang, Helin",
        "email": "helin.zhang@intel.com"
    },
    "delegate": {
        "id": 10,
        "url": "http://patches.dpdk.org/api/users/10/?format=api",
        "username": "bruce",
        "first_name": "Bruce",
        "last_name": "Richardson",
        "email": "bruce.richardson@intel.com"
    },
    "mbox": "http://patches.dpdk.org/project/dpdk/patch/1457278919-30800-13-git-send-email-helin.zhang@intel.com/mbox/",
    "series": [],
    "comments": "http://patches.dpdk.org/api/patches/11108/comments/",
    "check": "pending",
    "checks": "http://patches.dpdk.org/api/patches/11108/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id 32FA847D0;\n\tSun,  6 Mar 2016 16:42:40 +0100 (CET)",
            "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id D26A32C49\n\tfor <dev@dpdk.org>; Sun,  6 Mar 2016 16:42:38 +0100 (CET)",
            "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby fmsmga101.fm.intel.com with ESMTP; 06 Mar 2016 07:42:32 -0800",
            "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga002.fm.intel.com with ESMTP; 06 Mar 2016 07:42:32 -0800",
            "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id u26FgUGW000420;\n\tSun, 6 Mar 2016 23:42:30 +0800",
            "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid u26FgROP030919; Sun, 6 Mar 2016 23:42:29 +0800",
            "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id u26FgRxl030915; \n\tSun, 6 Mar 2016 23:42:27 +0800"
        ],
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.22,546,1449561600\"; d=\"scan'208\";a=\"930787948\"",
        "From": "Helin Zhang <helin.zhang@intel.com>",
        "To": "dev@dpdk.org",
        "Date": "Sun,  6 Mar 2016 23:41:42 +0800",
        "Message-Id": "<1457278919-30800-13-git-send-email-helin.zhang@intel.com>",
        "X-Mailer": "git-send-email 1.7.4.1",
        "In-Reply-To": "<1457278919-30800-1-git-send-email-helin.zhang@intel.com>",
        "References": "<1455806076-18497-1-git-send-email-helin.zhang@intel.com>\n\t<1457278919-30800-1-git-send-email-helin.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH v4 12/29] i40e/base: unify the capability function",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "patches and discussions about DPDK <dev.dpdk.org>",
        "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://dpdk.org/ml/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "The device capabilities were defined in two places, and neither had\nall the definitions. It really belongs with the AQ API definition,\nso this patch removes the other set of definitions and fills out the\nmissing item.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\nAcked-by: Jingjing Wu <jingjing.wu@intel.com>\n---\n drivers/net/i40e/base/i40e_adminq_cmd.h |   1 +\n drivers/net/i40e/base/i40e_common.c     | 191 ++++++++++++++++++++++----------\n 2 files changed, 131 insertions(+), 61 deletions(-)\n\nv4:\n - Reworded the commit logs.",
    "diff": "diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h\nindex ff6449c..aa11bcd 100644\n--- a/drivers/net/i40e/base/i40e_adminq_cmd.h\n+++ b/drivers/net/i40e/base/i40e_adminq_cmd.h\n@@ -444,6 +444,7 @@ struct i40e_aqc_list_capabilities_element_resp {\n #define I40E_AQ_CAP_ID_LED\t\t0x0061\n #define I40E_AQ_CAP_ID_SDP\t\t0x0062\n #define I40E_AQ_CAP_ID_MDIO\t\t0x0063\n+#define I40E_AQ_CAP_ID_WSR_PROT\t\t0x0064\n #define I40E_AQ_CAP_ID_FLEX10\t\t0x00F1\n #define I40E_AQ_CAP_ID_CEM\t\t0x00F2\n \ndiff --git a/drivers/net/i40e/base/i40e_common.c b/drivers/net/i40e/base/i40e_common.c\nindex cfe071b..8d2f2c7 100644\n--- a/drivers/net/i40e/base/i40e_common.c\n+++ b/drivers/net/i40e/base/i40e_common.c\n@@ -3342,38 +3342,6 @@ i40e_aq_erase_nvm_exit:\n \treturn status;\n }\n \n-#define I40E_DEV_FUNC_CAP_SWITCH_MODE\t0x01\n-#define I40E_DEV_FUNC_CAP_MGMT_MODE\t0x02\n-#define I40E_DEV_FUNC_CAP_NPAR\t\t0x03\n-#define I40E_DEV_FUNC_CAP_OS2BMC\t0x04\n-#define I40E_DEV_FUNC_CAP_VALID_FUNC\t0x05\n-#ifdef X722_SUPPORT\n-#define I40E_DEV_FUNC_CAP_WOL_PROXY\t0x08\n-#endif\n-#define I40E_DEV_FUNC_CAP_SRIOV_1_1\t0x12\n-#define I40E_DEV_FUNC_CAP_VF\t\t0x13\n-#define I40E_DEV_FUNC_CAP_VMDQ\t\t0x14\n-#define I40E_DEV_FUNC_CAP_802_1_QBG\t0x15\n-#define I40E_DEV_FUNC_CAP_802_1_QBH\t0x16\n-#define I40E_DEV_FUNC_CAP_VSI\t\t0x17\n-#define I40E_DEV_FUNC_CAP_DCB\t\t0x18\n-#define I40E_DEV_FUNC_CAP_FCOE\t\t0x21\n-#define I40E_DEV_FUNC_CAP_ISCSI\t\t0x22\n-#define I40E_DEV_FUNC_CAP_RSS\t\t0x40\n-#define I40E_DEV_FUNC_CAP_RX_QUEUES\t0x41\n-#define I40E_DEV_FUNC_CAP_TX_QUEUES\t0x42\n-#define I40E_DEV_FUNC_CAP_MSIX\t\t0x43\n-#define I40E_DEV_FUNC_CAP_MSIX_VF\t0x44\n-#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR\t0x45\n-#define I40E_DEV_FUNC_CAP_IEEE_1588\t0x46\n-#define I40E_DEV_FUNC_CAP_FLEX10\t0xF1\n-#define I40E_DEV_FUNC_CAP_CEM\t\t0xF2\n-#define I40E_DEV_FUNC_CAP_IWARP\t\t0x51\n-#define I40E_DEV_FUNC_CAP_LED\t\t0x61\n-#define I40E_DEV_FUNC_CAP_SDP\t\t0x62\n-#define I40E_DEV_FUNC_CAP_MDIO\t\t0x63\n-#define I40E_DEV_FUNC_CAP_WR_CSR_PROT\t0x64\n-\n /**\n  * i40e_parse_discover_capabilities\n  * @hw: pointer to the hw struct\n@@ -3412,79 +3380,146 @@ STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,\n \t\tmajor_rev = cap->major_rev;\n \n \t\tswitch (id) {\n-\t\tcase I40E_DEV_FUNC_CAP_SWITCH_MODE:\n+\t\tcase I40E_AQ_CAP_ID_SWITCH_MODE:\n \t\t\tp->switch_mode = number;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: Switch mode = %d\\n\",\n+\t\t\t\t   p->switch_mode);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_MGMT_MODE:\n+\t\tcase I40E_AQ_CAP_ID_MNG_MODE:\n \t\t\tp->management_mode = number;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: Management Mode = %d\\n\",\n+\t\t\t\t   p->management_mode);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_NPAR:\n+\t\tcase I40E_AQ_CAP_ID_NPAR_ACTIVE:\n \t\t\tp->npar_enable = number;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: NPAR enable = %d\\n\",\n+\t\t\t\t   p->npar_enable);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_OS2BMC:\n+\t\tcase I40E_AQ_CAP_ID_OS2BMC_CAP:\n \t\t\tp->os2bmc = number;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: OS2BMC = %d\\n\", p->os2bmc);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_VALID_FUNC:\n+\t\tcase I40E_AQ_CAP_ID_FUNCTIONS_VALID:\n \t\t\tp->valid_functions = number;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: Valid Functions = %d\\n\",\n+\t\t\t\t   p->valid_functions);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_SRIOV_1_1:\n+\t\tcase I40E_AQ_CAP_ID_SRIOV:\n \t\t\tif (number == 1)\n \t\t\t\tp->sr_iov_1_1 = true;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: SR-IOV = %d\\n\",\n+\t\t\t\t   p->sr_iov_1_1);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_VF:\n+\t\tcase I40E_AQ_CAP_ID_VF:\n \t\t\tp->num_vfs = number;\n \t\t\tp->vf_base_id = logical_id;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: VF count = %d\\n\",\n+\t\t\t\t   p->num_vfs);\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: VF base_id = %d\\n\",\n+\t\t\t\t   p->vf_base_id);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_VMDQ:\n+\t\tcase I40E_AQ_CAP_ID_VMDQ:\n \t\t\tif (number == 1)\n \t\t\t\tp->vmdq = true;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: VMDQ = %d\\n\", p->vmdq);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_802_1_QBG:\n+\t\tcase I40E_AQ_CAP_ID_8021QBG:\n \t\t\tif (number == 1)\n \t\t\t\tp->evb_802_1_qbg = true;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: 802.1Qbg = %d\\n\", number);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_802_1_QBH:\n+\t\tcase I40E_AQ_CAP_ID_8021QBR:\n \t\t\tif (number == 1)\n \t\t\t\tp->evb_802_1_qbh = true;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: 802.1Qbh = %d\\n\", number);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_VSI:\n+\t\tcase I40E_AQ_CAP_ID_VSI:\n \t\t\tp->num_vsis = number;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: VSI count = %d\\n\",\n+\t\t\t\t   p->num_vsis);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_DCB:\n+\t\tcase I40E_AQ_CAP_ID_DCB:\n \t\t\tif (number == 1) {\n \t\t\t\tp->dcb = true;\n \t\t\t\tp->enabled_tcmap = logical_id;\n \t\t\t\tp->maxtc = phys_id;\n \t\t\t}\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: DCB = %d\\n\", p->dcb);\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: TC Mapping = %d\\n\",\n+\t\t\t\t   logical_id);\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: TC Max = %d\\n\", p->maxtc);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_FCOE:\n+\t\tcase I40E_AQ_CAP_ID_FCOE:\n \t\t\tif (number == 1)\n \t\t\t\tp->fcoe = true;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: FCOE = %d\\n\", p->fcoe);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_ISCSI:\n+\t\tcase I40E_AQ_CAP_ID_ISCSI:\n \t\t\tif (number == 1)\n \t\t\t\tp->iscsi = true;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: iSCSI = %d\\n\", p->iscsi);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_RSS:\n+\t\tcase I40E_AQ_CAP_ID_RSS:\n \t\t\tp->rss = true;\n \t\t\tp->rss_table_size = number;\n \t\t\tp->rss_table_entry_width = logical_id;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: RSS = %d\\n\", p->rss);\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: RSS table size = %d\\n\",\n+\t\t\t\t   p->rss_table_size);\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: RSS table width = %d\\n\",\n+\t\t\t\t   p->rss_table_entry_width);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_RX_QUEUES:\n+\t\tcase I40E_AQ_CAP_ID_RXQ:\n \t\t\tp->num_rx_qp = number;\n \t\t\tp->base_queue = phys_id;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: Rx QP = %d\\n\", number);\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: base_queue = %d\\n\",\n+\t\t\t\t   p->base_queue);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_TX_QUEUES:\n+\t\tcase I40E_AQ_CAP_ID_TXQ:\n \t\t\tp->num_tx_qp = number;\n \t\t\tp->base_queue = phys_id;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: Tx QP = %d\\n\", number);\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: base_queue = %d\\n\",\n+\t\t\t\t   p->base_queue);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_MSIX:\n+\t\tcase I40E_AQ_CAP_ID_MSIX:\n \t\t\tp->num_msix_vectors = number;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: MSIX vector count = %d\\n\",\n+\t\t\t\t   p->num_msix_vectors_vf);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_MSIX_VF:\n+\t\tcase I40E_AQ_CAP_ID_VF_MSIX:\n \t\t\tp->num_msix_vectors_vf = number;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: MSIX VF vector count = %d\\n\",\n+\t\t\t\t   p->num_msix_vectors_vf);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_FLEX10:\n+\t\tcase I40E_AQ_CAP_ID_FLEX10:\n \t\t\tif (major_rev == 1) {\n \t\t\t\tif (number == 1) {\n \t\t\t\t\tp->flex10_enable = true;\n@@ -3499,44 +3534,75 @@ STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,\n \t\t\t}\n \t\t\tp->flex10_mode = logical_id;\n \t\t\tp->flex10_status = phys_id;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: Flex10 mode = %d\\n\",\n+\t\t\t\t   p->flex10_mode);\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: Flex10 status = %d\\n\",\n+\t\t\t\t   p->flex10_status);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_CEM:\n+\t\tcase I40E_AQ_CAP_ID_CEM:\n \t\t\tif (number == 1)\n \t\t\t\tp->mgmt_cem = true;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: CEM = %d\\n\", p->mgmt_cem);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_IWARP:\n+\t\tcase I40E_AQ_CAP_ID_IWARP:\n \t\t\tif (number == 1)\n \t\t\t\tp->iwarp = true;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: iWARP = %d\\n\", p->iwarp);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_LED:\n+\t\tcase I40E_AQ_CAP_ID_LED:\n \t\t\tif (phys_id < I40E_HW_CAP_MAX_GPIO)\n \t\t\t\tp->led[phys_id] = true;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: LED - PIN %d\\n\", phys_id);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_SDP:\n+\t\tcase I40E_AQ_CAP_ID_SDP:\n \t\t\tif (phys_id < I40E_HW_CAP_MAX_GPIO)\n \t\t\t\tp->sdp[phys_id] = true;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: SDP - PIN %d\\n\", phys_id);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_MDIO:\n+\t\tcase I40E_AQ_CAP_ID_MDIO:\n \t\t\tif (number == 1) {\n \t\t\t\tp->mdio_port_num = phys_id;\n \t\t\t\tp->mdio_port_mode = logical_id;\n \t\t\t}\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: MDIO port number = %d\\n\",\n+\t\t\t\t   p->mdio_port_num);\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: MDIO port mode = %d\\n\",\n+\t\t\t\t   p->mdio_port_mode);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_IEEE_1588:\n+\t\tcase I40E_AQ_CAP_ID_1588:\n \t\t\tif (number == 1)\n \t\t\t\tp->ieee_1588 = true;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: IEEE 1588 = %d\\n\",\n+\t\t\t\t   p->ieee_1588);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:\n+\t\tcase I40E_AQ_CAP_ID_FLOW_DIRECTOR:\n \t\t\tp->fd = true;\n \t\t\tp->fd_filters_guaranteed = number;\n \t\t\tp->fd_filters_best_effort = logical_id;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: Flow Director = 1\\n\");\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: Guaranteed FD filters = %d\\n\",\n+\t\t\t\t   p->fd_filters_guaranteed);\n \t\t\tbreak;\n-\t\tcase I40E_DEV_FUNC_CAP_WR_CSR_PROT:\n+\t\tcase I40E_AQ_CAP_ID_WSR_PROT:\n \t\t\tp->wr_csr_prot = (u64)number;\n \t\t\tp->wr_csr_prot |= (u64)logical_id << 32;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: wr_csr_prot = 0x%llX\\n\\n\",\n+\t\t\t\t   (p->wr_csr_prot & 0xffff));\n \t\t\tbreak;\n #ifdef X722_SUPPORT\n-\t\tcase I40E_DEV_FUNC_CAP_WOL_PROXY:\n+\t\tcase I40E_AQ_CAP_ID_WOL_AND_PROXY:\n \t\t\thw->num_wol_proxy_filters = (u16)number;\n \t\t\thw->wol_proxy_vsi_seid = (u16)logical_id;\n \t\t\tp->apm_wol_support = phys_id & I40E_WOL_SUPPORT_MASK;\n@@ -3546,6 +3612,9 @@ STATIC void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,\n \t\t\t\tp->acpi_prog_method = I40E_ACPI_PROGRAMMING_METHOD_HW_FVL;\n \t\t\tp->proxy_support = (phys_id & I40E_PROXY_SUPPORT_MASK) ? 1 : 0;\n \t\t\tp->proxy_support = p->proxy_support;\n+\t\t\ti40e_debug(hw, I40E_DEBUG_INIT,\n+\t\t\t\t   \"HW Capability: WOL proxy filters = %d\\n\",\n+\t\t\t\t   hw->num_wol_proxy_filters);\n \t\t\tbreak;\n #endif\n \t\tdefault:\n",
    "prefixes": [
        "dpdk-dev",
        "v4",
        "12/29"
    ]
}