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GET /api/patches/111045/?format=api
{ "id": 111045, "url": "http://patches.dpdk.org/api/patches/111045/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220512074443.183631-1-ke1x.zhang@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220512074443.183631-1-ke1x.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220512074443.183631-1-ke1x.zhang@intel.com", "date": "2022-05-12T07:44:43", "name": "[v5] fix mbuf release function point corrupt in multi-process", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9f3532e742ecc9a65fc2a77c63dc1275d489e358", "submitter": { "id": 2503, "url": "http://patches.dpdk.org/api/people/2503/?format=api", "name": "Zhang, Ke1X", "email": "ke1x.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220512074443.183631-1-ke1x.zhang@intel.com/mbox/", "series": [ { "id": 22905, "url": "http://patches.dpdk.org/api/series/22905/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22905", "date": "2022-05-12T07:44:43", "name": "[v5] fix mbuf release function point corrupt in multi-process", "version": 5, "mbox": "http://patches.dpdk.org/series/22905/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/111045/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/111045/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1B334A0032;\n\tThu, 12 May 2022 09:50:59 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id F10E040E64;\n\tThu, 12 May 2022 09:50:58 +0200 (CEST)", "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by mails.dpdk.org (Postfix) with ESMTP id DE3124014F\n for <dev@dpdk.org>; Thu, 12 May 2022 09:50:56 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 May 2022 00:50:55 -0700", "from unknown (HELO localhost.localdomain) ([10.239.251.104])\n by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 May 2022 00:50:53 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1652341857; x=1683877857;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=Ep4Gx92aavJzo5gPZqs9S6Nn+d601mjZ34TmNVIjXNk=;\n b=h2eatE4DPwX48YArfV7jtBBJZJbp6wpnIuYKZF1huALbY8bzxqjO9I8x\n RB+Jg83etmbNiqLZq4kmPqnfYeuaB/qCfCB4F0J732CGK0N1bzm3oJzI2\n To/nLfRT5i0TlVs+cQdjauD+khXY8PaYu2k+NSAvn264GqAf19Bl3ZMla\n xL98sd+hJyptXweo5RZDsOwUOXgir3jBH8N8KeuHBo9l/ZNNe7MGxaoFR\n akjKrGUy6KjXG7IlOsb/oN3yaC7NmsS3pl+SoW6+wxyvbD3++X4PHZ661\n wG431vg5EM1pIzwhv5SDd2Fj5M5yEMBe8M0yWKlRuLcn0VNlUIxWPc3AZ A==;", "X-IronPort-AV": [ "E=McAfee;i=\"6400,9594,10344\"; a=\"269865822\"", "E=Sophos;i=\"5.91,219,1647327600\"; d=\"scan'208\";a=\"269865822\"", "E=Sophos;i=\"5.91,219,1647327600\"; d=\"scan'208\";a=\"594548536\"" ], "From": "Ke Zhang <ke1x.zhang@intel.com>", "To": "xiaoyun.li@intel.com, jingjing.wu@intel.com, beilei.xing@intel.com,\n dev@dpdk.org", "Cc": "Ke Zhang <ke1x.zhang@intel.com>", "Subject": "[PATCH v5] fix mbuf release function point corrupt in multi-process", "Date": "Thu, 12 May 2022 07:44:43 +0000", "Message-Id": "<20220512074443.183631-1-ke1x.zhang@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20220510025428.110325-1-ke1x.zhang@intel.com>", "References": "<20220510025428.110325-1-ke1x.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "In the multiple process environment, the subprocess operates on the\nshared memory and changes the function pointer of the main process,\nresulting in the failure to find the address of the function when main\nprocess releasing, resulting in crash.\n\nSigned-off-by: Ke Zhang <ke1x.zhang@intel.com>\n---\n drivers/net/iavf/iavf_rxtx.c | 29 +++++++++++++++----------\n drivers/net/iavf/iavf_rxtx.h | 11 ++++++++++\n drivers/net/iavf/iavf_rxtx_vec_avx512.c | 8 ++-----\n drivers/net/iavf/iavf_rxtx_vec_sse.c | 16 ++++----------\n 4 files changed, 34 insertions(+), 30 deletions(-)", "diff": "diff --git a/drivers/net/iavf/iavf_rxtx.c b/drivers/net/iavf/iavf_rxtx.c\nindex 16e8d021f9..a4a6fcee10 100644\n--- a/drivers/net/iavf/iavf_rxtx.c\n+++ b/drivers/net/iavf/iavf_rxtx.c\n@@ -362,12 +362,17 @@ release_txq_mbufs(struct iavf_tx_queue *txq)\n \t}\n }\n \n-static const struct iavf_rxq_ops def_rxq_ops = {\n-\t.release_mbufs = release_rxq_mbufs,\n+static\n+struct iavf_rxq_ops iavf_rxq_release_mbufs_ops[] = {\n+\t[IAVF_REL_MBUFS_DEFAULT].release_mbufs = release_rxq_mbufs,\n+\t[IAVF_REL_MBUFS_SSE_VEC].release_mbufs = iavf_rx_queue_release_mbufs_sse,\n };\n \n-static const struct iavf_txq_ops def_txq_ops = {\n-\t.release_mbufs = release_txq_mbufs,\n+static\n+struct iavf_txq_ops iavf_txq_release_mbufs_ops[] = {\n+\t[IAVF_REL_MBUFS_DEFAULT].release_mbufs = release_txq_mbufs,\n+\t[IAVF_REL_MBUFS_SSE_VEC].release_mbufs = iavf_tx_queue_release_mbufs_sse,\n+\t[IAVF_REL_MBUFS_AVX512_VEC].release_mbufs = iavf_tx_queue_release_mbufs_avx512,\n };\n \n static inline void\n@@ -674,7 +679,7 @@ iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,\n \trxq->q_set = true;\n \tdev->data->rx_queues[queue_idx] = rxq;\n \trxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);\n-\trxq->ops = &def_rxq_ops;\n+\trxq->rel_mbufs_type = IAVF_REL_MBUFS_DEFAULT;\n \n \tif (check_rx_bulk_allow(rxq) == true) {\n \t\tPMD_INIT_LOG(DEBUG, \"Rx Burst Bulk Alloc Preconditions are \"\n@@ -811,7 +816,7 @@ iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,\n \ttxq->q_set = true;\n \tdev->data->tx_queues[queue_idx] = txq;\n \ttxq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);\n-\ttxq->ops = &def_txq_ops;\n+\ttxq->rel_mbufs_type = IAVF_REL_MBUFS_DEFAULT;\n \n \tif (check_tx_vec_allow(txq) == false) {\n \t\tstruct iavf_adapter *ad =\n@@ -943,7 +948,7 @@ iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)\n \t}\n \n \trxq = dev->data->rx_queues[rx_queue_id];\n-\trxq->ops->release_mbufs(rxq);\n+\tiavf_rxq_release_mbufs_ops[rxq->rel_mbufs_type].release_mbufs(rxq);\n \treset_rx_queue(rxq);\n \tdev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n \n@@ -971,7 +976,7 @@ iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n \t}\n \n \ttxq = dev->data->tx_queues[tx_queue_id];\n-\ttxq->ops->release_mbufs(txq);\n+\tiavf_txq_release_mbufs_ops[txq->rel_mbufs_type].release_mbufs(txq);\n \treset_tx_queue(txq);\n \tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n \n@@ -986,7 +991,7 @@ iavf_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t qid)\n \tif (!q)\n \t\treturn;\n \n-\tq->ops->release_mbufs(q);\n+\tiavf_rxq_release_mbufs_ops[q->rel_mbufs_type].release_mbufs(q);\n \trte_free(q->sw_ring);\n \trte_memzone_free(q->mz);\n \trte_free(q);\n@@ -1000,7 +1005,7 @@ iavf_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t qid)\n \tif (!q)\n \t\treturn;\n \n-\tq->ops->release_mbufs(q);\n+\tiavf_txq_release_mbufs_ops[q->rel_mbufs_type].release_mbufs(q);\n \trte_free(q->sw_ring);\n \trte_memzone_free(q->mz);\n \trte_free(q);\n@@ -1034,7 +1039,7 @@ iavf_stop_queues(struct rte_eth_dev *dev)\n \t\ttxq = dev->data->tx_queues[i];\n \t\tif (!txq)\n \t\t\tcontinue;\n-\t\ttxq->ops->release_mbufs(txq);\n+\t\tiavf_txq_release_mbufs_ops[txq->rel_mbufs_type].release_mbufs(txq);\n \t\treset_tx_queue(txq);\n \t\tdev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;\n \t}\n@@ -1042,7 +1047,7 @@ iavf_stop_queues(struct rte_eth_dev *dev)\n \t\trxq = dev->data->rx_queues[i];\n \t\tif (!rxq)\n \t\t\tcontinue;\n-\t\trxq->ops->release_mbufs(rxq);\n+\t\tiavf_rxq_release_mbufs_ops[rxq->rel_mbufs_type].release_mbufs(rxq);\n \t\treset_rx_queue(rxq);\n \t\tdev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;\n \t}\ndiff --git a/drivers/net/iavf/iavf_rxtx.h b/drivers/net/iavf/iavf_rxtx.h\nindex bf8aebbce8..48cc0da6f5 100644\n--- a/drivers/net/iavf/iavf_rxtx.h\n+++ b/drivers/net/iavf/iavf_rxtx.h\n@@ -187,6 +187,7 @@ struct iavf_rx_queue {\n \tstruct rte_mbuf *pkt_last_seg; /* last segment of current packet */\n \tstruct rte_mbuf fake_mbuf; /* dummy mbuf */\n \tuint8_t rxdid;\n+\tuint8_t rel_mbufs_type;\n \n \t/* used for VPMD */\n \tuint16_t rxrearm_nb; /* number of remaining to be re-armed */\n@@ -246,6 +247,7 @@ struct iavf_tx_queue {\n \tuint16_t last_desc_cleaned; /* last desc have been cleaned*/\n \tuint16_t free_thresh;\n \tuint16_t rs_thresh;\n+\tuint8_t rel_mbufs_type;\n \n \tuint16_t port_id;\n \tuint16_t queue_id;\n@@ -389,6 +391,12 @@ struct iavf_32b_rx_flex_desc_comms_ipsec {\n \t__le32 ipsec_said;\n };\n \n+enum iavf_rxtx_rel_mbufs_type {\n+\tIAVF_REL_MBUFS_DEFAULT\t\t= 0,\n+\tIAVF_REL_MBUFS_SSE_VEC\t\t= 1,\n+\tIAVF_REL_MBUFS_AVX512_VEC\t= 2,\n+};\n+\n /* Receive Flex Descriptor profile IDs: There are a total\n * of 64 profiles where profile IDs 0/1 are for legacy; and\n * profiles 2-63 are flex profiles that can be programmed\n@@ -692,6 +700,9 @@ int iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq);\n uint8_t iavf_proto_xtr_type_to_rxdid(uint8_t xtr_type);\n \n void iavf_set_default_ptype_table(struct rte_eth_dev *dev);\n+void iavf_tx_queue_release_mbufs_avx512(struct iavf_tx_queue *txq);\n+void iavf_rx_queue_release_mbufs_sse(struct iavf_rx_queue *rxq);\n+void iavf_tx_queue_release_mbufs_sse(struct iavf_tx_queue *txq);\n \n static inline\n void iavf_dump_rx_descriptor(struct iavf_rx_queue *rxq,\ndiff --git a/drivers/net/iavf/iavf_rxtx_vec_avx512.c b/drivers/net/iavf/iavf_rxtx_vec_avx512.c\nindex 7319d4cb65..3bfec63851 100644\n--- a/drivers/net/iavf/iavf_rxtx_vec_avx512.c\n+++ b/drivers/net/iavf/iavf_rxtx_vec_avx512.c\n@@ -1992,7 +1992,7 @@ iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,\n \treturn iavf_xmit_pkts_vec_avx512_cmn(tx_queue, tx_pkts, nb_pkts, false);\n }\n \n-static inline void\n+void __rte_cold\n iavf_tx_queue_release_mbufs_avx512(struct iavf_tx_queue *txq)\n {\n \tunsigned int i;\n@@ -2012,14 +2012,10 @@ iavf_tx_queue_release_mbufs_avx512(struct iavf_tx_queue *txq)\n \t}\n }\n \n-static const struct iavf_txq_ops avx512_vec_txq_ops = {\n-\t.release_mbufs = iavf_tx_queue_release_mbufs_avx512,\n-};\n-\n int __rte_cold\n iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq)\n {\n-\ttxq->ops = &avx512_vec_txq_ops;\n+\ttxq->rel_mbufs_type = IAVF_REL_MBUFS_AVX512_VEC;\n \treturn 0;\n }\n \ndiff --git a/drivers/net/iavf/iavf_rxtx_vec_sse.c b/drivers/net/iavf/iavf_rxtx_vec_sse.c\nindex 717a227b2c..4a5232c1d2 100644\n--- a/drivers/net/iavf/iavf_rxtx_vec_sse.c\n+++ b/drivers/net/iavf/iavf_rxtx_vec_sse.c\n@@ -1198,37 +1198,29 @@ iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,\n \treturn nb_tx;\n }\n \n-static void __rte_cold\n+void __rte_cold\n iavf_rx_queue_release_mbufs_sse(struct iavf_rx_queue *rxq)\n {\n \t_iavf_rx_queue_release_mbufs_vec(rxq);\n }\n \n-static void __rte_cold\n+void __rte_cold\n iavf_tx_queue_release_mbufs_sse(struct iavf_tx_queue *txq)\n {\n \t_iavf_tx_queue_release_mbufs_vec(txq);\n }\n \n-static const struct iavf_rxq_ops sse_vec_rxq_ops = {\n-\t.release_mbufs = iavf_rx_queue_release_mbufs_sse,\n-};\n-\n-static const struct iavf_txq_ops sse_vec_txq_ops = {\n-\t.release_mbufs = iavf_tx_queue_release_mbufs_sse,\n-};\n-\n int __rte_cold\n iavf_txq_vec_setup(struct iavf_tx_queue *txq)\n {\n-\ttxq->ops = &sse_vec_txq_ops;\n+\ttxq->rel_mbufs_type = IAVF_REL_MBUFS_SSE_VEC;\n \treturn 0;\n }\n \n int __rte_cold\n iavf_rxq_vec_setup(struct iavf_rx_queue *rxq)\n {\n-\trxq->ops = &sse_vec_rxq_ops;\n+\trxq->rel_mbufs_type = IAVF_REL_MBUFS_SSE_VEC;\n \treturn iavf_rxq_vec_setup_default(rxq);\n }\n \n", "prefixes": [ "v5" ] }