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GET /api/patches/110730/?format=api
{ "id": 110730, "url": "http://patches.dpdk.org/api/patches/110730/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220505125557.8828-28-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220505125557.8828-28-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220505125557.8828-28-ndabilpuram@marvell.com", "date": "2022-05-05T12:55:57", "name": "[v3,28/28] common/cnxk: add support for per-port RQ in inline device", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "d96384886de4e57cee159aac11accedad2bc79b6", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220505125557.8828-28-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 22796, "url": "http://patches.dpdk.org/api/series/22796/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22796", "date": "2022-05-05T12:55:30", "name": "[v3,01/28] common/cnxk: add multi channel support for SDP send queues", "version": 3, "mbox": "http://patches.dpdk.org/series/22796/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/110730/comments/", "check": "fail", "checks": "http://patches.dpdk.org/api/patches/110730/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0C9C8A04FF;\n\tThu, 5 May 2022 14:59:28 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id ECD534069F;\n\tThu, 5 May 2022 14:59:27 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id A46E340042\n for <dev@dpdk.org>; Thu, 5 May 2022 14:59:26 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.17.1.5/8.16.1.2) with ESMTP id\n 2457XGqN012012;\n Thu, 5 May 2022 05:57:22 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fuscx4yc6-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT);\n Thu, 05 May 2022 05:57:22 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2;\n Thu, 5 May 2022 05:57:21 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 5 May 2022 05:57:20 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 940303F704E;\n Thu, 5 May 2022 05:57:18 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=954vrayENF9XjUZGR4zWBor7DlFvafbZFIc64iUNyU4=;\n b=AEZq30Vg5y6HPKHYTixiFf+2EZ1w1eW8kCjG717MFi9thcSt7q5zs+4F/qwHJuOkHjUr\n G52IfTTLxTWkVrlwarz/BNtamNoABWH2pJo15dvbFukOmhxsqXmAJd0D2CvX7XLj/Qxe\n Sg4orLXmfF4/tKDQl9EqBEqslRlksofoFaQqyf3dNxmRCNoWj1CCjcLsxFhhOx340Z1a\n M51av/XBWvH3q1DpksOfKtgNCkGaSQc88E99X5C21z1HA3WqpoaQseo6Cbf2xIT/mwqL\n u94wULJ8VWyzZikUHOwB3lVZQXDr6MhysExUcZ80PPRC4ryWMxeGhmyX4wrk5YVYZkME vw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>, Ray Kinsella <mdr@ashroe.eu>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v3 28/28] common/cnxk: add support for per-port RQ in inline\n device", "Date": "Thu, 5 May 2022 18:25:57 +0530", "Message-ID": "<20220505125557.8828-28-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220505125557.8828-1-ndabilpuram@marvell.com>", "References": "<20220419055921.10566-1-ndabilpuram@marvell.com>\n <20220505125557.8828-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-GUID": "3gwKbDWqB5k3DRXrKV41d6Q85Fc_Q40H", "X-Proofpoint-ORIG-GUID": "3gwKbDWqB5k3DRXrKV41d6Q85Fc_Q40H", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514\n definitions=2022-05-05_05,2022-05-05_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for per port RQ in inline device thereby using\nAura/Pool attributes from that port specific first RQ.\nWhen inline device is used with channel masking, it will\nfallback to single RQ for all ethdev ports.\n\nAlso remove clamping up of CQ size for LBK ethdev when\ninline inbound is enabled as now backpressure is supported\neven on LBK ethdevs.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_nix.h | 2 +-\n drivers/common/cnxk/roc_nix_debug.c | 7 +-\n drivers/common/cnxk/roc_nix_inl.c | 81 ++++++++--------\n drivers/common/cnxk/roc_nix_inl.h | 5 +-\n drivers/common/cnxk/roc_nix_inl_dev.c | 42 ++++++--\n drivers/common/cnxk/roc_nix_inl_dev_irq.c | 155 +++++++++++++++++++-----------\n drivers/common/cnxk/roc_nix_inl_priv.h | 12 ++-\n drivers/common/cnxk/roc_npc.c | 13 ++-\n drivers/common/cnxk/version.map | 1 -\n drivers/net/cnxk/cnxk_ethdev.c | 14 +--\n 10 files changed, 202 insertions(+), 130 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_nix.h b/drivers/common/cnxk/roc_nix.h\nindex 1019e37..1c38af0 100644\n--- a/drivers/common/cnxk/roc_nix.h\n+++ b/drivers/common/cnxk/roc_nix.h\n@@ -309,7 +309,7 @@ struct roc_nix_rq {\n \tbool spb_drop_ena;\n \t/* End of Input parameters */\n \tstruct roc_nix *roc_nix;\n-\tbool inl_dev_ref;\n+\tuint16_t inl_dev_refs;\n };\n \n struct roc_nix_cq {\ndiff --git a/drivers/common/cnxk/roc_nix_debug.c b/drivers/common/cnxk/roc_nix_debug.c\nindex 1ae0451..e05e60d 100644\n--- a/drivers/common/cnxk/roc_nix_debug.c\n+++ b/drivers/common/cnxk/roc_nix_debug.c\n@@ -826,7 +826,7 @@ roc_nix_rq_dump(struct roc_nix_rq *rq)\n \tnix_dump(\" vwqe_wait_tmo = %ld\", rq->vwqe_wait_tmo);\n \tnix_dump(\" vwqe_aura_handle = %ld\", rq->vwqe_aura_handle);\n \tnix_dump(\" roc_nix = %p\", rq->roc_nix);\n-\tnix_dump(\" inl_dev_ref = %d\", rq->inl_dev_ref);\n+\tnix_dump(\" inl_dev_refs = %d\", rq->inl_dev_refs);\n }\n \n void\n@@ -1243,6 +1243,7 @@ roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev)\n \tstruct nix_inl_dev *inl_dev =\n \t\t(struct nix_inl_dev *)&roc_inl_dev->reserved;\n \tstruct dev *dev = &inl_dev->dev;\n+\tint i;\n \n \tnix_dump(\"nix_inl_dev@%p\", inl_dev);\n \tnix_dump(\" pf = %d\", dev_get_pf(dev->pf_func));\n@@ -1259,7 +1260,6 @@ roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev)\n \tnix_dump(\" \\tssow_msixoff = %d\", inl_dev->ssow_msixoff);\n \tnix_dump(\" \\tnix_cints = %d\", inl_dev->cints);\n \tnix_dump(\" \\tnix_qints = %d\", inl_dev->qints);\n-\tnix_dump(\" \\trq_refs = %d\", inl_dev->rq_refs);\n \tnix_dump(\" \\tinb_sa_base = 0x%p\", inl_dev->inb_sa_base);\n \tnix_dump(\" \\tinb_sa_sz = %d\", inl_dev->inb_sa_sz);\n \tnix_dump(\" \\txaq_buf_size = %u\", inl_dev->xaq_buf_size);\n@@ -1269,5 +1269,6 @@ roc_nix_inl_dev_dump(struct roc_nix_inl_dev *roc_inl_dev)\n \tnix_dump(\" \\txaq_mem = 0x%p\", inl_dev->xaq.mem);\n \n \tnix_dump(\" \\tinl_dev_rq:\");\n-\troc_nix_rq_dump(&inl_dev->rq);\n+\tfor (i = 0; i < inl_dev->nb_rqs; i++)\n+\t\troc_nix_rq_dump(&inl_dev->rqs[i]);\n }\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex 05c663d..28d01b0 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -585,8 +585,10 @@ int\n roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)\n {\n \tstruct idev_cfg *idev = idev_get_cfg();\n+\tint port_id = rq->roc_nix->port_id;\n \tstruct nix_inl_dev *inl_dev;\n \tstruct roc_nix_rq *inl_rq;\n+\tuint16_t inl_rq_id;\n \tstruct dev *dev;\n \tint rc;\n \n@@ -598,19 +600,24 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)\n \tif (!inl_dev)\n \t\treturn 0;\n \n+\t/* Check if this RQ is already holding reference */\n+\tif (rq->inl_dev_refs)\n+\t\treturn 0;\n+\n+\tinl_rq_id = inl_dev->nb_rqs > 1 ? port_id : 0;\n+\tdev = &inl_dev->dev;\n+\tinl_rq = &inl_dev->rqs[inl_rq_id];\n+\n \t/* Just take reference if already inited */\n-\tif (inl_dev->rq_refs) {\n-\t\tinl_dev->rq_refs++;\n-\t\trq->inl_dev_ref = true;\n+\tif (inl_rq->inl_dev_refs) {\n+\t\tinl_rq->inl_dev_refs++;\n+\t\trq->inl_dev_refs = 1;\n \t\treturn 0;\n \t}\n-\n-\tdev = &inl_dev->dev;\n-\tinl_rq = &inl_dev->rq;\n \tmemset(inl_rq, 0, sizeof(struct roc_nix_rq));\n \n \t/* Take RQ pool attributes from the first ethdev RQ */\n-\tinl_rq->qid = 0;\n+\tinl_rq->qid = inl_rq_id;\n \tinl_rq->aura_handle = rq->aura_handle;\n \tinl_rq->first_skip = rq->first_skip;\n \tinl_rq->later_skip = rq->later_skip;\n@@ -688,8 +695,8 @@ roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq)\n \t\treturn rc;\n \t}\n \n-\tinl_dev->rq_refs++;\n-\trq->inl_dev_ref = true;\n+\tinl_rq->inl_dev_refs++;\n+\trq->inl_dev_refs = 1;\n \treturn 0;\n }\n \n@@ -697,15 +704,17 @@ int\n roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq)\n {\n \tstruct idev_cfg *idev = idev_get_cfg();\n+\tint port_id = rq->roc_nix->port_id;\n \tstruct nix_inl_dev *inl_dev;\n \tstruct roc_nix_rq *inl_rq;\n+\tuint16_t inl_rq_id;\n \tstruct dev *dev;\n \tint rc;\n \n \tif (idev == NULL)\n \t\treturn 0;\n \n-\tif (!rq->inl_dev_ref)\n+\tif (!rq->inl_dev_refs)\n \t\treturn 0;\n \n \tinl_dev = idev->nix_inl_dev;\n@@ -715,13 +724,15 @@ roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq)\n \t\treturn -EFAULT;\n \t}\n \n-\trq->inl_dev_ref = false;\n-\tinl_dev->rq_refs--;\n-\tif (inl_dev->rq_refs)\n-\t\treturn 0;\n-\n \tdev = &inl_dev->dev;\n-\tinl_rq = &inl_dev->rq;\n+\tinl_rq_id = inl_dev->nb_rqs > 1 ? port_id : 0;\n+\tinl_rq = &inl_dev->rqs[inl_rq_id];\n+\n+\trq->inl_dev_refs = 0;\n+\tinl_rq->inl_dev_refs--;\n+\tif (inl_rq->inl_dev_refs)\n+\t\treturn 0;\n+\n \t/* There are no more references, disable RQ */\n \trc = nix_rq_ena_dis(dev, inl_rq, false);\n \tif (rc)\n@@ -737,25 +748,6 @@ roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq)\n \treturn rc;\n }\n \n-uint64_t\n-roc_nix_inl_dev_rq_limit_get(void)\n-{\n-\tstruct idev_cfg *idev = idev_get_cfg();\n-\tstruct nix_inl_dev *inl_dev;\n-\tstruct roc_nix_rq *inl_rq;\n-\n-\tif (!idev || !idev->nix_inl_dev)\n-\t\treturn 0;\n-\n-\tinl_dev = idev->nix_inl_dev;\n-\tif (!inl_dev->rq_refs)\n-\t\treturn 0;\n-\n-\tinl_rq = &inl_dev->rq;\n-\n-\treturn roc_npa_aura_op_limit_get(inl_rq->aura_handle);\n-}\n-\n void\n roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev)\n {\n@@ -804,15 +796,22 @@ roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix)\n }\n \n struct roc_nix_rq *\n-roc_nix_inl_dev_rq(void)\n+roc_nix_inl_dev_rq(struct roc_nix *roc_nix)\n {\n \tstruct idev_cfg *idev = idev_get_cfg();\n+\tint port_id = roc_nix->port_id;\n \tstruct nix_inl_dev *inl_dev;\n+\tstruct roc_nix_rq *inl_rq;\n+\tuint16_t inl_rq_id;\n \n \tif (idev != NULL) {\n \t\tinl_dev = idev->nix_inl_dev;\n-\t\tif (inl_dev != NULL && inl_dev->rq_refs)\n-\t\t\treturn &inl_dev->rq;\n+\t\tif (inl_dev != NULL) {\n+\t\t\tinl_rq_id = inl_dev->nb_rqs > 1 ? port_id : 0;\n+\t\t\tinl_rq = &inl_dev->rqs[inl_rq_id];\n+\t\t\tif (inl_rq->inl_dev_refs)\n+\t\t\t\treturn inl_rq;\n+\t\t}\n \t}\n \n \treturn NULL;\n@@ -1022,6 +1021,7 @@ roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev)\n \tvoid *sa, *sa_base = NULL;\n \tstruct nix *nix = NULL;\n \tuint16_t max_spi = 0;\n+\tuint32_t rq_refs = 0;\n \tuint8_t pkind = 0;\n \tint i;\n \n@@ -1044,7 +1044,10 @@ roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena, bool inb_inl_dev)\n \t}\n \n \tif (inl_dev) {\n-\t\tif (inl_dev->rq_refs == 0) {\n+\t\tfor (i = 0; i < inl_dev->nb_rqs; i++)\n+\t\t\trq_refs += inl_dev->rqs[i].inl_dev_refs;\n+\n+\t\tif (rq_refs == 0) {\n \t\t\tinl_dev->ts_ena = ts_ena;\n \t\t\tmax_spi = inl_dev->ipsec_in_max_spi;\n \t\t\tsa_base = inl_dev->inb_sa_base;\ndiff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nindex 633f090..7835ba3 100644\n--- a/drivers/common/cnxk/roc_nix_inl.h\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -168,12 +168,11 @@ void __roc_api roc_nix_inb_mode_set(struct roc_nix *roc_nix, bool use_inl_dev);\n int __roc_api roc_nix_inl_dev_rq_get(struct roc_nix_rq *rq);\n int __roc_api roc_nix_inl_dev_rq_put(struct roc_nix_rq *rq);\n bool __roc_api roc_nix_inb_is_with_inl_dev(struct roc_nix *roc_nix);\n-struct roc_nix_rq *__roc_api roc_nix_inl_dev_rq(void);\n+struct roc_nix_rq *__roc_api roc_nix_inl_dev_rq(struct roc_nix *roc_nix);\n int __roc_api roc_nix_inl_inb_tag_update(struct roc_nix *roc_nix,\n \t\t\t\t\t uint32_t tag_const, uint8_t tt);\n-uint64_t __roc_api roc_nix_inl_dev_rq_limit_get(void);\n int __roc_api roc_nix_reassembly_configure(uint32_t max_wait_time,\n-\t\t\t\t\tuint16_t max_frags);\n+\t\t\t\t\t uint16_t max_frags);\n int __roc_api roc_nix_inl_ts_pkind_set(struct roc_nix *roc_nix, bool ts_ena,\n \t\t\t\t bool inb_inl_dev);\n \ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev.c b/drivers/common/cnxk/roc_nix_inl_dev.c\nindex 5e61a42..b304937 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev.c\n@@ -334,6 +334,7 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)\n \tstruct nix_lf_alloc_rsp *rsp;\n \tstruct nix_lf_alloc_req *req;\n \tstruct nix_hw_info *hw_info;\n+\tstruct roc_nix_rq *rqs;\n \tuint64_t max_sa, i;\n \tsize_t inb_sa_sz;\n \tint rc = -ENOSPC;\n@@ -345,7 +346,8 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)\n \treq = mbox_alloc_msg_nix_lf_alloc(mbox);\n \tif (req == NULL)\n \t\treturn rc;\n-\treq->rq_cnt = 1;\n+\t/* We will have per-port RQ if it is not with channel masking */\n+\treq->rq_cnt = inl_dev->nb_rqs;\n \treq->sq_cnt = 1;\n \treq->cq_cnt = 1;\n \t/* XQESZ is W16 */\n@@ -421,6 +423,14 @@ nix_inl_nix_setup(struct nix_inl_dev *inl_dev)\n \t\tgoto free_mem;\n \t}\n \n+\t/* Allocate memory for RQ's */\n+\trqs = plt_zmalloc(sizeof(struct roc_nix_rq) * PLT_MAX_ETHPORTS, 0);\n+\tif (!rqs) {\n+\t\tplt_err(\"Failed to allocate memory for RQ's\");\n+\t\tgoto free_mem;\n+\t}\n+\tinl_dev->rqs = rqs;\n+\n \treturn 0;\n free_mem:\n \tplt_free(inl_dev->inb_sa_base);\n@@ -464,7 +474,15 @@ nix_inl_nix_release(struct nix_inl_dev *inl_dev)\n \tif (req == NULL)\n \t\treturn -ENOSPC;\n \n-\treturn mbox_process(mbox);\n+\trc = mbox_process(mbox);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tplt_free(inl_dev->rqs);\n+\tplt_free(inl_dev->inb_sa_base);\n+\tinl_dev->rqs = NULL;\n+\tinl_dev->inb_sa_base = NULL;\n+\treturn 0;\n }\n \n static int\n@@ -584,10 +602,13 @@ roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle)\n \n no_pool:\n \t/* Disable RQ if enabled */\n-\tif (inl_dev->rq_refs) {\n-\t\trc = nix_rq_ena_dis(&inl_dev->dev, &inl_dev->rq, false);\n+\tfor (i = 0; i < inl_dev->nb_rqs; i++) {\n+\t\tif (!inl_dev->rqs[i].inl_dev_refs)\n+\t\t\tcontinue;\n+\t\trc = nix_rq_ena_dis(&inl_dev->dev, &inl_dev->rqs[i], false);\n \t\tif (rc) {\n-\t\t\tplt_err(\"Failed to disable inline dev RQ, rc=%d\", rc);\n+\t\t\tplt_err(\"Failed to disable inline dev RQ %d, rc=%d\", i,\n+\t\t\t\trc);\n \t\t\treturn rc;\n \t\t}\n \t}\n@@ -633,10 +654,14 @@ roc_nix_inl_dev_xaq_realloc(uint64_t aura_handle)\n \n exit:\n \t/* Renable RQ */\n-\tif (inl_dev->rq_refs) {\n-\t\trc = nix_rq_ena_dis(&inl_dev->dev, &inl_dev->rq, true);\n+\tfor (i = 0; i < inl_dev->nb_rqs; i++) {\n+\t\tif (!inl_dev->rqs[i].inl_dev_refs)\n+\t\t\tcontinue;\n+\n+\t\trc = nix_rq_ena_dis(&inl_dev->dev, &inl_dev->rqs[i], true);\n \t\tif (rc)\n-\t\t\tplt_err(\"Failed to enable inline dev RQ, rc=%d\", rc);\n+\t\t\tplt_err(\"Failed to enable inline dev RQ %d, rc=%d\", i,\n+\t\t\t\trc);\n \t}\n \n \treturn rc;\n@@ -815,6 +840,7 @@ roc_nix_inl_dev_init(struct roc_nix_inl_dev *roc_inl_dev)\n \tinl_dev->spb_drop_pc = NIX_AURA_DROP_PC_DFLT;\n \tinl_dev->lpb_drop_pc = NIX_AURA_DROP_PC_DFLT;\n \tinl_dev->set_soft_exp_poll = roc_inl_dev->set_soft_exp_poll;\n+\tinl_dev->nb_rqs = inl_dev->is_multi_channel ? 1 : PLT_MAX_ETHPORTS;\n \n \tif (roc_inl_dev->spb_drop_pc)\n \t\tinl_dev->spb_drop_pc = roc_inl_dev->spb_drop_pc;\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c\nindex 1855f36..5fd4f0f 100644\n--- a/drivers/common/cnxk/roc_nix_inl_dev_irq.c\n+++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c\n@@ -179,50 +179,59 @@ nix_inl_sso_unregister_irqs(struct nix_inl_dev *inl_dev)\n static void\n nix_inl_nix_q_irq(void *param)\n {\n-\tstruct nix_inl_dev *inl_dev = (struct nix_inl_dev *)param;\n+\tstruct nix_inl_qint *qints_mem = (struct nix_inl_qint *)param;\n+\tstruct nix_inl_dev *inl_dev = qints_mem->inl_dev;\n \tuintptr_t nix_base = inl_dev->nix_base;\n \tstruct dev *dev = &inl_dev->dev;\n+\tuint16_t qint = qints_mem->qint;\n \tvolatile void *ctx;\n \tuint64_t reg, intr;\n+\tuint64_t wdata;\n \tuint8_t irq;\n-\tint rc;\n+\tint rc, q;\n \n-\tintr = plt_read64(nix_base + NIX_LF_QINTX_INT(0));\n+\tintr = plt_read64(nix_base + NIX_LF_QINTX_INT(qint));\n \tif (intr == 0)\n \t\treturn;\n \n \tplt_err(\"Queue_intr=0x%\" PRIx64 \" qintx 0 pf=%d, vf=%d\", intr, dev->pf,\n \t\tdev->vf);\n \n-\t/* Get and clear RQ0 interrupt */\n-\treg = roc_atomic64_add_nosync(0,\n-\t\t\t\t (int64_t *)(nix_base + NIX_LF_RQ_OP_INT));\n-\tif (reg & BIT_ULL(42) /* OP_ERR */) {\n-\t\tplt_err(\"Failed to get rq_int\");\n-\t\treturn;\n+\t/* Handle RQ interrupts */\n+\tfor (q = 0; q < inl_dev->nb_rqs; q++) {\n+\t\t/* Get and clear RQ interrupts */\n+\t\twdata = (uint64_t)q << 44;\n+\t\treg = roc_atomic64_add_nosync(wdata,\n+\t\t\t\t\t (int64_t *)(nix_base + NIX_LF_RQ_OP_INT));\n+\t\tif (reg & BIT_ULL(42) /* OP_ERR */) {\n+\t\t\tplt_err(\"Failed to get rq_int\");\n+\t\t\treturn;\n+\t\t}\n+\t\tirq = reg & 0xff;\n+\t\tplt_write64(wdata | irq, nix_base + NIX_LF_RQ_OP_INT);\n+\n+\t\tif (irq & BIT_ULL(NIX_RQINT_DROP))\n+\t\t\tplt_err(\"RQ=0 NIX_RQINT_DROP\");\n+\n+\t\tif (irq & BIT_ULL(NIX_RQINT_RED))\n+\t\t\tplt_err(\"RQ=0 NIX_RQINT_RED\");\n \t}\n-\tirq = reg & 0xff;\n-\tplt_write64(0 | irq, nix_base + NIX_LF_RQ_OP_INT);\n-\n-\tif (irq & BIT_ULL(NIX_RQINT_DROP))\n-\t\tplt_err(\"RQ=0 NIX_RQINT_DROP\");\n-\n-\tif (irq & BIT_ULL(NIX_RQINT_RED))\n-\t\tplt_err(\"RQ=0 NIX_RQINT_RED\");\n \n \t/* Clear interrupt */\n-\tplt_write64(intr, nix_base + NIX_LF_QINTX_INT(0));\n+\tplt_write64(intr, nix_base + NIX_LF_QINTX_INT(qint));\n \n \t/* Dump registers to std out */\n \tnix_inl_nix_reg_dump(inl_dev);\n \n-\t/* Dump RQ 0 */\n-\trc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, 0, &ctx);\n-\tif (rc) {\n-\t\tplt_err(\"Failed to get rq context\");\n-\t\treturn;\n+\t/* Dump RQs */\n+\tfor (q = 0; q < inl_dev->nb_rqs; q++) {\n+\t\trc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, q, &ctx);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to get rq %d context, rc=%d\", q, rc);\n+\t\t\tcontinue;\n+\t\t}\n+\t\tnix_lf_rq_dump(ctx);\n \t}\n-\tnix_lf_rq_dump(ctx);\n }\n \n static void\n@@ -233,7 +242,7 @@ nix_inl_nix_ras_irq(void *param)\n \tstruct dev *dev = &inl_dev->dev;\n \tvolatile void *ctx;\n \tuint64_t intr;\n-\tint rc;\n+\tint rc, q;\n \n \tintr = plt_read64(nix_base + NIX_LF_RAS);\n \tif (intr == 0)\n@@ -246,13 +255,15 @@ nix_inl_nix_ras_irq(void *param)\n \t/* Dump registers to std out */\n \tnix_inl_nix_reg_dump(inl_dev);\n \n-\t/* Dump RQ 0 */\n-\trc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, 0, &ctx);\n-\tif (rc) {\n-\t\tplt_err(\"Failed to get rq context\");\n-\t\treturn;\n+\t/* Dump RQs */\n+\tfor (q = 0; q < inl_dev->nb_rqs; q++) {\n+\t\trc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, q, &ctx);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to get rq %d context, rc=%d\", q, rc);\n+\t\t\tcontinue;\n+\t\t}\n+\t\tnix_lf_rq_dump(ctx);\n \t}\n-\tnix_lf_rq_dump(ctx);\n }\n \n static void\n@@ -263,7 +274,7 @@ nix_inl_nix_err_irq(void *param)\n \tstruct dev *dev = &inl_dev->dev;\n \tvolatile void *ctx;\n \tuint64_t intr;\n-\tint rc;\n+\tint rc, q;\n \n \tintr = plt_read64(nix_base + NIX_LF_ERR_INT);\n \tif (intr == 0)\n@@ -277,13 +288,15 @@ nix_inl_nix_err_irq(void *param)\n \t/* Dump registers to std out */\n \tnix_inl_nix_reg_dump(inl_dev);\n \n-\t/* Dump RQ 0 */\n-\trc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, 0, &ctx);\n-\tif (rc) {\n-\t\tplt_err(\"Failed to get rq context\");\n-\t\treturn;\n+\t/* Dump RQs */\n+\tfor (q = 0; q < inl_dev->nb_rqs; q++) {\n+\t\trc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, q, &ctx);\n+\t\tif (rc) {\n+\t\t\tplt_err(\"Failed to get rq %d context, rc=%d\", q, rc);\n+\t\t\tcontinue;\n+\t\t}\n+\t\tnix_lf_rq_dump(ctx);\n \t}\n-\tnix_lf_rq_dump(ctx);\n }\n \n int\n@@ -291,8 +304,10 @@ nix_inl_nix_register_irqs(struct nix_inl_dev *inl_dev)\n {\n \tstruct plt_intr_handle *handle = inl_dev->pci_dev->intr_handle;\n \tuintptr_t nix_base = inl_dev->nix_base;\n+\tstruct nix_inl_qint *qints_mem;\n \tuint16_t msixoff;\n-\tint rc;\n+\tint rc, q, ret;\n+\tint qints;\n \n \tmsixoff = inl_dev->nix_msixoff;\n \tif (msixoff == MSIX_VECTOR_INVALID) {\n@@ -317,21 +332,38 @@ nix_inl_nix_register_irqs(struct nix_inl_dev *inl_dev)\n \t/* Enable RAS interrupts */\n \tplt_write64(~0ull, nix_base + NIX_LF_RAS_ENA_W1S);\n \n-\t/* Setup queue irq for RQ 0 */\n+\t/* Setup queue irq for RQ's */\n+\tqints = PLT_MIN(inl_dev->nb_rqs, inl_dev->qints);\n+\tqints_mem = plt_zmalloc(sizeof(struct nix_inl_qint) * qints, 0);\n+\tif (!qints_mem) {\n+\t\tplt_err(\"Failed to allocate memory for %u qints\", qints);\n+\t\treturn -ENOMEM;\n+\t}\n \n-\t/* Clear QINT CNT, interrupt */\n-\tplt_write64(0, nix_base + NIX_LF_QINTX_CNT(0));\n-\tplt_write64(~0ull, nix_base + NIX_LF_QINTX_ENA_W1C(0));\n+\tinl_dev->configured_qints = qints;\n+\tinl_dev->qints_mem = qints_mem;\n \n-\t/* Register queue irq vector */\n-\trc |= dev_irq_register(handle, nix_inl_nix_q_irq, inl_dev,\n-\t\t\t msixoff + NIX_LF_INT_VEC_QINT_START);\n+\tfor (q = 0; q < qints; q++) {\n+\t\t/* Clear QINT CNT, interrupt */\n+\t\tplt_write64(0, nix_base + NIX_LF_QINTX_CNT(q));\n+\t\tplt_write64(~0ull, nix_base + NIX_LF_QINTX_ENA_W1C(q));\n \n-\tplt_write64(0, nix_base + NIX_LF_QINTX_CNT(0));\n-\tplt_write64(0, nix_base + NIX_LF_QINTX_INT(0));\n-\t/* Enable QINT interrupt */\n-\tplt_write64(~0ull, nix_base + NIX_LF_QINTX_ENA_W1S(0));\n+\t\t/* Register queue irq vector */\n+\t\tret = dev_irq_register(handle, nix_inl_nix_q_irq, &qints_mem[q],\n+\t\t\t\t msixoff + NIX_LF_INT_VEC_QINT_START + q);\n+\t\tif (ret)\n+\t\t\tbreak;\n \n+\t\tplt_write64(0, nix_base + NIX_LF_QINTX_CNT(q));\n+\t\tplt_write64(0, nix_base + NIX_LF_QINTX_INT(q));\n+\t\t/* Enable QINT interrupt */\n+\t\tplt_write64(~0ull, nix_base + NIX_LF_QINTX_ENA_W1S(q));\n+\n+\t\tqints_mem[q].inl_dev = inl_dev;\n+\t\tqints_mem[q].qint = q;\n+\t}\n+\n+\trc |= ret;\n \treturn rc;\n }\n \n@@ -339,8 +371,10 @@ void\n nix_inl_nix_unregister_irqs(struct nix_inl_dev *inl_dev)\n {\n \tstruct plt_intr_handle *handle = inl_dev->pci_dev->intr_handle;\n+\tstruct nix_inl_qint *qints_mem = inl_dev->qints_mem;\n \tuintptr_t nix_base = inl_dev->nix_base;\n \tuint16_t msixoff;\n+\tint q;\n \n \tmsixoff = inl_dev->nix_msixoff;\n \t/* Disable err interrupts */\n@@ -353,14 +387,19 @@ nix_inl_nix_unregister_irqs(struct nix_inl_dev *inl_dev)\n \tdev_irq_unregister(handle, nix_inl_nix_ras_irq, inl_dev,\n \t\t\t msixoff + NIX_LF_INT_VEC_POISON);\n \n-\t/* Clear QINT CNT */\n-\tplt_write64(0, nix_base + NIX_LF_QINTX_CNT(0));\n-\tplt_write64(0, nix_base + NIX_LF_QINTX_INT(0));\n+\tfor (q = 0; q < inl_dev->configured_qints; q++) {\n+\t\t/* Clear QINT CNT */\n+\t\tplt_write64(0, nix_base + NIX_LF_QINTX_CNT(q));\n+\t\tplt_write64(0, nix_base + NIX_LF_QINTX_INT(q));\n \n-\t/* Disable QINT interrupt */\n-\tplt_write64(~0ull, nix_base + NIX_LF_QINTX_ENA_W1C(0));\n+\t\t/* Disable QINT interrupt */\n+\t\tplt_write64(~0ull, nix_base + NIX_LF_QINTX_ENA_W1C(q));\n \n-\t/* Unregister queue irq vector */\n-\tdev_irq_unregister(handle, nix_inl_nix_q_irq, inl_dev,\n-\t\t\t msixoff + NIX_LF_INT_VEC_QINT_START);\n+\t\t/* Unregister queue irq vector */\n+\t\tdev_irq_unregister(handle, nix_inl_nix_q_irq, &qints_mem[q],\n+\t\t\t\t msixoff + NIX_LF_INT_VEC_QINT_START + q);\n+\t}\n+\n+\tplt_free(inl_dev->qints_mem);\n+\tinl_dev->qints_mem = NULL;\n }\ndiff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h\nindex 1ab8470..d61c7b2 100644\n--- a/drivers/common/cnxk/roc_nix_inl_priv.h\n+++ b/drivers/common/cnxk/roc_nix_inl_priv.h\n@@ -6,6 +6,12 @@\n #include <pthread.h>\n #include <sys/types.h>\n \n+struct nix_inl_dev;\n+struct nix_inl_qint {\n+\tstruct nix_inl_dev *inl_dev;\n+\tuint16_t qint;\n+};\n+\n struct nix_inl_dev {\n \t/* Base device object */\n \tstruct dev dev;\n@@ -42,8 +48,10 @@ struct nix_inl_dev {\n \tuint16_t vwqe_interval;\n \tuint16_t cints;\n \tuint16_t qints;\n-\tstruct roc_nix_rq rq;\n-\tuint16_t rq_refs;\n+\tuint16_t configured_qints;\n+\tstruct roc_nix_rq *rqs;\n+\tstruct nix_inl_qint *qints_mem;\n+\tuint16_t nb_rqs;\n \tbool is_nix1;\n \tuint8_t spb_drop_pc;\n \tuint8_t lpb_drop_pc;\ndiff --git a/drivers/common/cnxk/roc_npc.c b/drivers/common/cnxk/roc_npc.c\nindex 51e36f1..3dee1ff 100644\n--- a/drivers/common/cnxk/roc_npc.c\n+++ b/drivers/common/cnxk/roc_npc.c\n@@ -307,6 +307,7 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,\n \tbool vlan_insert_action = false;\n \tint sel_act, req_act = 0;\n \tuint16_t pf_func, vf_id;\n+\tstruct roc_nix *roc_nix;\n \tint errcode = 0;\n \tint mark = 0;\n \tint rq = 0;\n@@ -392,11 +393,19 @@ npc_parse_actions(struct roc_npc *roc_npc, const struct roc_npc_attr *attr,\n \t\t\t */\n \t\t\treq_act |= ROC_NPC_ACTION_TYPE_SEC;\n \t\t\trq = 0;\n+\t\t\troc_nix = roc_npc->roc_nix;\n \n \t\t\t/* Special processing when with inline device */\n-\t\t\tif (roc_nix_inb_is_with_inl_dev(roc_npc->roc_nix) &&\n+\t\t\tif (roc_nix_inb_is_with_inl_dev(roc_nix) &&\n \t\t\t roc_nix_inl_dev_is_probed()) {\n-\t\t\t\trq = 0;\n+\t\t\t\tstruct roc_nix_rq *inl_rq;\n+\n+\t\t\t\tinl_rq = roc_nix_inl_dev_rq(roc_nix);\n+\t\t\t\tif (!inl_rq) {\n+\t\t\t\t\terrcode = NPC_ERR_INTERNAL;\n+\t\t\t\t\tgoto err_exit;\n+\t\t\t\t}\n+\t\t\t\trq = inl_rq->qid;\n \t\t\t\tpf_func = nix_inl_dev_pffunc_get();\n \t\t\t}\n \t\t\tbreak;\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 53586da..a77f3f6 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -138,7 +138,6 @@ INTERNAL {\n \troc_nix_inl_dev_rq;\n \troc_nix_inl_dev_rq_get;\n \troc_nix_inl_dev_rq_put;\n-\troc_nix_inl_dev_rq_limit_get;\n \troc_nix_inl_dev_unlock;\n \troc_nix_inl_dev_xaq_realloc;\n \troc_nix_inl_inb_is_enabled;\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 3912c24..09e5736 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -546,19 +546,6 @@ cnxk_nix_rx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t qid,\n \t\teth_dev->data->rx_queues[qid] = NULL;\n \t}\n \n-\t/* Clam up cq limit to size of packet pool aura for LBK\n-\t * to avoid meta packet drop as LBK does not currently support\n-\t * backpressure.\n-\t */\n-\tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY && roc_nix_is_lbk(nix)) {\n-\t\tuint64_t pkt_pool_limit = roc_nix_inl_dev_rq_limit_get();\n-\n-\t\t/* Use current RQ's aura limit if inl rq is not available */\n-\t\tif (!pkt_pool_limit)\n-\t\t\tpkt_pool_limit = roc_npa_aura_op_limit_get(mp->pool_id);\n-\t\tnb_desc = RTE_MAX(nb_desc, pkt_pool_limit);\n-\t}\n-\n \t/* Its a no-op when inline device is not used */\n \tif (dev->rx_offloads & RTE_ETH_RX_OFFLOAD_SECURITY ||\n \t dev->tx_offloads & RTE_ETH_TX_OFFLOAD_SECURITY)\n@@ -1675,6 +1662,7 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)\n \t/* Initialize base roc nix */\n \tnix->pci_dev = pci_dev;\n \tnix->hw_vlan_ins = true;\n+\tnix->port_id = eth_dev->data->port_id;\n \trc = roc_nix_dev_init(nix);\n \tif (rc) {\n \t\tplt_err(\"Failed to initialize roc nix rc=%d\", rc);\n", "prefixes": [ "v3", "28/28" ] }