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GET /api/patches/110573/?format=api
{ "id": 110573, "url": "http://patches.dpdk.org/api/patches/110573/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220502194557.16016-6-pagupta@vmware.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220502194557.16016-6-pagupta@vmware.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220502194557.16016-6-pagupta@vmware.com", "date": "2022-05-02T19:45:54", "name": "[5/8] vmxnet3, version 6", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "554661ab431c60bde421e4c67193ca82632f0e1f", "submitter": { "id": 2677, "url": "http://patches.dpdk.org/api/people/2677/?format=api", "name": "Pankaj Gupta", "email": "pagupta@vmware.com" }, "delegate": { "id": 3961, "url": "http://patches.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220502194557.16016-6-pagupta@vmware.com/mbox/", "series": [ { "id": 22762, "url": "http://patches.dpdk.org/api/series/22762/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22762", "date": "2022-05-02T19:45:49", "name": "vmxnet3: V5 and V6", "version": 1, "mbox": "http://patches.dpdk.org/series/22762/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/110573/comments/", "check": "warning", "checks": "http://patches.dpdk.org/api/patches/110573/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", 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header.d=none;dmarc=none action=none header.from=vmware.com;", "From": "Pankaj Gupta <pagupta@vmware.com>", "To": "jbehrens@vmware.com,\n\tyongwang@vmware.com", "Cc": "dev@dpdk.org,\n\tpagupta@vmware.com", "Subject": "[PATCH 5/8] vmxnet3, version 6", "Date": "Mon, 2 May 2022 15:45:54 -0400", "Message-Id": "<20220502194557.16016-6-pagupta@vmware.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20220502194557.16016-1-pagupta@vmware.com>", "References": "<20220502194557.16016-1-pagupta@vmware.com>", "Content-Type": "text/plain", "X-ClientProxiedBy": "BYAPR01CA0049.prod.exchangelabs.com (2603:10b6:a03:94::26)\n To BYAPR05MB5624.namprd05.prod.outlook.com\n (2603:10b6:a03:1d::13)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "77ca3734-c76d-47b8-6bf7-08da2c74999c", "X-MS-TrafficTypeDiagnostic": "MWHPR05MB3294:EE_", "X-Microsoft-Antispam-PRVS": "\n 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"X-OriginatorOrg": "vmware.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 77ca3734-c76d-47b8-6bf7-08da2c74999c", "X-MS-Exchange-CrossTenant-AuthSource": "BYAPR05MB5624.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "02 May 2022 19:47:33.3371 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "b39138ca-3cee-4b4a-a4d6-cd83d9dd62f0", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n 2zGOaZsgSnzBDJK29bpr3h1VyDb6anNF18Vg3PJrnQgMkdQrZIvDldP3n2bwpJZT9n6OOfAMIuZodpfN9+Z57A==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR05MB3294", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "vmxnet3 version 6 supports some new features, including but\nnot limited to:\n- Increased max MTU up to 9190\n- Increased max number of queues, both for RX and TX\n- Removes power-of-two limitations\n- Extended interrupt structures, required implementation for\n additional number of queues\n\nTested, using testpmd, for different hardware version on\nESXi 7.0 Update 2.\n\nSigned-off-by: Pankaj Gupta <pagupta@vmware.com>\n---\n drivers/net/vmxnet3/base/vmxnet3_defs.h | 135 +++++++++-----\n drivers/net/vmxnet3/vmxnet3_ethdev.c | 222 +++++++++++++++++-------\n drivers/net/vmxnet3/vmxnet3_ethdev.h | 10 +-\n drivers/net/vmxnet3/vmxnet3_rxtx.c | 2 +-\n 4 files changed, 259 insertions(+), 110 deletions(-)", "diff": "diff --git a/drivers/net/vmxnet3/base/vmxnet3_defs.h b/drivers/net/vmxnet3/base/vmxnet3_defs.h\nindex 8d62b3e116..ceac5d64db 100644\n--- a/drivers/net/vmxnet3/base/vmxnet3_defs.h\n+++ b/drivers/net/vmxnet3/base/vmxnet3_defs.h\n@@ -72,38 +72,42 @@\n #endif\n \n typedef enum {\n- VMXNET3_CMD_FIRST_SET = 0xCAFE0000,\n- VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,\n- VMXNET3_CMD_QUIESCE_DEV,\n- VMXNET3_CMD_RESET_DEV,\n- VMXNET3_CMD_UPDATE_RX_MODE,\n- VMXNET3_CMD_UPDATE_MAC_FILTERS,\n- VMXNET3_CMD_UPDATE_VLAN_FILTERS,\n- VMXNET3_CMD_UPDATE_RSSIDT,\n- VMXNET3_CMD_UPDATE_IML,\n- VMXNET3_CMD_UPDATE_PMCFG,\n- VMXNET3_CMD_UPDATE_FEATURE,\n- VMXNET3_CMD_STOP_EMULATION,\n- VMXNET3_CMD_LOAD_PLUGIN,\n- VMXNET3_CMD_ACTIVATE_VF,\n- VMXNET3_CMD_RESERVED3,\n- VMXNET3_CMD_RESERVED4,\n- VMXNET3_CMD_REGISTER_MEMREGS,\n- VMXNET3_CMD_SET_RSS_FIELDS,\n-\n- VMXNET3_CMD_FIRST_GET = 0xF00D0000,\n- VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,\n- VMXNET3_CMD_GET_STATS,\n- VMXNET3_CMD_GET_LINK,\n- VMXNET3_CMD_GET_PERM_MAC_LO,\n- VMXNET3_CMD_GET_PERM_MAC_HI,\n- VMXNET3_CMD_GET_DID_LO,\n- VMXNET3_CMD_GET_DID_HI,\n- VMXNET3_CMD_GET_DEV_EXTRA_INFO,\n- VMXNET3_CMD_GET_CONF_INTR,\n- VMXNET3_CMD_GET_ADAPTIVE_RING_INFO,\n- VMXNET3_CMD_GET_TXDATA_DESC_SIZE,\n- VMXNET3_CMD_RESERVED5,\n+\tVMXNET3_CMD_FIRST_SET = 0xCAFE0000,\n+\tVMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,\n+\tVMXNET3_CMD_QUIESCE_DEV,\n+\tVMXNET3_CMD_RESET_DEV,\n+\tVMXNET3_CMD_UPDATE_RX_MODE,\n+\tVMXNET3_CMD_UPDATE_MAC_FILTERS,\n+\tVMXNET3_CMD_UPDATE_VLAN_FILTERS,\n+\tVMXNET3_CMD_UPDATE_RSSIDT,\n+\tVMXNET3_CMD_UPDATE_IML,\n+\tVMXNET3_CMD_UPDATE_PMCFG,\n+\tVMXNET3_CMD_UPDATE_FEATURE,\n+\tVMXNET3_CMD_STOP_EMULATION,\n+\tVMXNET3_CMD_LOAD_PLUGIN,\n+\tVMXNET3_CMD_ACTIVATE_VF,\n+\tVMXNET3_CMD_RESERVED3,\n+\tVMXNET3_CMD_RESERVED4,\n+\tVMXNET3_CMD_REGISTER_MEMREGS,\n+\tVMXNET3_CMD_SET_RSS_FIELDS,\n+\n+\tVMXNET3_CMD_FIRST_GET = 0xF00D0000,\n+\tVMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,\n+\tVMXNET3_CMD_GET_STATS,\n+\tVMXNET3_CMD_GET_LINK,\n+\tVMXNET3_CMD_GET_PERM_MAC_LO,\n+\tVMXNET3_CMD_GET_PERM_MAC_HI,\n+\tVMXNET3_CMD_GET_DID_LO,\n+\tVMXNET3_CMD_GET_DID_HI,\n+\tVMXNET3_CMD_GET_DEV_EXTRA_INFO,\n+\tVMXNET3_CMD_GET_CONF_INTR,\n+\tVMXNET3_CMD_GET_ADAPTIVE_RING_INFO,\n+\tVMXNET3_CMD_GET_TXDATA_DESC_SIZE,\n+\tVMXNET3_CMD_RESERVED5,\n+\tVMXNET3_CMD_RESERVED6,\n+\tVMXNET3_CMD_RESERVED7,\n+\tVMXNET3_CMD_RESERVED8,\n+\tVMXNET3_CMD_GET_MAX_QUEUES_CONF,\n } Vmxnet3_Cmd;\n \n /* Adaptive Ring Info Flags */\n@@ -571,6 +575,24 @@ enum vmxnet3_intr_type {\n /* addition 1 for events */\n #define VMXNET3_MAX_INTRS 25\n \n+/* Version 6 and later will use below macros */\n+#define VMXNET3_EXT_MAX_TX_QUEUES 32\n+#define VMXNET3_EXT_MAX_RX_QUEUES 32\n+\n+/* Version-dependent MAX RX/TX queues macro */\n+#define MAX_RX_QUEUES \\\n+\t(VMXNET3_VERSION_GE_6(hw) ? \\\n+\tVMXNET3_EXT_MAX_RX_QUEUES : \\\n+\tVMXNET3_MAX_RX_QUEUES)\n+#define MAX_TX_QUEUES \\\n+\t(VMXNET3_VERSION_GE_6(hw) ? \\\n+\tVMXNET3_EXT_MAX_TX_QUEUES : \\\n+\tVMXNET3_MAX_TX_QUEUES)\n+\n+/* addition 1 for events */\n+#define VMXNET3_EXT_MAX_INTRS 65\n+#define VMXNET3_FIRST_SET_INTRS 64\n+\n /* value of intrCtrl */\n #define VMXNET3_IC_DISABLE_ALL 0x1 /* bit 0 */\n \n@@ -587,6 +609,21 @@ struct Vmxnet3_IntrConf {\n #include \"vmware_pack_end.h\"\n Vmxnet3_IntrConf;\n \n+typedef\n+#include \"vmware_pack_begin.h\"\n+struct Vmxnet3_IntrConfExt {\n+\tuint8 autoMask;\n+\tuint8 numIntrs; /* # of interrupts */\n+\tuint8 eventIntrIdx;\n+\tuint8 reserved;\n+\t__le32 intrCtrl;\n+\t__le32 reserved1;\n+\tuint8 modLevels[VMXNET3_EXT_MAX_INTRS]; /* moderation level for each intr */\n+\tuint8 reserved2[3];\n+}\n+#include \"vmware_pack_end.h\"\n+Vmxnet3_IntrConfExt;\n+\n /* one bit per VLAN ID, the size is in the units of uint32 */\n #define VMXNET3_VFT_SIZE (4096 / (sizeof(uint32) * 8))\n \n@@ -692,6 +729,15 @@ struct Vmxnet3_DSDevRead {\n #include \"vmware_pack_end.h\"\n Vmxnet3_DSDevRead;\n \n+typedef\n+#include \"vmware_pack_begin.h\"\n+struct Vmxnet3_DSDevReadExt {\n+\t/* read-only region for device, read by dev in response to a SET cmd */\n+\tstruct Vmxnet3_IntrConfExt intrConfExt;\n+}\n+#include \"vmware_pack_end.h\"\n+Vmxnet3_DSDevReadExt;\n+\n typedef\n #include \"vmware_pack_begin.h\"\n struct Vmxnet3_TxQueueDesc {\n@@ -778,18 +824,18 @@ Vmxnet3_CmdInfo;\n typedef\n #include \"vmware_pack_begin.h\"\n struct Vmxnet3_DriverShared {\n- __le32 magic;\n- __le32 pad; /* make devRead start at 64-bit boundaries */\n- Vmxnet3_DSDevRead devRead;\n- __le32 ecr;\n- __le32 reserved;\n-\n- union {\n- __le32 reserved1[4];\n- Vmxnet3_CmdInfo cmdInfo; /* only valid in the context of executing the\n-\t\t\t\t * relevant command\n-\t\t\t\t */\n- } cu;\n+\t__le32 magic;\n+\t__le32 size; /* size of DriverShared */\n+\tVmxnet3_DSDevRead devRead;\n+\t__le32 ecr;\n+\t__le32 reserved;\n+\n+\tunion {\n+\t\t__le32\t\t\treserved1[4];\n+\t\t/* only valid in the context of executing the relevant command */\n+\t\tVmxnet3_CmdInfo\tcmdInfo;\n+\t} cu;\n+\tstruct Vmxnet3_DSDevReadExt devReadExt;\n }\n #include \"vmware_pack_end.h\"\n Vmxnet3_DriverShared;\n@@ -821,6 +867,7 @@ do {\\\n ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)\n \n #define VMXNET3_MAX_MTU 9000\n+#define VMXNET3_V6_MAX_MTU 9190\n #define VMXNET3_MIN_MTU 60\n \n #define VMXNET3_LINK_UP (10000 << 16 | 1) // 10 Gbps, up\ndiff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.c b/drivers/net/vmxnet3/vmxnet3_ethdev.c\nindex f77399f145..e213b6d864 100644\n--- a/drivers/net/vmxnet3/vmxnet3_ethdev.c\n+++ b/drivers/net/vmxnet3/vmxnet3_ethdev.c\n@@ -222,24 +222,20 @@ vmxnet3_disable_intr(struct vmxnet3_hw *hw, unsigned int intr_idx)\n }\n \n /*\n- * Enable all intrs used by the device\n+ * Simple helper to get intrCtrl and eventIntrIdx based on config and hw version\n */\n static void\n-vmxnet3_enable_all_intrs(struct vmxnet3_hw *hw)\n+vmxnet3_get_intr_ctrl_ev(struct vmxnet3_hw *hw,\n+\t\t\t uint8 **out_eventIntrIdx,\n+\t\t\t uint32 **out_intrCtrl)\n {\n-\tVmxnet3_DSDevRead *devRead = &hw->shared->devRead;\n-\n-\tPMD_INIT_FUNC_TRACE();\n \n-\tdevRead->intrConf.intrCtrl &= rte_cpu_to_le_32(~VMXNET3_IC_DISABLE_ALL);\n-\n-\tif (hw->intr.lsc_only) {\n-\t\tvmxnet3_enable_intr(hw, devRead->intrConf.eventIntrIdx);\n+\tif (VMXNET3_VERSION_GE_6(hw) && hw->queuesExtEnabled) {\n+\t\t*out_eventIntrIdx = &hw->shared->devReadExt.intrConfExt.eventIntrIdx;\n+\t\t*out_intrCtrl = &hw->shared->devReadExt.intrConfExt.intrCtrl;\n \t} else {\n-\t\tint i;\n-\n-\t\tfor (i = 0; i < hw->intr.num_intrs; i++)\n-\t\t\tvmxnet3_enable_intr(hw, i);\n+\t\t*out_eventIntrIdx = &hw->shared->devRead.intrConf.eventIntrIdx;\n+\t\t*out_intrCtrl = &hw->shared->devRead.intrConf.intrCtrl;\n \t}\n }\n \n@@ -250,15 +246,42 @@ static void\n vmxnet3_disable_all_intrs(struct vmxnet3_hw *hw)\n {\n \tint i;\n+\tuint8 *eventIntrIdx;\n+\tuint32 *intrCtrl;\n \n \tPMD_INIT_FUNC_TRACE();\n+\tvmxnet3_get_intr_ctrl_ev(hw, &eventIntrIdx, &intrCtrl);\n+\n+\t*intrCtrl |= rte_cpu_to_le_32(VMXNET3_IC_DISABLE_ALL);\n \n-\thw->shared->devRead.intrConf.intrCtrl |=\n-\t\trte_cpu_to_le_32(VMXNET3_IC_DISABLE_ALL);\n-\tfor (i = 0; i < hw->num_intrs; i++)\n+\tfor (i = 0; i < hw->intr.num_intrs; i++)\n \t\tvmxnet3_disable_intr(hw, i);\n }\n \n+/*\n+ * Enable all intrs used by the device\n+ */\n+static void\n+vmxnet3_enable_all_intrs(struct vmxnet3_hw *hw)\n+{\n+\tuint8 *eventIntrIdx;\n+\tuint32 *intrCtrl;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\tvmxnet3_get_intr_ctrl_ev(hw, &eventIntrIdx, &intrCtrl);\n+\n+\t*intrCtrl &= rte_cpu_to_le_32(~VMXNET3_IC_DISABLE_ALL);\n+\n+\tif (hw->intr.lsc_only) {\n+\t\tvmxnet3_enable_intr(hw, *eventIntrIdx);\n+\t} else {\n+\t\tint i;\n+\n+\t\tfor (i = 0; i < hw->intr.num_intrs; i++)\n+\t\t\tvmxnet3_enable_intr(hw, i);\n+\t}\n+}\n+\n /*\n * Gets tx data ring descriptor size.\n */\n@@ -333,7 +356,11 @@ eth_vmxnet3_dev_init(struct rte_eth_dev *eth_dev)\n \t/* Check h/w version compatibility with driver. */\n \tver = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_VRRS);\n \n-\tif (ver & (1 << VMXNET3_REV_5)) {\n+\tif (ver & (1 << VMXNET3_REV_6)) {\n+\t\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,\n+\t\t\t\t 1 << VMXNET3_REV_6);\n+\t\thw->version = VMXNET3_REV_6 + 1;\n+\t} else if (ver & (1 << VMXNET3_REV_5)) {\n \t\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_VRRS,\n \t\t\t\t 1 << VMXNET3_REV_5);\n \t\thw->version = VMXNET3_REV_5 + 1;\n@@ -508,15 +535,22 @@ vmxnet3_dev_configure(struct rte_eth_dev *dev)\n \tif (dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)\n \t\tdev->data->dev_conf.rxmode.offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH;\n \n-\tif (dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES ||\n-\t dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES) {\n-\t\tPMD_INIT_LOG(ERR, \"ERROR: Number of queues not supported\");\n-\t\treturn -EINVAL;\n+\tif (!VMXNET3_VERSION_GE_6(hw)) {\n+\t\tif (!rte_is_power_of_2(dev->data->nb_rx_queues)) {\n+\t\t\tPMD_INIT_LOG(ERR,\n+\t\t\t\t \"ERROR: Number of rx queues not power of 2\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n \t}\n \n-\tif (!rte_is_power_of_2(dev->data->nb_rx_queues)) {\n-\t\tPMD_INIT_LOG(ERR, \"ERROR: Number of rx queues not power of 2\");\n-\t\treturn -EINVAL;\n+\t/* At this point, the number of queues requested has already\n+\t * been validated against dev_infos max queues by EAL\n+\t */\n+\tif (dev->data->nb_rx_queues > VMXNET3_MAX_RX_QUEUES ||\n+\t dev->data->nb_tx_queues > VMXNET3_MAX_TX_QUEUES) {\n+\t\thw->queuesExtEnabled = 1;\n+\t} else {\n+\t\thw->queuesExtEnabled = 0;\n \t}\n \n \tsize = dev->data->nb_rx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +\n@@ -627,9 +661,9 @@ vmxnet3_configure_msix(struct rte_eth_dev *dev)\n \t\treturn -1;\n \n \tintr_vector = dev->data->nb_rx_queues;\n-\tif (intr_vector > VMXNET3_MAX_RX_QUEUES) {\n+\tif (intr_vector > MAX_RX_QUEUES) {\n \t\tPMD_INIT_LOG(ERR, \"At most %d intr queues supported\",\n-\t\t\t VMXNET3_MAX_RX_QUEUES);\n+\t\t\t MAX_RX_QUEUES);\n \t\treturn -ENOTSUP;\n \t}\n \n@@ -777,6 +811,7 @@ vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)\n \tuint32_t mtu = dev->data->mtu;\n \tVmxnet3_DriverShared *shared = hw->shared;\n \tVmxnet3_DSDevRead *devRead = &shared->devRead;\n+\tstruct Vmxnet3_DSDevReadExt *devReadExt = &shared->devReadExt;\n \tuint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads;\n \tuint32_t i;\n \tint ret;\n@@ -853,13 +888,27 @@ vmxnet3_setup_driver_shared(struct rte_eth_dev *dev)\n \t}\n \n \t/* intr settings */\n-\tdevRead->intrConf.autoMask = hw->intr.mask_mode == VMXNET3_IMM_AUTO;\n-\tdevRead->intrConf.numIntrs = hw->intr.num_intrs;\n-\tfor (i = 0; i < hw->intr.num_intrs; i++)\n-\t\tdevRead->intrConf.modLevels[i] = hw->intr.mod_levels[i];\n+\tif (VMXNET3_VERSION_GE_6(hw) && hw->queuesExtEnabled) {\n+\t\tdevReadExt->intrConfExt.autoMask = hw->intr.mask_mode ==\n+\t\t\t\t\t\t VMXNET3_IMM_AUTO;\n+\t\tdevReadExt->intrConfExt.numIntrs = hw->intr.num_intrs;\n+\t\tfor (i = 0; i < hw->intr.num_intrs; i++)\n+\t\t\tdevReadExt->intrConfExt.modLevels[i] =\n+\t\t\t\thw->intr.mod_levels[i];\n+\n+\t\tdevReadExt->intrConfExt.eventIntrIdx = hw->intr.event_intr_idx;\n+\t\tdevReadExt->intrConfExt.intrCtrl |=\n+\t\t\trte_cpu_to_le_32(VMXNET3_IC_DISABLE_ALL);\n+\t} else {\n+\t\tdevRead->intrConf.autoMask = hw->intr.mask_mode ==\n+\t\t\t\t\t VMXNET3_IMM_AUTO;\n+\t\tdevRead->intrConf.numIntrs = hw->intr.num_intrs;\n+\t\tfor (i = 0; i < hw->intr.num_intrs; i++)\n+\t\t\tdevRead->intrConf.modLevels[i] = hw->intr.mod_levels[i];\n \n-\tdevRead->intrConf.eventIntrIdx = hw->intr.event_intr_idx;\n-\tdevRead->intrConf.intrCtrl |= rte_cpu_to_le_32(VMXNET3_IC_DISABLE_ALL);\n+\t\tdevRead->intrConf.eventIntrIdx = hw->intr.event_intr_idx;\n+\t\tdevRead->intrConf.intrCtrl |= rte_cpu_to_le_32(VMXNET3_IC_DISABLE_ALL);\n+\t}\n \n \t/* RxMode set to 0 of VMXNET3_RXM_xxx */\n \tdevRead->rxFilterConf.rxMode = 0;\n@@ -937,18 +986,24 @@ vmxnet3_dev_start(struct rte_eth_dev *dev)\n \t\treturn -EINVAL;\n \t}\n \n-\t/* Setup memory region for rx buffers */\n-\tret = vmxnet3_dev_setup_memreg(dev);\n-\tif (ret == 0) {\n-\t\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,\n-\t\t\t\t VMXNET3_CMD_REGISTER_MEMREGS);\n-\t\tret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);\n-\t\tif (ret != 0)\n-\t\t\tPMD_INIT_LOG(DEBUG,\n-\t\t\t\t \"Failed in setup memory region cmd\\n\");\n-\t\tret = 0;\n+\t/* Check memregs restrictions first */\n+\tif (dev->data->nb_rx_queues <= VMXNET3_MAX_RX_QUEUES &&\n+\t dev->data->nb_tx_queues <= VMXNET3_MAX_TX_QUEUES) {\n+\t\tret = vmxnet3_dev_setup_memreg(dev);\n+\t\tif (ret == 0) {\n+\t\t\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,\n+\t\t\t\t\tVMXNET3_CMD_REGISTER_MEMREGS);\n+\t\t\tret = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);\n+\t\t\tif (ret != 0)\n+\t\t\t\tPMD_INIT_LOG(DEBUG,\n+\t\t\t\t\t\"Failed in setup memory region cmd\\n\");\n+\t\t\tret = 0;\n+\t\t} else {\n+\t\t\tPMD_INIT_LOG(DEBUG, \"Failed to setup memory region\\n\");\n+\t\t}\n \t} else {\n-\t\tPMD_INIT_LOG(DEBUG, \"Failed to setup memory region\\n\");\n+\t\tPMD_INIT_LOG(WARNING, \"Memregs can't init (rx: %d, tx: %d)\",\n+\t\t\t dev->data->nb_rx_queues, dev->data->nb_tx_queues);\n \t}\n \n \tif (VMXNET3_VERSION_GE_4(hw) &&\n@@ -1203,8 +1258,6 @@ vmxnet3_hw_stats_save(struct vmxnet3_hw *hw)\n \n \tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);\n \n-\tRTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);\n-\n \tfor (i = 0; i < hw->num_tx_queues; i++)\n \t\tvmxnet3_hw_tx_stats_get(hw, i, &hw->saved_tx_stats[i]);\n \tfor (i = 0; i < hw->num_rx_queues; i++)\n@@ -1306,7 +1359,6 @@ vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n \n \tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD, VMXNET3_CMD_GET_STATS);\n \n-\tRTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_TX_QUEUES);\n \tfor (i = 0; i < hw->num_tx_queues; i++) {\n \t\tvmxnet3_tx_stats_get(hw, i, &txStats);\n \n@@ -1323,7 +1375,6 @@ vmxnet3_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)\n \t\tstats->oerrors += txStats.pktsTxError + txStats.pktsTxDiscard;\n \t}\n \n-\tRTE_BUILD_BUG_ON(RTE_ETHDEV_QUEUE_STAT_CNTRS < VMXNET3_MAX_RX_QUEUES);\n \tfor (i = 0; i < hw->num_rx_queues; i++) {\n \t\tvmxnet3_rx_stats_get(hw, i, &rxStats);\n \n@@ -1377,9 +1428,29 @@ vmxnet3_dev_info_get(struct rte_eth_dev *dev,\n \t\t struct rte_eth_dev_info *dev_info)\n {\n \tstruct vmxnet3_hw *hw = dev->data->dev_private;\n+\tint queues = 0;\n+\n+\tif (VMXNET3_VERSION_GE_6(hw)) {\n+\t\tVMXNET3_WRITE_BAR1_REG(hw, VMXNET3_REG_CMD,\n+\t\t\t\t VMXNET3_CMD_GET_MAX_QUEUES_CONF);\n+\t\tqueues = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_CMD);\n+\n+\t\tif (queues > 0) {\n+#define MIN(x, y) (((x) < (y)) ? (x) : (y))\n+\t\t\tdev_info->max_rx_queues =\n+\t\t\t MIN(VMXNET3_EXT_MAX_RX_QUEUES, ((queues >> 8) & 0xff));\n+\t\t\tdev_info->max_tx_queues =\n+\t\t\t MIN(VMXNET3_EXT_MAX_TX_QUEUES, (queues & 0xff));\n+#undef MIN\n+\t\t} else {\n+\t\t\tdev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;\n+\t\t\tdev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;\n+\t\t}\n+\t} else {\n+\t\tdev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;\n+\t\tdev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;\n+\t}\n \n-\tdev_info->max_rx_queues = VMXNET3_MAX_RX_QUEUES;\n-\tdev_info->max_tx_queues = VMXNET3_MAX_TX_QUEUES;\n \tdev_info->min_rx_bufsize = 1518 + RTE_PKTMBUF_HEADROOM;\n \tdev_info->max_rx_pktlen = 16384; /* includes CRC, cf MAXFRS register */\n \tdev_info->min_mtu = VMXNET3_MIN_MTU;\n@@ -1430,24 +1501,50 @@ vmxnet3_dev_supported_ptypes_get(struct rte_eth_dev *dev)\n }\n \n static int\n-vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, __rte_unused uint16_t mtu)\n+vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)\n {\n-\tif (dev->data->dev_started) {\n-\t\tPMD_DRV_LOG(ERR, \"Port %d must be stopped to configure MTU\",\n-\t\t\t dev->data->port_id);\n-\t\treturn -EBUSY;\n-\t}\n+\tstruct vmxnet3_hw *hw = dev->data->dev_private;\n \n+\trte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)(hw->perm_addr));\n+\tvmxnet3_write_mac(hw, mac_addr->addr_bytes);\n \treturn 0;\n }\n \n static int\n-vmxnet3_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr)\n+vmxnet3_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)\n {\n \tstruct vmxnet3_hw *hw = dev->data->dev_private;\n+\tuint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 4;\n+\n+\tif (mtu < VMXNET3_MIN_MTU)\n+\t\treturn -EINVAL;\n+\n+\tif (VMXNET3_VERSION_GE_6(hw)) {\n+\t\tif (mtu > VMXNET3_V6_MAX_MTU)\n+\t\t\treturn -EINVAL;\n+\t} else {\n+\t\tif (mtu > VMXNET3_MAX_MTU) {\n+\t\t\tPMD_DRV_LOG(ERR, \"MTU %d too large in device version v%d\",\n+\t\t\t\t mtu, hw->version);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\tdev->data->mtu = mtu;\n+\t/* update max frame size */\n+\tdev->data->dev_conf.rxmode.mtu = frame_size;\n+\n+\tif (dev->data->dev_started == 0)\n+\t\treturn 0;\n+\n+ /* changing mtu for vmxnet3 pmd does not require a restart\n+ * as it does not need to repopulate the rx rings to support\n+ * different mtu size. We stop and restart the device here\n+ * just to pass the mtu info to the backend.\n+ */\n+\tvmxnet3_dev_stop(dev);\n+\tvmxnet3_dev_start(dev);\n \n-\trte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)(hw->perm_addr));\n-\tvmxnet3_write_mac(hw, mac_addr->addr_bytes);\n \treturn 0;\n }\n \n@@ -1668,11 +1765,14 @@ vmxnet3_interrupt_handler(void *param)\n {\n \tstruct rte_eth_dev *dev = param;\n \tstruct vmxnet3_hw *hw = dev->data->dev_private;\n-\tVmxnet3_DSDevRead *devRead = &hw->shared->devRead;\n \tuint32_t events;\n+\tuint8 *eventIntrIdx;\n+\tuint32 *intrCtrl;\n \n \tPMD_INIT_FUNC_TRACE();\n-\tvmxnet3_disable_intr(hw, devRead->intrConf.eventIntrIdx);\n+\n+\tvmxnet3_get_intr_ctrl_ev(hw, &eventIntrIdx, &intrCtrl);\n+\tvmxnet3_disable_intr(hw, *eventIntrIdx);\n \n \tevents = VMXNET3_READ_BAR1_REG(hw, VMXNET3_REG_ECR);\n \tif (events == 0)\n@@ -1681,7 +1781,7 @@ vmxnet3_interrupt_handler(void *param)\n \tRTE_LOG(DEBUG, PMD, \"Reading events: 0x%X\", events);\n \tvmxnet3_process_events(dev);\n done:\n-\tvmxnet3_enable_intr(hw, devRead->intrConf.eventIntrIdx);\n+\tvmxnet3_enable_intr(hw, *eventIntrIdx);\n }\n \n static int\ndiff --git a/drivers/net/vmxnet3/vmxnet3_ethdev.h b/drivers/net/vmxnet3/vmxnet3_ethdev.h\nindex ceaeb66392..5a303717b1 100644\n--- a/drivers/net/vmxnet3/vmxnet3_ethdev.h\n+++ b/drivers/net/vmxnet3/vmxnet3_ethdev.h\n@@ -70,7 +70,7 @@ struct vmxnet3_intr {\n \tenum vmxnet3_intr_type type; /* MSI-X, MSI, or INTx? */\n \tuint8_t num_intrs; /* # of intr vectors */\n \tuint8_t event_intr_idx; /* idx of the intr vector for event */\n-\tuint8_t mod_levels[VMXNET3_MAX_MSIX_VECT]; /* moderation level */\n+\tuint8_t mod_levels[VMXNET3_EXT_MAX_INTRS]; /* moderation level */\n \tbool lsc_only; /* no Rx queue interrupt */\n };\n \n@@ -108,6 +108,7 @@ struct vmxnet3_hw {\n \tuint64_t queueDescPA;\n \tuint16_t queue_desc_len;\n \tuint16_t mtu;\n+\tbool queuesExtEnabled;\n \n \tVMXNET3_RSSConf *rss_conf;\n \tuint64_t rss_confPA;\n@@ -117,19 +118,20 @@ struct vmxnet3_hw {\n \tVmxnet3_MemRegs\t *memRegs;\n \tuint64_t\t memRegsPA;\n #define VMXNET3_VFT_TABLE_SIZE (VMXNET3_VFT_SIZE * sizeof(uint32_t))\n-\tUPT1_TxStats\t saved_tx_stats[VMXNET3_MAX_TX_QUEUES];\n-\tUPT1_RxStats\t saved_rx_stats[VMXNET3_MAX_RX_QUEUES];\n-\n+\tUPT1_TxStats\t saved_tx_stats[VMXNET3_EXT_MAX_TX_QUEUES];\n+\tUPT1_RxStats\t saved_rx_stats[VMXNET3_EXT_MAX_RX_QUEUES];\n \tUPT1_TxStats snapshot_tx_stats[VMXNET3_MAX_TX_QUEUES];\n \tUPT1_RxStats snapshot_rx_stats[VMXNET3_MAX_RX_QUEUES];\n };\n \n+#define VMXNET3_REV_6\t\t5\t\t/* Vmxnet3 Rev. 6 */\n #define VMXNET3_REV_5\t\t4\t\t/* Vmxnet3 Rev. 5 */\n #define VMXNET3_REV_4\t\t3\t\t/* Vmxnet3 Rev. 4 */\n #define VMXNET3_REV_3\t\t2\t\t/* Vmxnet3 Rev. 3 */\n #define VMXNET3_REV_2\t\t1\t\t/* Vmxnet3 Rev. 2 */\n #define VMXNET3_REV_1\t\t0\t\t/* Vmxnet3 Rev. 1 */\n \n+#define VMXNET3_VERSION_GE_6(hw) ((hw)->version >= VMXNET3_REV_6 + 1)\n #define VMXNET3_VERSION_GE_5(hw) ((hw)->version >= VMXNET3_REV_5 + 1)\n #define VMXNET3_VERSION_GE_4(hw) ((hw)->version >= VMXNET3_REV_4 + 1)\n #define VMXNET3_VERSION_GE_3(hw) ((hw)->version >= VMXNET3_REV_3 + 1)\ndiff --git a/drivers/net/vmxnet3/vmxnet3_rxtx.c b/drivers/net/vmxnet3/vmxnet3_rxtx.c\nindex e15b377d8c..a6665fbf70 100644\n--- a/drivers/net/vmxnet3/vmxnet3_rxtx.c\n+++ b/drivers/net/vmxnet3/vmxnet3_rxtx.c\n@@ -1400,7 +1400,7 @@ vmxnet3_rss_configure(struct rte_eth_dev *dev)\n \t/* loading hashKeySize */\n \tdev_rss_conf->hashKeySize = VMXNET3_RSS_MAX_KEY_SIZE;\n \t/* loading indTableSize: Must not exceed VMXNET3_RSS_MAX_IND_TABLE_SIZE (128)*/\n-\tdev_rss_conf->indTableSize = (uint16_t)(hw->num_rx_queues * 4);\n+\tdev_rss_conf->indTableSize = (uint16_t)(MAX_RX_QUEUES * 4);\n \n \tif (port_rss_conf->rss_key == NULL) {\n \t\t/* Default hash key */\n", "prefixes": [ "5/8" ] }