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GET /api/patches/110169/?format=api
{ "id": 110169, "url": "http://patches.dpdk.org/api/patches/110169/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220422104709.20722-26-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220422104709.20722-26-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220422104709.20722-26-ndabilpuram@marvell.com", "date": "2022-04-22T10:47:07", "name": "[v2,26/28] common/cnxk: allow lesser inline inbound sa sizes", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "dfb47cbcb371f751a3f80abecf7269da3db88094", "submitter": { "id": 1202, "url": "http://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220422104709.20722-26-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 22634, "url": "http://patches.dpdk.org/api/series/22634/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22634", "date": "2022-04-22T10:46:42", "name": "[v2,01/28] common/cnxk: add multi channel support for SDP send queues", "version": 2, "mbox": "http://patches.dpdk.org/series/22634/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/110169/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/110169/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D9D53A0093;\n\tFri, 22 Apr 2022 12:49:46 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4877341611;\n\tFri, 22 Apr 2022 12:48:32 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id EE35A42815\n for <dev@dpdk.org>; Fri, 22 Apr 2022 12:48:29 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with ESMTP id\n 23M0SDFi003220\n for <dev@dpdk.org>; Fri, 22 Apr 2022 03:48:29 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3fk7mk44eh-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 22 Apr 2022 03:48:29 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Fri, 22 Apr 2022 03:48:27 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Fri, 22 Apr 2022 03:48:27 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id A12ED3F707F;\n Fri, 22 Apr 2022 03:48:25 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=xMb7f20uPoE1i3Sa3+qnglg4TONtAPLjhfi2rMEG+Kc=;\n b=TS0ObJZ2X0q7lBfyrjfjSdm1KFgm4kUOXP3UJbdoJ6v0lDXYCY+XFSbn1I88HnkzbNVw\n 2PyZN64vC/pJ4owboC0lfD52R+YhUD55jTFAdCyKEE1hzHXyQIsdkh1UyXgypyjdm0QG\n ZVmd/V/hJ0j/9twsftqElDQEEWdhVyp+MbF3O30SmbGnDUo0VyPpCVqBG2Xfe1oKIdcn\n WWUnyruOCvns/4oUt0ZARmJvUxHvhf1NFL9BJ33O5ZSCeQAzh9gnE6pdx0WLMVSY3GRT\n IZMCpgP24CM92d7QGuSSZ13iAocZwgYVgmlxmdwPUJvrZn9i2xHpKdD/GPoWgXHRW0be GA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "<jerinj@marvell.com>, Nithin Dabilpuram <ndabilpuram@marvell.com>, \"Kiran\n Kumar K\" <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>,\n Satha Rao <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH v2 26/28] common/cnxk: allow lesser inline inbound sa sizes", "Date": "Fri, 22 Apr 2022 16:17:07 +0530", "Message-ID": "<20220422104709.20722-26-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20220422104709.20722-1-ndabilpuram@marvell.com>", "References": "<20220422104709.20722-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "RO9R5pFUs_ljrtUbKLW0jWZhqTXFFdXa", "X-Proofpoint-GUID": "RO9R5pFUs_ljrtUbKLW0jWZhqTXFFdXa", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514\n definitions=2022-04-22_02,2022-04-22_01,2022-02-23_01", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Restructure SA setup to allow lesser inbound SA sizes as opposed\nto full Inbound SA size of 1024B with max possible Anti-Replay\nwindow. Since inbound SA size is variable, move the memset logic\nout of common code.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/roc_ie_ot.c | 4 ----\n drivers/common/cnxk/roc_nix_inl.c | 9 ++++++++-\n drivers/common/cnxk/roc_nix_inl.h | 26 +++++++++++++++++++++++---\n 3 files changed, 31 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/roc_ie_ot.c b/drivers/common/cnxk/roc_ie_ot.c\nindex d0b7ad3..4b5823d 100644\n--- a/drivers/common/cnxk/roc_ie_ot.c\n+++ b/drivers/common/cnxk/roc_ie_ot.c\n@@ -10,8 +10,6 @@ roc_ot_ipsec_inb_sa_init(struct roc_ot_ipsec_inb_sa *sa, bool is_inline)\n {\n \tsize_t offset;\n \n-\tmemset(sa, 0, sizeof(struct roc_ot_ipsec_inb_sa));\n-\n \tif (is_inline) {\n \t\tsa->w0.s.pkt_output = ROC_IE_OT_SA_PKT_OUTPUT_NO_FRAG;\n \t\tsa->w0.s.pkt_format = ROC_IE_OT_SA_PKT_FMT_META;\n@@ -33,8 +31,6 @@ roc_ot_ipsec_outb_sa_init(struct roc_ot_ipsec_outb_sa *sa)\n {\n \tsize_t offset;\n \n-\tmemset(sa, 0, sizeof(struct roc_ot_ipsec_outb_sa));\n-\n \toffset = offsetof(struct roc_ot_ipsec_outb_sa, ctx);\n \tsa->w0.s.ctx_push_size = (offset / ROC_CTX_UNIT_8B) + 1;\n \tsa->w0.s.ctx_size = ROC_IE_OT_CTX_ILEN;\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex 2c013cb..887d4ad 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -14,9 +14,16 @@ PLT_STATIC_ASSERT(ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ ==\n \t\t 1UL << ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2);\n PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ ==\n \t\t 1UL << ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2);\n-PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ == 1024);\n PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ ==\n \t\t 1UL << ROC_NIX_INL_OT_IPSEC_OUTB_SA_SZ_LOG2);\n+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ >=\n+\t\t ROC_NIX_INL_OT_IPSEC_INB_HW_SZ +\n+\t\t\t ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD);\n+/* Allow lesser INB SA HW sizes */\n+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_INB_HW_SZ <=\n+\t\t PLT_ALIGN(sizeof(struct roc_ot_ipsec_inb_sa), ROC_ALIGN));\n+PLT_STATIC_ASSERT(ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ ==\n+\t\t PLT_ALIGN(sizeof(struct roc_ot_ipsec_outb_sa), ROC_ALIGN));\n \n static int\n nix_inl_inb_sa_tbl_setup(struct roc_nix *roc_nix)\ndiff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nindex 633f090..e7bcffc 100644\n--- a/drivers/common/cnxk/roc_nix_inl.h\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -23,13 +23,33 @@\n #define ROC_NIX_INL_ONF_IPSEC_OUTB_SA_SZ_LOG2 8\n \n /* OT INB HW area */\n+#ifndef ROC_NIX_INL_OT_IPSEC_AR_WIN_SZ_MAX\n+#define ROC_NIX_INL_OT_IPSEC_AR_WIN_SZ_MAX 4096u\n+#endif\n+#define ROC_NIX_INL_OT_IPSEC_AR_WINBITS_SZ \\\n+\t(PLT_ALIGN_CEIL(ROC_NIX_INL_OT_IPSEC_AR_WIN_SZ_MAX, \\\n+\t\t\tBITS_PER_LONG_LONG) / \\\n+\t BITS_PER_LONG_LONG)\n+#define __ROC_NIX_INL_OT_IPSEC_INB_HW_SZ \\\n+\t(offsetof(struct roc_ot_ipsec_inb_sa, ctx.ar_winbits) + \\\n+\t sizeof(uint64_t) * ROC_NIX_INL_OT_IPSEC_AR_WINBITS_SZ)\n #define ROC_NIX_INL_OT_IPSEC_INB_HW_SZ \\\n-\tPLT_ALIGN(sizeof(struct roc_ot_ipsec_inb_sa), ROC_ALIGN)\n+\tPLT_ALIGN(__ROC_NIX_INL_OT_IPSEC_INB_HW_SZ, ROC_ALIGN)\n /* OT INB SW reserved area */\n+#ifndef ROC_NIX_INL_INB_POST_PROCESS\n+#define ROC_NIX_INL_INB_POST_PROCESS 1\n+#endif\n+#if ROC_NIX_INL_INB_POST_PROCESS == 0\n+#define ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD 0\n+#else\n #define ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD 128\n+#endif\n+\n #define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ \\\n-\t(ROC_NIX_INL_OT_IPSEC_INB_HW_SZ + ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD)\n-#define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2 10\n+\t(1UL << (64 - __builtin_clzll(ROC_NIX_INL_OT_IPSEC_INB_HW_SZ + \\\n+\t\t\t\t ROC_NIX_INL_OT_IPSEC_INB_SW_RSVD - 1)))\n+#define ROC_NIX_INL_OT_IPSEC_INB_SA_SZ_LOG2 \\\n+\t__builtin_ctzll(ROC_NIX_INL_OT_IPSEC_INB_SA_SZ)\n \n /* OT OUTB HW area */\n #define ROC_NIX_INL_OT_IPSEC_OUTB_HW_SZ \\\n", "prefixes": [ "v2", "26/28" ] }