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GET /api/patches/109387/?format=api
{ "id": 109387, "url": "http://patches.dpdk.org/api/patches/109387/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/patch/20220407105706.18889-36-kevinx.liu@intel.com/", "project": { "id": 1, "url": "http://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20220407105706.18889-36-kevinx.liu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20220407105706.18889-36-kevinx.liu@intel.com", "date": "2022-04-07T10:57:02", "name": "[35/39] net/ice: enable IRQ mapping configuration for large VF", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a790c6d8ef132c7b3ec3e196fd22d687f6a62eaf", "submitter": { "id": 2440, "url": "http://patches.dpdk.org/api/people/2440/?format=api", "name": "Kevin Liu", "email": "kevinx.liu@intel.com" }, "delegate": { "id": 1540, "url": "http://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patches.dpdk.org/project/dpdk/patch/20220407105706.18889-36-kevinx.liu@intel.com/mbox/", "series": [ { "id": 22387, "url": "http://patches.dpdk.org/api/series/22387/?format=api", "web_url": "http://patches.dpdk.org/project/dpdk/list/?series=22387", "date": "2022-04-07T10:56:27", "name": "support full function of DCF", "version": 1, "mbox": "http://patches.dpdk.org/series/22387/mbox/" } ], "comments": "http://patches.dpdk.org/api/patches/109387/comments/", "check": "success", "checks": "http://patches.dpdk.org/api/patches/109387/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id DB400A0508;\n\tThu, 7 Apr 2022 05:01:38 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B077642893;\n\tThu, 7 Apr 2022 04:59:54 +0200 (CEST)", "from mga02.intel.com (mga02.intel.com [134.134.136.20])\n by mails.dpdk.org (Postfix) with ESMTP id 7A83E428D5\n for <dev@dpdk.org>; Thu, 7 Apr 2022 04:59:52 +0200 (CEST)", "from orsmga008.jf.intel.com ([10.7.209.65])\n by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 06 Apr 2022 19:59:52 -0700", "from intel-cd-odc-kevin.cd.intel.com ([10.240.178.195])\n by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 06 Apr 2022 19:59:49 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1649300392; x=1680836392;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=mUlwG4P1npA//qHv8ipnUHwxjbIWgcR5/tLdwp57zKg=;\n b=Cn1Q/3iUALMU5OjNkmZOnIuFn5OjYirISsjCjInhTmhl1F2X2stdJT3G\n AOCTAcQADpXptuZEET5XiWKnisvjmhWP5vd0ACBJGnDCdeZBpXnPmFqwl\n ZE2NUmPETNwzodOzcd1Pl+hP6DIaDR1nZXGgQq4QO8crLXcYf9QxkiHjv\n PB7YtoCzNuK+AISp1/9SA+hOi1p69EZiKzgJcjB4OcxFpizpu1OoNXOXZ\n grA+/3lj3dk9xKoTfWHoppaTjcMH+yJoUfsib1lWH0eKTo4hLigGKnbpZ\n vDkcbGF4Jlxw+DAyTykreDWtOlRuQBH6fGAywHSjQD+LsIbGxsFG23n1w w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10309\"; a=\"248738509\"", "E=Sophos;i=\"5.90,241,1643702400\"; d=\"scan'208\";a=\"248738509\"", "E=Sophos;i=\"5.90,241,1643702400\"; d=\"scan'208\";a=\"570850832\"" ], "From": "Kevin Liu <kevinx.liu@intel.com>", "To": "dev@dpdk.org", "Cc": "qiming.yang@intel.com, qi.z.zhang@intel.com, stevex.yang@intel.com,\n Kevin Liu <kevinx.liu@intel.com>", "Subject": "[PATCH 35/39] net/ice: enable IRQ mapping configuration for large VF", "Date": "Thu, 7 Apr 2022 10:57:02 +0000", "Message-Id": "<20220407105706.18889-36-kevinx.liu@intel.com>", "X-Mailer": "git-send-email 2.33.1", "In-Reply-To": "<20220407105706.18889-1-kevinx.liu@intel.com>", "References": "<20220407105706.18889-1-kevinx.liu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Steve Yang <stevex.yang@intel.com>\n\nThe current IRQ mapping configuration only supports max 16 queues and\n16 MSIX vectors. Change the queue vector mapping structure to indicate\nup to 256 queues. A new opcode is used to handle the case with large\nnumber of queues. To avoid adminq buffer size limitation, we support\nto send the virtchnl message multiple times if needed.\n\nSigned-off-by: Steve Yang <stevex.yang@intel.com>\nSigned-off-by: Kevin Liu <kevinx.liu@intel.com>\n---\n drivers/net/ice/ice_dcf.c | 50 +++++++++++++++++++++++++++----\n drivers/net/ice/ice_dcf.h | 10 ++++++-\n drivers/net/ice/ice_dcf_ethdev.c | 51 +++++++++++++++++++++++++++-----\n drivers/net/ice/ice_dcf_ethdev.h | 1 +\n 4 files changed, 99 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c\nindex 7a0a9a3534..90af99f8d0 100644\n--- a/drivers/net/ice/ice_dcf.c\n+++ b/drivers/net/ice/ice_dcf.c\n@@ -1116,7 +1116,6 @@ ice_dcf_get_max_rss_queue_region(struct ice_dcf_hw *hw)\n \treturn 0;\n }\n \n-\n int\n ice_dcf_config_irq_map(struct ice_dcf_hw *hw)\n {\n@@ -1133,13 +1132,14 @@ ice_dcf_config_irq_map(struct ice_dcf_hw *hw)\n \t\treturn -ENOMEM;\n \n \tmap_info->num_vectors = hw->nb_msix;\n-\tfor (i = 0; i < hw->nb_msix; i++) {\n-\t\tvecmap = &map_info->vecmap[i];\n+\tfor (i = 0; i < hw->eth_dev->data->nb_rx_queues; i++) {\n+\t\tvecmap =\n+\t\t &map_info->vecmap[hw->qv_map[i].vector_id - hw->msix_base];\n \t\tvecmap->vsi_id = hw->vsi_res->vsi_id;\n \t\tvecmap->rxitr_idx = 0;\n-\t\tvecmap->vector_id = hw->msix_base + i;\n+\t\tvecmap->vector_id = hw->qv_map[i].vector_id;\n \t\tvecmap->txq_map = 0;\n-\t\tvecmap->rxq_map = hw->rxq_map[hw->msix_base + i];\n+\t\tvecmap->rxq_map |= 1 << hw->qv_map[i].queue_id;\n \t}\n \n \tmemset(&args, 0, sizeof(args));\n@@ -1155,6 +1155,46 @@ ice_dcf_config_irq_map(struct ice_dcf_hw *hw)\n \treturn err;\n }\n \n+int\n+ice_dcf_config_irq_map_lv(struct ice_dcf_hw *hw,\n+\t\t uint16_t num, uint16_t index)\n+{\n+\tstruct virtchnl_queue_vector_maps *map_info;\n+\tstruct virtchnl_queue_vector *qv_maps;\n+\tstruct dcf_virtchnl_cmd args;\n+\tint len, i, err;\n+\tint count = 0;\n+\n+\tlen = sizeof(struct virtchnl_queue_vector_maps) +\n+\t sizeof(struct virtchnl_queue_vector) * (num - 1);\n+\n+\tmap_info = rte_zmalloc(\"map_info\", len, 0);\n+\tif (!map_info)\n+\t\treturn -ENOMEM;\n+\n+\tmap_info->vport_id = hw->vsi_res->vsi_id;\n+\tmap_info->num_qv_maps = num;\n+\tfor (i = index; i < index + map_info->num_qv_maps; i++) {\n+\t\tqv_maps = &map_info->qv_maps[count++];\n+\t\tqv_maps->itr_idx = VIRTCHNL_ITR_IDX_0;\n+\t\tqv_maps->queue_type = VIRTCHNL_QUEUE_TYPE_RX;\n+\t\tqv_maps->queue_id = hw->qv_map[i].queue_id;\n+\t\tqv_maps->vector_id = hw->qv_map[i].vector_id;\n+\t}\n+\n+\targs.v_op = VIRTCHNL_OP_MAP_QUEUE_VECTOR;\n+\targs.req_msg = (u8 *)map_info;\n+\targs.req_msglen = len;\n+\targs.rsp_msgbuf = hw->arq_buf;\n+\targs.req_msglen = ICE_DCF_AQ_BUF_SZ;\n+\terr = ice_dcf_execute_virtchnl_cmd(hw, &args);\n+\tif (err)\n+\t\tPMD_DRV_LOG(ERR, \"fail to execute command OP_MAP_QUEUE_VECTOR\");\n+\n+\trte_free(map_info);\n+\treturn err;\n+}\n+\n int\n ice_dcf_switch_queue(struct ice_dcf_hw *hw, uint16_t qid, bool rx, bool on)\n {\ndiff --git a/drivers/net/ice/ice_dcf.h b/drivers/net/ice/ice_dcf.h\nindex 1f45881315..bd88424034 100644\n--- a/drivers/net/ice/ice_dcf.h\n+++ b/drivers/net/ice/ice_dcf.h\n@@ -74,6 +74,11 @@ struct ice_dcf_tm_conf {\n \tbool committed;\n };\n \n+struct ice_dcf_qv_map {\n+\tuint16_t queue_id;\n+\tuint16_t vector_id;\n+};\n+\n struct ice_dcf_hw {\n \tstruct iavf_hw avf;\n \n@@ -108,7 +113,8 @@ struct ice_dcf_hw {\n \tuint16_t msix_base;\n \tuint16_t nb_msix;\n \tuint16_t max_rss_qregion; /* max RSS queue region supported by PF */\n-\tuint16_t rxq_map[16];\n+\n+\tstruct ice_dcf_qv_map *qv_map; /* queue vector mapping */\n \tstruct virtchnl_eth_stats eth_stats_offset;\n \tstruct virtchnl_vlan_caps vlan_v2_caps;\n \n@@ -136,6 +142,8 @@ int ice_dcf_configure_queues(struct ice_dcf_hw *hw,\n int ice_dcf_request_queues(struct ice_dcf_hw *hw, uint16_t num);\n int ice_dcf_get_max_rss_queue_region(struct ice_dcf_hw *hw);\n int ice_dcf_config_irq_map(struct ice_dcf_hw *hw);\n+int ice_dcf_config_irq_map_lv(struct ice_dcf_hw *hw,\n+\t\t\t uint16_t num, uint16_t index);\n int ice_dcf_switch_queue(struct ice_dcf_hw *hw, uint16_t qid, bool rx, bool on);\n int ice_dcf_disable_queues(struct ice_dcf_hw *hw);\n int ice_dcf_query_stats(struct ice_dcf_hw *hw,\ndiff --git a/drivers/net/ice/ice_dcf_ethdev.c b/drivers/net/ice/ice_dcf_ethdev.c\nindex 211a2510fa..82d97fd049 100644\n--- a/drivers/net/ice/ice_dcf_ethdev.c\n+++ b/drivers/net/ice/ice_dcf_ethdev.c\n@@ -144,6 +144,7 @@ ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev,\n {\n \tstruct ice_dcf_adapter *adapter = dev->data->dev_private;\n \tstruct ice_dcf_hw *hw = &adapter->real_hw;\n+\tstruct ice_dcf_qv_map *qv_map;\n \tuint16_t interval, i;\n \tint vec;\n \n@@ -162,6 +163,14 @@ ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev,\n \t\t}\n \t}\n \n+\tqv_map = rte_zmalloc(\"qv_map\",\n+\t\tdev->data->nb_rx_queues * sizeof(struct ice_dcf_qv_map), 0);\n+\tif (!qv_map) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to allocate %d queue-vector map\",\n+\t\t\t\tdev->data->nb_rx_queues);\n+\t\treturn -1;\n+\t}\n+\n \tif (!dev->data->dev_conf.intr_conf.rxq ||\n \t !rte_intr_dp_is_en(intr_handle)) {\n \t\t/* Rx interrupt disabled, Map interrupt only for writeback */\n@@ -197,17 +206,22 @@ ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev,\n \t\t}\n \t\tIAVF_WRITE_FLUSH(&hw->avf);\n \t\t/* map all queues to the same interrupt */\n-\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++)\n-\t\t\thw->rxq_map[hw->msix_base] |= 1 << i;\n+\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n+\t\t\tqv_map[i].queue_id = i;\n+\t\t\tqv_map[i].vector_id = hw->msix_base;\n+\t\t}\n+\t\thw->qv_map = qv_map;\n \t} else {\n \t\tif (!rte_intr_allow_others(intr_handle)) {\n \t\t\thw->nb_msix = 1;\n \t\t\thw->msix_base = IAVF_MISC_VEC_ID;\n \t\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n-\t\t\t\thw->rxq_map[hw->msix_base] |= 1 << i;\n+\t\t\t\tqv_map[i].queue_id = i;\n+\t\t\t\tqv_map[i].vector_id = hw->msix_base;\n \t\t\t\trte_intr_vec_list_index_set(intr_handle,\n \t\t\t\t\t\t\ti, IAVF_MISC_VEC_ID);\n \t\t\t}\n+\t\t\thw->qv_map = qv_map;\n \t\t\tPMD_DRV_LOG(DEBUG,\n \t\t\t\t \"vector %u are mapping to all Rx queues\",\n \t\t\t\t hw->msix_base);\n@@ -220,21 +234,44 @@ ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev,\n \t\t\thw->msix_base = IAVF_MISC_VEC_ID;\n \t\t\tvec = IAVF_MISC_VEC_ID;\n \t\t\tfor (i = 0; i < dev->data->nb_rx_queues; i++) {\n-\t\t\t\thw->rxq_map[vec] |= 1 << i;\n+\t\t\t\tqv_map[i].queue_id = i;\n+\t\t\t\tqv_map[i].vector_id = vec;\n \t\t\t\trte_intr_vec_list_index_set(intr_handle,\n \t\t\t\t\t\t\t\t i, vec++);\n \t\t\t\tif (vec >= hw->nb_msix)\n \t\t\t\t\tvec = IAVF_RX_VEC_START;\n \t\t\t}\n+\t\t\thw->qv_map = qv_map;\n \t\t\tPMD_DRV_LOG(DEBUG,\n \t\t\t\t \"%u vectors are mapping to %u Rx queues\",\n \t\t\t\t hw->nb_msix, dev->data->nb_rx_queues);\n \t\t}\n \t}\n \n-\tif (ice_dcf_config_irq_map(hw)) {\n-\t\tPMD_DRV_LOG(ERR, \"config interrupt mapping failed\");\n-\t\treturn -1;\n+\tif (!hw->lv_enabled) {\n+\t\tif (ice_dcf_config_irq_map(hw)) {\n+\t\t\tPMD_DRV_LOG(ERR, \"config interrupt mapping failed\");\n+\t\t\treturn -1;\n+\t\t}\n+\t} else {\n+\t\tuint16_t num_qv_maps = dev->data->nb_rx_queues;\n+\t\tuint16_t index = 0;\n+\n+\t\twhile (num_qv_maps > ICE_DCF_IRQ_MAP_NUM_PER_BUF) {\n+\t\t\tif (ice_dcf_config_irq_map_lv(hw,\n+\t\t\t\t\tICE_DCF_IRQ_MAP_NUM_PER_BUF, index)) {\n+\t\t\t\tPMD_DRV_LOG(ERR, \"config interrupt mapping for large VF failed\");\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t\tnum_qv_maps -= ICE_DCF_IRQ_MAP_NUM_PER_BUF;\n+\t\t\tindex += ICE_DCF_IRQ_MAP_NUM_PER_BUF;\n+\t\t}\n+\n+\t\tif (ice_dcf_config_irq_map_lv(hw, num_qv_maps, index)) {\n+\t\t\tPMD_DRV_LOG(ERR, \"config interrupt mapping for large VF failed\");\n+\t\t\treturn -1;\n+\t\t}\n+\n \t}\n \treturn 0;\n }\ndiff --git a/drivers/net/ice/ice_dcf_ethdev.h b/drivers/net/ice/ice_dcf_ethdev.h\nindex 2fac1e5b21..9ef524c97c 100644\n--- a/drivers/net/ice/ice_dcf_ethdev.h\n+++ b/drivers/net/ice/ice_dcf_ethdev.h\n@@ -23,6 +23,7 @@\n #define ICE_DCF_MAX_NUM_QUEUES_DFLT 16\n #define ICE_DCF_MAX_NUM_QUEUES_LV 256\n #define ICE_DCF_CFG_Q_NUM_PER_BUF 32\n+#define ICE_DCF_IRQ_MAP_NUM_PER_BUF 128\n \n struct ice_dcf_queue {\n \tuint64_t dummy;\n", "prefixes": [ "35/39" ] }